watchdog: lantiq: access boot cause register through regmap
This patch avoids accessing the function ltq_reset_cause() and directly accesses the register given over the syscon interface. The syscon interface will be implemented for the xway SoCs for the falcon SoCs the ltq_reset_cause() function never worked, because a wrong offset was used. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Acked-by: Guenter Roeck <linux@reck-us.net> Cc: martin.blumenstingl@googlemail.com Cc: john@phrozen.org Cc: robh@kernel.org Cc: andy.shevchenko@gmail.com Cc: p.zabel@pengutronix.de Cc: kishon@ti.com Cc: mark.rutland@arm.com Cc: linux-mips@linux-mips.org Cc: linux-mtd@lists.infradead.org Cc: linux-watchdog@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-spi@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17123/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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710322ba8c
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@ -4,6 +4,7 @@
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* by the Free Software Foundation.
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*
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* Copyright (C) 2010 John Crispin <john@phrozen.org>
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* Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
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* Based on EP93xx wdt driver
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*/
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@ -17,9 +18,20 @@
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#include <linux/uaccess.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#include <lantiq_soc.h>
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#define LTQ_XRX_RCU_RST_STAT 0x0014
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#define LTQ_XRX_RCU_RST_STAT_WDT BIT(31)
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/* CPU0 Reset Source Register */
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#define LTQ_FALCON_SYS1_CPU0RS 0x0060
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/* reset cause mask */
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#define LTQ_FALCON_SYS1_CPU0RS_MASK 0x0007
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#define LTQ_FALCON_SYS1_CPU0RS_WDT 0x02
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/*
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* Section 3.4 of the datasheet
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* The password sequence protects the WDT control register from unintended
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@ -186,16 +198,70 @@ static struct miscdevice ltq_wdt_miscdev = {
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.fops = <q_wdt_fops,
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};
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typedef int (*ltq_wdt_bootstatus_set)(struct platform_device *pdev);
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static int ltq_wdt_bootstatus_xrx(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct regmap *rcu_regmap;
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u32 val;
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int err;
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rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "regmap");
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if (IS_ERR(rcu_regmap))
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return PTR_ERR(rcu_regmap);
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err = regmap_read(rcu_regmap, LTQ_XRX_RCU_RST_STAT, &val);
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if (err)
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return err;
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if (val & LTQ_XRX_RCU_RST_STAT_WDT)
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ltq_wdt_bootstatus = WDIOF_CARDRESET;
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return 0;
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}
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static int ltq_wdt_bootstatus_falcon(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct regmap *rcu_regmap;
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u32 val;
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int err;
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rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
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"lantiq,rcu");
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if (IS_ERR(rcu_regmap))
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return PTR_ERR(rcu_regmap);
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err = regmap_read(rcu_regmap, LTQ_FALCON_SYS1_CPU0RS, &val);
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if (err)
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return err;
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if ((val & LTQ_FALCON_SYS1_CPU0RS_MASK) == LTQ_FALCON_SYS1_CPU0RS_WDT)
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ltq_wdt_bootstatus = WDIOF_CARDRESET;
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return 0;
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}
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static int
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ltq_wdt_probe(struct platform_device *pdev)
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{
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struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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struct clk *clk;
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ltq_wdt_bootstatus_set ltq_wdt_bootstatus_set;
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int ret;
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ltq_wdt_membase = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(ltq_wdt_membase))
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return PTR_ERR(ltq_wdt_membase);
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ltq_wdt_bootstatus_set = of_device_get_match_data(&pdev->dev);
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if (ltq_wdt_bootstatus_set) {
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ret = ltq_wdt_bootstatus_set(pdev);
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if (ret)
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return ret;
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}
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/* we do not need to enable the clock as it is always running */
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clk = clk_get_io();
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if (IS_ERR(clk)) {
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@ -205,10 +271,6 @@ ltq_wdt_probe(struct platform_device *pdev)
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ltq_io_region_clk_rate = clk_get_rate(clk);
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clk_put(clk);
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/* find out if the watchdog caused the last reboot */
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if (ltq_reset_cause() == LTQ_RST_CAUSE_WDTRST)
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ltq_wdt_bootstatus = WDIOF_CARDRESET;
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dev_info(&pdev->dev, "Init done\n");
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return misc_register(<q_wdt_miscdev);
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}
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@ -222,7 +284,9 @@ ltq_wdt_remove(struct platform_device *pdev)
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}
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static const struct of_device_id ltq_wdt_match[] = {
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{ .compatible = "lantiq,wdt" },
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{ .compatible = "lantiq,wdt", .data = NULL},
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{ .compatible = "lantiq,xrx100-wdt", .data = ltq_wdt_bootstatus_xrx },
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{ .compatible = "lantiq,falcon-wdt", .data = ltq_wdt_bootstatus_falcon },
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{},
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};
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MODULE_DEVICE_TABLE(of, ltq_wdt_match);
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