drm/nouveau/bios/rammap: Pull DLLoff bit out of version 0x10 struct
In preparation of NV50 reclocking, where there is no version Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Родитель
4a68ccc8e4
Коммит
7164f4c5b2
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@ -32,6 +32,7 @@ struct nvbios_ramcfg {
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unsigned ramcfg_ver;
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unsigned ramcfg_hdr;
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unsigned ramcfg_timing;
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unsigned ramcfg_DLLoff;
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union {
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struct {
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unsigned ramcfg_10_02_01:1;
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@ -40,7 +41,6 @@ struct nvbios_ramcfg {
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unsigned ramcfg_10_02_08:1;
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unsigned ramcfg_10_02_10:1;
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unsigned ramcfg_10_02_20:1;
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unsigned ramcfg_10_DLLoff:1;
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unsigned ramcfg_10_03_0f:4;
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unsigned ramcfg_10_04_01:1;
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unsigned ramcfg_10_05:8;
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@ -157,7 +157,7 @@ nvbios_rammapSp(struct nvkm_bios *bios, u32 data,
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p->ramcfg_10_02_08 = (nv_ro08(bios, data + 0x02) & 0x08) >> 3;
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p->ramcfg_10_02_10 = (nv_ro08(bios, data + 0x02) & 0x10) >> 4;
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p->ramcfg_10_02_20 = (nv_ro08(bios, data + 0x02) & 0x20) >> 5;
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p->ramcfg_10_DLLoff = (nv_ro08(bios, data + 0x02) & 0x40) >> 6;
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p->ramcfg_DLLoff = (nv_ro08(bios, data + 0x02) & 0x40) >> 6;
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p->ramcfg_10_03_0f = (nv_ro08(bios, data + 0x03) & 0x0f) >> 0;
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p->ramcfg_10_04_01 = (nv_ro08(bios, data + 0x04) & 0x01) >> 0;
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p->ramcfg_10_05 = (nv_ro08(bios, data + 0x05) & 0xff) >> 0;
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@ -77,7 +77,7 @@ nvkm_gddr3_calc(struct nvkm_ram *ram)
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CWL = ram->next->bios.timing_10_CWL;
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CL = ram->next->bios.timing_10_CL;
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WR = ram->next->bios.timing_10_WR;
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DLL = !ram->next->bios.ramcfg_10_DLLoff;
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DLL = !ram->next->bios.ramcfg_DLLoff;
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ODT = ram->next->bios.timing_10_ODT;
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break;
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case 0x20:
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@ -590,7 +590,7 @@ gt215_ram_calc(struct nvkm_fb *pfb, u32 freq)
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r100da0 = 0x00000000;
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}
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if (!next->bios.ramcfg_10_DLLoff)
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if (!next->bios.ramcfg_DLLoff)
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r004018 |= 0x00004000;
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/* pll2pll requires to switch to a safe clock first */
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@ -630,7 +630,7 @@ gt215_ram_calc(struct nvkm_fb *pfb, u32 freq)
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}
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/* If we're disabling the DLL, do it now */
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switch (next->bios.ramcfg_10_DLLoff * ram->base.type) {
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switch (next->bios.ramcfg_DLLoff * ram->base.type) {
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case NV_MEM_TYPE_DDR3:
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nvkm_sddr3_dll_disable(fuc, ram->base.mr);
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break;
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@ -810,7 +810,7 @@ gt215_ram_calc(struct nvkm_fb *pfb, u32 freq)
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gt215_ram_fbvref(fuc, 1);
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/* Reset DLL */
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if (!next->bios.ramcfg_10_DLLoff)
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if (!next->bios.ramcfg_DLLoff)
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nvkm_sddr2_dll_reset(fuc);
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if (ram->base.type == NV_MEM_TYPE_GDDR3) {
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@ -65,7 +65,7 @@ nvkm_sddr2_calc(struct nvkm_ram *ram)
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case 0x10:
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CL = ram->next->bios.timing_10_CL;
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WR = ram->next->bios.timing_10_WR;
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DLL = !ram->next->bios.ramcfg_10_DLLoff;
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DLL = !ram->next->bios.ramcfg_DLLoff;
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ODT = ram->next->bios.timing_10_ODT & 3;
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break;
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case 0x20:
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@ -79,7 +79,7 @@ nvkm_sddr3_calc(struct nvkm_ram *ram)
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CWL = ram->next->bios.timing_10_CWL;
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CL = ram->next->bios.timing_10_CL;
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WR = ram->next->bios.timing_10_WR;
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DLL = !ram->next->bios.ramcfg_10_DLLoff;
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DLL = !ram->next->bios.ramcfg_DLLoff;
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ODT = ram->next->bios.timing_10_ODT;
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break;
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case 0x20:
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