ASoC: rt5640: Add the function of the PLL clock calculation to RL6231 shared support
The patch adds the function of the PLL clock calculation to RL6231 shared support. Signed-off-by: Oder Chiou <oder_chiou@realtek.com> Signed-off-by: Mark Brown <broonie@linaro.org>
This commit is contained in:
Родитель
49ef7925c2
Коммит
71c7a2d675
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@ -62,6 +62,75 @@ int rl6231_calc_dmic_clk(int rate)
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}
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EXPORT_SYMBOL_GPL(rl6231_calc_dmic_clk);
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/**
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* rl6231_pll_calc - Calcualte PLL M/N/K code.
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* @freq_in: external clock provided to codec.
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* @freq_out: target clock which codec works on.
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* @pll_code: Pointer to structure with M, N, K and bypass flag.
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*
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* Calcualte M/N/K code to configure PLL for codec.
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*
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* Returns 0 for success or negative error code.
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*/
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int rl6231_pll_calc(const unsigned int freq_in,
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const unsigned int freq_out, struct rl6231_pll_code *pll_code)
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{
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int max_n = RL6231_PLL_N_MAX, max_m = RL6231_PLL_M_MAX;
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int k, red, n_t, pll_out, in_t, out_t;
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int n = 0, m = 0, m_t = 0;
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int red_t = abs(freq_out - freq_in);
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bool bypass = false;
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if (RL6231_PLL_INP_MAX < freq_in || RL6231_PLL_INP_MIN > freq_in)
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return -EINVAL;
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k = 100000000 / freq_out - 2;
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if (k > RL6231_PLL_K_MAX)
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k = RL6231_PLL_K_MAX;
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for (n_t = 0; n_t <= max_n; n_t++) {
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in_t = freq_in / (k + 2);
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pll_out = freq_out / (n_t + 2);
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if (in_t < 0)
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continue;
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if (in_t == pll_out) {
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bypass = true;
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n = n_t;
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goto code_find;
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}
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red = abs(in_t - pll_out);
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if (red < red_t) {
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bypass = true;
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n = n_t;
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m = m_t;
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if (red == 0)
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goto code_find;
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red_t = red;
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}
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for (m_t = 0; m_t <= max_m; m_t++) {
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out_t = in_t / (m_t + 2);
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red = abs(out_t - pll_out);
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if (red < red_t) {
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bypass = false;
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n = n_t;
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m = m_t;
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if (red == 0)
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goto code_find;
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red_t = red;
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}
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}
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}
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pr_debug("Only get approximation about PLL\n");
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code_find:
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pll_code->m_bp = bypass;
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pll_code->m_code = m;
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pll_code->n_code = n;
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pll_code->k_code = k;
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return 0;
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}
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EXPORT_SYMBOL_GPL(rl6231_pll_calc);
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MODULE_DESCRIPTION("RL6231 class device shared support");
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MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
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MODULE_LICENSE("GPL v2");
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@ -13,6 +13,21 @@
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#ifndef __RL6231_H__
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#define __RL6231_H__
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#define RL6231_PLL_INP_MAX 40000000
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#define RL6231_PLL_INP_MIN 256000
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#define RL6231_PLL_N_MAX 0x1ff
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#define RL6231_PLL_K_MAX 0x1f
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#define RL6231_PLL_M_MAX 0xf
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struct rl6231_pll_code {
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bool m_bp; /* Indicates bypass m code or not. */
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int m_code;
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int n_code;
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int k_code;
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};
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int rl6231_calc_dmic_clk(int rate);
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int rl6231_pll_calc(const unsigned int freq_in,
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const unsigned int freq_out, struct rl6231_pll_code *pll_code);
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#endif /* __RL6231_H__ */
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@ -1806,65 +1806,12 @@ static int rt5640_set_dai_sysclk(struct snd_soc_dai *dai,
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return 0;
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}
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/**
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* rt5640_pll_calc - Calculate PLL M/N/K code.
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* @freq_in: external clock provided to codec.
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* @freq_out: target clock which codec works on.
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* @pll_code: Pointer to structure with M, N, K and bypass flag.
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*
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* Calculate M/N/K code to configure PLL for codec. And K is assigned to 2
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* which make calculation more efficiently.
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*
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* Returns 0 for success or negative error code.
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*/
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static int rt5640_pll_calc(const unsigned int freq_in,
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const unsigned int freq_out, struct rt5640_pll_code *pll_code)
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{
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int max_n = RT5640_PLL_N_MAX, max_m = RT5640_PLL_M_MAX;
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int n = 0, m = 0, red, n_t, m_t, in_t, out_t;
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int red_t = abs(freq_out - freq_in);
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bool bypass = false;
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if (RT5640_PLL_INP_MAX < freq_in || RT5640_PLL_INP_MIN > freq_in)
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return -EINVAL;
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for (n_t = 0; n_t <= max_n; n_t++) {
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in_t = (freq_in >> 1) + (freq_in >> 2) * n_t;
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if (in_t < 0)
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continue;
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if (in_t == freq_out) {
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bypass = true;
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n = n_t;
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goto code_find;
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}
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for (m_t = 0; m_t <= max_m; m_t++) {
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out_t = in_t / (m_t + 2);
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red = abs(out_t - freq_out);
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if (red < red_t) {
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n = n_t;
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m = m_t;
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if (red == 0)
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goto code_find;
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red_t = red;
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}
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}
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}
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pr_debug("Only get approximation about PLL\n");
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code_find:
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pll_code->m_bp = bypass;
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pll_code->m_code = m;
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pll_code->n_code = n;
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pll_code->k_code = 2;
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return 0;
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}
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static int rt5640_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
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unsigned int freq_in, unsigned int freq_out)
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{
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struct snd_soc_codec *codec = dai->codec;
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struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
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struct rt5640_pll_code *pll_code = &rt5640->pll_code;
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struct rl6231_pll_code pll_code;
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int ret, dai_sel;
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if (source == rt5640->pll_src && freq_in == rt5640->pll_in &&
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@ -1908,20 +1855,21 @@ static int rt5640_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
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return -EINVAL;
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}
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ret = rt5640_pll_calc(freq_in, freq_out, pll_code);
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ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
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if (ret < 0) {
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dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
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return ret;
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}
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dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=2\n", pll_code->m_bp,
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(pll_code->m_bp ? 0 : pll_code->m_code), pll_code->n_code);
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dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
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pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
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pll_code.n_code, pll_code.k_code);
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snd_soc_write(codec, RT5640_PLL_CTRL1,
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pll_code->n_code << RT5640_PLL_N_SFT | pll_code->k_code);
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pll_code.n_code << RT5640_PLL_N_SFT | pll_code.k_code);
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snd_soc_write(codec, RT5640_PLL_CTRL2,
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(pll_code->m_bp ? 0 : pll_code->m_code) << RT5640_PLL_M_SFT |
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pll_code->m_bp << RT5640_PLL_M_BP_SFT);
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(pll_code.m_bp ? 0 : pll_code.m_code) << RT5640_PLL_M_SFT |
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pll_code.m_bp << RT5640_PLL_M_BP_SFT);
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rt5640->pll_in = freq_in;
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rt5640->pll_out = freq_out;
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@ -2079,13 +2079,6 @@ enum {
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RT5640_DMIC2,
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};
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struct rt5640_pll_code {
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bool m_bp; /* Indicates bypass m code or not. */
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int m_code;
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int n_code;
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int k_code;
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};
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struct rt5640_priv {
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struct snd_soc_codec *codec;
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struct rt5640_platform_data pdata;
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@ -2097,7 +2090,6 @@ struct rt5640_priv {
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int bclk[RT5640_AIFS];
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int master[RT5640_AIFS];
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struct rt5640_pll_code pll_code;
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int pll_src;
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int pll_in;
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int pll_out;
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@ -1964,80 +1964,12 @@ static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai,
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return 0;
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}
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/**
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* rt5645_pll_calc - Calcualte PLL M/N/K code.
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* @freq_in: external clock provided to codec.
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* @freq_out: target clock which codec works on.
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* @pll_code: Pointer to structure with M, N, K and bypass flag.
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*
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* Calcualte M/N/K code to configure PLL for codec. And K is assigned to 2
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* which make calculation more efficiently.
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*
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* Returns 0 for success or negative error code.
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*/
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static int rt5645_pll_calc(const unsigned int freq_in,
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const unsigned int freq_out, struct rt5645_pll_code *pll_code)
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{
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int max_n = RT5645_PLL_N_MAX, max_m = RT5645_PLL_M_MAX;
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int k, n = 0, m = 0, red, n_t, m_t, pll_out, in_t, out_t;
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int red_t = abs(freq_out - freq_in);
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bool bypass = false;
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if (RT5645_PLL_INP_MAX < freq_in || RT5645_PLL_INP_MIN > freq_in)
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return -EINVAL;
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k = 100000000 / freq_out - 2;
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if (k > RT5645_PLL_K_MAX)
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k = RT5645_PLL_K_MAX;
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for (n_t = 0; n_t <= max_n; n_t++) {
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in_t = freq_in / (k + 2);
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pll_out = freq_out / (n_t + 2);
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if (in_t < 0)
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continue;
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if (in_t == pll_out) {
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bypass = true;
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n = n_t;
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goto code_find;
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}
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red = abs(in_t - pll_out);
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if (red < red_t) {
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bypass = true;
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n = n_t;
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m = m_t;
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if (red == 0)
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goto code_find;
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red_t = red;
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}
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for (m_t = 0; m_t <= max_m; m_t++) {
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out_t = in_t / (m_t + 2);
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red = abs(out_t - pll_out);
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if (red < red_t) {
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bypass = false;
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n = n_t;
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m = m_t;
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if (red == 0)
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goto code_find;
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red_t = red;
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}
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}
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}
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pr_debug("Only get approximation about PLL\n");
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code_find:
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pll_code->m_bp = bypass;
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pll_code->m_code = m;
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pll_code->n_code = n;
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pll_code->k_code = k;
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return 0;
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}
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static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
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unsigned int freq_in, unsigned int freq_out)
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{
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struct snd_soc_codec *codec = dai->codec;
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struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
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struct rt5645_pll_code pll_code;
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struct rl6231_pll_code pll_code;
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int ret;
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if (source == rt5645->pll_src && freq_in == rt5645->pll_in &&
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@ -2080,7 +2012,7 @@ static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
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return -EINVAL;
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}
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ret = rt5645_pll_calc(freq_in, freq_out, &pll_code);
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ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
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if (ret < 0) {
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dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
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return ret;
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@ -2162,13 +2162,6 @@ enum {
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RT5645_DMIC_DATA_GPIO11,
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};
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struct rt5645_pll_code {
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bool m_bp; /* Indicates bypass m code or not. */
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int m_code;
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int n_code;
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int k_code;
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};
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struct rt5645_priv {
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struct snd_soc_codec *codec;
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struct rt5645_platform_data pdata;
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@ -1516,65 +1516,12 @@ static int rt5651_set_dai_sysclk(struct snd_soc_dai *dai,
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return 0;
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}
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/**
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* rt5651_pll_calc - Calcualte PLL M/N/K code.
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* @freq_in: external clock provided to codec.
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* @freq_out: target clock which codec works on.
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* @pll_code: Pointer to structure with M, N, K and bypass flag.
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*
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* Calcualte M/N/K code to configure PLL for codec. And K is assigned to 2
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* which make calculation more efficiently.
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*
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* Returns 0 for success or negative error code.
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*/
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static int rt5651_pll_calc(const unsigned int freq_in,
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const unsigned int freq_out, struct rt5651_pll_code *pll_code)
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{
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int max_n = RT5651_PLL_N_MAX, max_m = RT5651_PLL_M_MAX;
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int n = 0, m = 0, red, n_t, m_t, in_t, out_t;
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int red_t = abs(freq_out - freq_in);
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bool bypass = false;
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if (RT5651_PLL_INP_MAX < freq_in || RT5651_PLL_INP_MIN > freq_in)
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return -EINVAL;
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for (n_t = 0; n_t <= max_n; n_t++) {
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in_t = (freq_in >> 1) + (freq_in >> 2) * n_t;
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if (in_t < 0)
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continue;
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if (in_t == freq_out) {
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bypass = true;
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n = n_t;
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goto code_find;
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}
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for (m_t = 0; m_t <= max_m; m_t++) {
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out_t = in_t / (m_t + 2);
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red = abs(out_t - freq_out);
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if (red < red_t) {
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n = n_t;
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m = m_t;
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if (red == 0)
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goto code_find;
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red_t = red;
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}
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}
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}
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pr_debug("Only get approximation about PLL\n");
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code_find:
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pll_code->m_bp = bypass;
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pll_code->m_code = m;
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pll_code->n_code = n;
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pll_code->k_code = 2;
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return 0;
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}
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static int rt5651_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
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unsigned int freq_in, unsigned int freq_out)
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{
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struct snd_soc_codec *codec = dai->codec;
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struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
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struct rt5651_pll_code *pll_code = &rt5651->pll_code;
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struct rl6231_pll_code pll_code;
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int ret;
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if (source == rt5651->pll_src && freq_in == rt5651->pll_in &&
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@ -1609,20 +1556,21 @@ static int rt5651_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
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return -EINVAL;
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}
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ret = rt5651_pll_calc(freq_in, freq_out, pll_code);
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ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
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if (ret < 0) {
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dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
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return ret;
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}
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dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=2\n", pll_code->m_bp,
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(pll_code->m_bp ? 0 : pll_code->m_code), pll_code->n_code);
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dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
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pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
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pll_code.n_code, pll_code.k_code);
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snd_soc_write(codec, RT5651_PLL_CTRL1,
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pll_code->n_code << RT5651_PLL_N_SFT | pll_code->k_code);
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pll_code.n_code << RT5651_PLL_N_SFT | pll_code.k_code);
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snd_soc_write(codec, RT5651_PLL_CTRL2,
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(pll_code->m_bp ? 0 : pll_code->m_code) << RT5651_PLL_M_SFT |
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pll_code->m_bp << RT5651_PLL_M_BP_SFT);
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(pll_code.m_bp ? 0 : pll_code.m_code) << RT5651_PLL_M_SFT |
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pll_code.m_bp << RT5651_PLL_M_BP_SFT);
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||||
rt5651->pll_in = freq_in;
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rt5651->pll_out = freq_out;
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@ -2069,7 +2069,6 @@ struct rt5651_priv {
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int bclk[RT5651_AIFS];
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int master[RT5651_AIFS];
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struct rt5651_pll_code pll_code;
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int pll_src;
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||||
int pll_in;
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||||
int pll_out;
|
||||
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|
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