mxc_nand: Add v3 (i.MX51) Support
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This commit is contained in:
Sascha Hauer
David Woodhouse
Родитель
6e85dfdc19
Коммит
71ec51554a
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@ -481,7 +481,7 @@ config MTD_NAND_MPC5121_NFC
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config MTD_NAND_MXC
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tristate "MXC NAND support"
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depends on ARCH_MX2 || ARCH_MX25 || ARCH_MX3
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depends on ARCH_MX2 || ARCH_MX25 || ARCH_MX3 || ARCH_MX51
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help
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This enables the driver for the NAND flash controller on the
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MXC processors.
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@ -39,6 +39,8 @@
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#define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35())
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#define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21())
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#define nfc_is_v3_2() cpu_is_mx51()
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#define nfc_is_v3() nfc_is_v3_2()
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/* Addresses for NFC registers */
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#define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
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@ -80,6 +82,54 @@
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#define NFC_ID (1 << 4)
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#define NFC_STATUS (1 << 5)
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#define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
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#define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
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#define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
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#define NFC_V3_CONFIG1_SP_EN (1 << 0)
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#define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
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#define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
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#define NFC_V3_LAUNCH (host->regs_axi + 0x40)
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#define NFC_V3_WRPROT (host->regs_ip + 0x0)
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#define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
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#define NFC_V3_WRPROT_LOCK (1 << 1)
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#define NFC_V3_WRPROT_UNLOCK (1 << 2)
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#define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
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#define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
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#define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
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#define NFC_V3_CONFIG2_PS_512 (0 << 0)
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#define NFC_V3_CONFIG2_PS_2048 (1 << 0)
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#define NFC_V3_CONFIG2_PS_4096 (2 << 0)
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#define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
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#define NFC_V3_CONFIG2_ECC_EN (1 << 3)
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#define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
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#define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
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#define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
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#define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7)
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#define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
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#define NFC_V3_CONFIG2_INT_MSK (1 << 15)
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#define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
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#define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
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#define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
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#define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
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#define NFC_V3_CONFIG3_FW8 (1 << 3)
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#define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
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#define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
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#define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
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#define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
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#define NFC_V3_IPC (host->regs_ip + 0x2C)
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#define NFC_V3_IPC_CREQ (1 << 0)
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#define NFC_V3_IPC_INT (1 << 31)
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#define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
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struct mxc_nand_host {
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struct mtd_info mtd;
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struct nand_chip nand;
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@ -91,6 +141,8 @@ struct mxc_nand_host {
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void __iomem *base;
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void __iomem *regs;
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void __iomem *regs_axi;
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void __iomem *regs_ip;
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int status_request;
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struct clk *clk;
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int clk_act;
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@ -169,6 +221,20 @@ static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
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return IRQ_HANDLED;
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}
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static int check_int_v3(struct mxc_nand_host *host)
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{
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uint32_t tmp;
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tmp = readl(NFC_V3_IPC);
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if (!(tmp & NFC_V3_IPC_INT))
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return 0;
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tmp &= ~NFC_V3_IPC_INT;
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writel(tmp, NFC_V3_IPC);
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return 1;
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}
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static int check_int_v1_v2(struct mxc_nand_host *host)
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{
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uint32_t tmp;
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@ -209,6 +275,18 @@ static void wait_op_done(struct mxc_nand_host *host, int useirq)
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}
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}
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static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
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{
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/* fill command */
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writel(cmd, NFC_V3_FLASH_CMD);
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/* send out command */
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writel(NFC_CMD, NFC_V3_LAUNCH);
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/* Wait for operation to complete */
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wait_op_done(host, useirq);
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}
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/* This function issues the specified command to the NAND device and
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* waits for completion. */
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static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
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@ -237,6 +315,17 @@ static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
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}
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}
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static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
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{
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/* fill address */
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writel(addr, NFC_V3_FLASH_ADDR0);
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/* send out address */
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writel(NFC_ADDR, NFC_V3_LAUNCH);
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wait_op_done(host, 0);
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}
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/* This function sends an address (or partial address) to the
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* NAND device. The address is used to select the source/destination for
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* a NAND command. */
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@ -251,6 +340,22 @@ static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islas
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wait_op_done(host, islast);
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}
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static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
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{
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struct nand_chip *nand_chip = mtd->priv;
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struct mxc_nand_host *host = nand_chip->priv;
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uint32_t tmp;
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tmp = readl(NFC_V3_CONFIG1);
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tmp &= ~(7 << 4);
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writel(tmp, NFC_V3_CONFIG1);
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/* transfer data from NFC ram to nand */
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writel(ops, NFC_V3_LAUNCH);
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wait_op_done(host, false);
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}
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static void send_page_v1_v2(struct mtd_info *mtd, unsigned int ops)
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{
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struct nand_chip *nand_chip = mtd->priv;
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@ -274,6 +379,16 @@ static void send_page_v1_v2(struct mtd_info *mtd, unsigned int ops)
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}
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}
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static void send_read_id_v3(struct mxc_nand_host *host)
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{
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/* Read ID into main buffer */
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writel(NFC_ID, NFC_V3_LAUNCH);
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wait_op_done(host, true);
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memcpy(host->data_buf, host->main_area0, 16);
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}
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/* Request the NANDFC to perform a read of the NAND device ID. */
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static void send_read_id_v1_v2(struct mxc_nand_host *host)
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{
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@ -299,6 +414,14 @@ static void send_read_id_v1_v2(struct mxc_nand_host *host)
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memcpy(host->data_buf, host->main_area0, 16);
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}
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static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
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{
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writew(NFC_STATUS, NFC_V3_LAUNCH);
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wait_op_done(host, true);
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return readl(NFC_V3_CONFIG1) >> 16;
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}
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/* This function requests the NANDFC to perform a read of the
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* NAND device status and returns the current status. */
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static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
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@ -381,7 +504,10 @@ static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
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no_subpages = mtd->writesize >> 9;
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ecc_stat = readl(NFC_V1_V2_ECC_STATUS_RESULT);
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if (nfc_is_v21())
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ecc_stat = readl(NFC_V1_V2_ECC_STATUS_RESULT);
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else
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ecc_stat = readl(NFC_V3_ECC_STATUS_RESULT);
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do {
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err = ecc_stat & ecc_bit_mask;
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@ -643,6 +769,72 @@ static void preset_v1_v2(struct mtd_info *mtd)
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writew(0x4, NFC_V1_V2_WRPROT);
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}
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static void preset_v3(struct mtd_info *mtd)
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{
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struct nand_chip *chip = mtd->priv;
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struct mxc_nand_host *host = chip->priv;
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uint32_t config2, config3;
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int i, addr_phases;
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writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
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writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
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/* Unlock the internal RAM Buffer */
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writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
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NFC_V3_WRPROT);
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/* Blocks to be unlocked */
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for (i = 0; i < NAND_MAX_CHIPS; i++)
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writel(0x0 | (0xffff << 16),
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NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
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writel(0, NFC_V3_IPC);
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config2 = NFC_V3_CONFIG2_ONE_CYCLE |
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NFC_V3_CONFIG2_2CMD_PHASES |
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NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
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NFC_V3_CONFIG2_ST_CMD(0x70) |
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NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
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if (chip->ecc.mode == NAND_ECC_HW)
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config2 |= NFC_V3_CONFIG2_ECC_EN;
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addr_phases = fls(chip->pagemask) >> 3;
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if (mtd->writesize == 2048) {
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config2 |= NFC_V3_CONFIG2_PS_2048;
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config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
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} else if (mtd->writesize == 4096) {
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config2 |= NFC_V3_CONFIG2_PS_4096;
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config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
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} else {
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config2 |= NFC_V3_CONFIG2_PS_512;
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config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
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}
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if (mtd->writesize) {
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config2 |= NFC_V3_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6);
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host->eccsize = get_eccsize(mtd);
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if (host->eccsize == 8)
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config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
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}
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writel(config2, NFC_V3_CONFIG2);
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config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
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NFC_V3_CONFIG3_NO_SDMA |
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NFC_V3_CONFIG3_RBB_MODE |
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NFC_V3_CONFIG3_SBB(6) | /* Reset default */
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NFC_V3_CONFIG3_ADD_OP(0);
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if (!(chip->options & NAND_BUSWIDTH_16))
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config3 |= NFC_V3_CONFIG3_FW8;
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writel(config3, NFC_V3_CONFIG3);
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writel(0, NFC_V3_DELAY_LINE);
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}
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/* Used by the upper layer to write command to NAND Flash for
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* different operations to be carried out on NAND Flash */
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static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
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@ -843,6 +1035,30 @@ static int __init mxcnd_probe(struct platform_device *pdev)
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oob_smallpage = &nandv1_hw_eccoob_smallpage;
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oob_largepage = &nandv1_hw_eccoob_largepage;
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this->ecc.bytes = 3;
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host->eccsize = 1;
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} else if (nfc_is_v3_2()) {
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!res) {
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err = -ENODEV;
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goto eirq;
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}
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host->regs_ip = ioremap(res->start, resource_size(res));
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if (!host->regs_ip) {
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err = -ENOMEM;
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goto eirq;
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}
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host->regs_axi = host->base + 0x1e00;
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host->spare0 = host->base + 0x1000;
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host->spare_len = 64;
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host->preset = preset_v3;
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host->send_cmd = send_cmd_v3;
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host->send_addr = send_addr_v3;
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host->send_page = send_page_v3;
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host->send_read_id = send_read_id_v3;
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host->check_int = check_int_v3;
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host->get_dev_status = get_dev_status_v3;
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oob_smallpage = &nandv2_hw_eccoob_smallpage;
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oob_largepage = &nandv2_hw_eccoob_largepage;
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} else
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BUG();
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@ -918,6 +1134,8 @@ static int __init mxcnd_probe(struct platform_device *pdev)
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escan:
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free_irq(host->irq, host);
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eirq:
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if (host->regs_ip)
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iounmap(host->regs_ip);
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iounmap(host->base);
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eres:
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clk_put(host->clk);
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@ -937,6 +1155,8 @@ static int __devexit mxcnd_remove(struct platform_device *pdev)
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nand_release(&host->mtd);
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free_irq(host->irq, host);
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if (host->regs_ip)
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iounmap(host->regs_ip);
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iounmap(host->base);
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kfree(host);
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