ASoC: stm32: i2s: manage identification registers
Add support of identification registers in STM32 I2S. Signed-off-by: Olivier Moysan <olivier.moysan@st.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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Родитель
0cf4610b9f
Коммит
71ed4bddde
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@ -16,6 +16,7 @@
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* details.
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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@ -37,6 +38,10 @@
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#define STM32_I2S_TXDR_REG 0X20
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#define STM32_I2S_RXDR_REG 0x30
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#define STM32_I2S_CGFR_REG 0X50
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#define STM32_I2S_HWCFGR_REG 0x3F0
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#define STM32_I2S_VERR_REG 0x3F4
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#define STM32_I2S_IPIDR_REG 0x3F8
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#define STM32_I2S_SIDR_REG 0x3FC
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/* Bit definition for SPI2S_CR1 register */
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#define I2S_CR1_SPE BIT(0)
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@ -143,6 +148,23 @@
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#define I2S_CGFR_ODD BIT(I2S_CGFR_ODD_SHIFT)
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#define I2S_CGFR_MCKOE BIT(25)
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/* Registers below apply to I2S version 1.1 and more */
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/* Bit definition for SPI_HWCFGR register */
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#define I2S_HWCFGR_I2S_SUPPORT_MASK GENMASK(15, 12)
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/* Bit definition for SPI_VERR register */
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#define I2S_VERR_MIN_MASK GENMASK(3, 0)
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#define I2S_VERR_MAJ_MASK GENMASK(7, 4)
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/* Bit definition for SPI_IPIDR register */
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#define I2S_IPIDR_ID_MASK GENMASK(31, 0)
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/* Bit definition for SPI_SIDR register */
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#define I2S_SIDR_ID_MASK GENMASK(31, 0)
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#define I2S_IPIDR_NUMBER 0x00130022
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enum i2s_master_mode {
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I2S_MS_NOT_SET,
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I2S_MS_MASTER,
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@ -280,6 +302,10 @@ static bool stm32_i2s_readable_reg(struct device *dev, unsigned int reg)
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case STM32_I2S_SR_REG:
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case STM32_I2S_RXDR_REG:
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case STM32_I2S_CGFR_REG:
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case STM32_I2S_HWCFGR_REG:
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case STM32_I2S_VERR_REG:
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case STM32_I2S_IPIDR_REG:
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case STM32_I2S_SIDR_REG:
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return true;
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default:
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return false;
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@ -711,10 +737,11 @@ static const struct regmap_config stm32_h7_i2s_regmap_conf = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = STM32_I2S_CGFR_REG,
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.max_register = STM32_I2S_SIDR_REG,
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.readable_reg = stm32_i2s_readable_reg,
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.volatile_reg = stm32_i2s_volatile_reg,
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.writeable_reg = stm32_i2s_writeable_reg,
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.num_reg_defaults_raw = STM32_I2S_SIDR_REG / sizeof(u32) + 1,
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.fast_io = true,
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.cache_type = REGCACHE_FLAT,
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};
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@ -864,6 +891,7 @@ static int stm32_i2s_parse_dt(struct platform_device *pdev,
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static int stm32_i2s_probe(struct platform_device *pdev)
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{
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struct stm32_i2s_data *i2s;
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u32 val;
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int ret;
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i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
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@ -902,8 +930,34 @@ static int stm32_i2s_probe(struct platform_device *pdev)
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return ret;
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/* Set SPI/I2S in i2s mode */
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return regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
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I2S_CGFR_I2SMOD, I2S_CGFR_I2SMOD);
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ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG,
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I2S_CGFR_I2SMOD, I2S_CGFR_I2SMOD);
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if (ret)
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return ret;
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ret = regmap_read(i2s->regmap, STM32_I2S_IPIDR_REG, &val);
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if (ret)
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return ret;
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if (val == I2S_IPIDR_NUMBER) {
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ret = regmap_read(i2s->regmap, STM32_I2S_HWCFGR_REG, &val);
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if (ret)
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return ret;
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if (!FIELD_GET(I2S_HWCFGR_I2S_SUPPORT_MASK, val)) {
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dev_err(&pdev->dev,
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"Device does not support i2s mode\n");
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return -EPERM;
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}
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ret = regmap_read(i2s->regmap, STM32_I2S_VERR_REG, &val);
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dev_dbg(&pdev->dev, "I2S version: %lu.%lu registered\n",
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FIELD_GET(I2S_VERR_MAJ_MASK, val),
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FIELD_GET(I2S_VERR_MIN_MASK, val));
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}
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return ret;
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}
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MODULE_DEVICE_TABLE(of, stm32_i2s_ids);
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