r8169: make ERIAR_EXGMAC the default in eri functions
In basically all eri function calls the type argument is ERIAR_EXGMAC. Therefore make it the default. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Heiner Kallweit
David S. Miller
Родитель
b4d081df03
Коммит
724c6fd015
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@ -1065,8 +1065,8 @@ DECLARE_RTL_COND(rtl_eriar_cond)
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return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
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}
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static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
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u32 val, int type)
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static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
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u32 val, int type)
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{
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BUG_ON((addr & 3) || (mask == 0));
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RTL_W32(tp, ERIDR, val);
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@ -1075,7 +1075,13 @@ static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
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rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
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}
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static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
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static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
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u32 val)
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{
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_rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
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}
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static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
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{
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RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
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@ -1083,13 +1089,18 @@ static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
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RTL_R32(tp, ERIDR) : ~0;
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}
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static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
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{
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return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
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}
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static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
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u32 m, int type)
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u32 m)
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{
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u32 val;
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val = rtl_eri_read(tp, addr, type);
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rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
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val = rtl_eri_read(tp, addr);
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rtl_eri_write(tp, addr, mask, (val & ~m) | p);
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}
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static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
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@ -1101,7 +1112,7 @@ static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
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static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
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{
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return rtl_eri_read(tp, reg, ERIAR_OOB);
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return _rtl_eri_read(tp, reg, ERIAR_OOB);
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}
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static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
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@ -1115,13 +1126,13 @@ static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
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static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
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u32 data)
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{
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rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
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data, ERIAR_OOB);
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_rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
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data, ERIAR_OOB);
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}
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static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
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{
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rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
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rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
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r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
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}
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@ -1267,7 +1278,7 @@ static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
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const struct exgmac_reg *r, int len)
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{
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while (len-- > 0) {
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rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
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rtl_eri_write(tp, r->addr, r->mask, r->val);
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r++;
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}
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}
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@ -1325,48 +1336,33 @@ static void rtl_link_chg_patch(struct rtl8169_private *tp)
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if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
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tp->mac_version == RTL_GIGA_MAC_VER_38) {
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if (phydev->speed == SPEED_1000) {
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rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
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ERIAR_EXGMAC);
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rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
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ERIAR_EXGMAC);
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rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
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rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
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} else if (phydev->speed == SPEED_100) {
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rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
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ERIAR_EXGMAC);
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rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
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ERIAR_EXGMAC);
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rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
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rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
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} else {
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rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
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ERIAR_EXGMAC);
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rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
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ERIAR_EXGMAC);
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rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
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rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
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}
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/* Reset packet filter */
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rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
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ERIAR_EXGMAC);
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rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
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ERIAR_EXGMAC);
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rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01);
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rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00);
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} else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
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tp->mac_version == RTL_GIGA_MAC_VER_36) {
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if (phydev->speed == SPEED_1000) {
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rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
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ERIAR_EXGMAC);
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rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
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ERIAR_EXGMAC);
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rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
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rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
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} else {
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rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
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ERIAR_EXGMAC);
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rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
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ERIAR_EXGMAC);
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rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
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rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
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}
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} else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
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if (phydev->speed == SPEED_10) {
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rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
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ERIAR_EXGMAC);
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rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
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ERIAR_EXGMAC);
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rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
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rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
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} else {
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rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
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ERIAR_EXGMAC);
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rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
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}
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}
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}
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@ -1411,15 +1407,13 @@ static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
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0x0dc,
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ERIAR_MASK_0100,
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MagicPacket_v2,
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0x0000,
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ERIAR_EXGMAC);
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0x0000);
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else
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rtl_w0w1_eri(tp,
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0x0dc,
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ERIAR_MASK_0100,
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0x0000,
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MagicPacket_v2,
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ERIAR_EXGMAC);
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MagicPacket_v2);
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break;
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default:
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tmp = ARRAY_SIZE(cfg);
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@ -2562,7 +2556,7 @@ static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
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static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
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{
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rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
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rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000);
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}
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static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
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@ -3959,7 +3953,7 @@ static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
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rtl_apply_firmware(tp);
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/* EEE setting */
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rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
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rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
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rtl_writephy(tp, 0x1f, 0x0004);
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rtl_writephy(tp, 0x10, 0x401f);
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rtl_writephy(tp, 0x19, 0x7030);
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@ -3982,10 +3976,10 @@ static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
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rtl_apply_firmware(tp);
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rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
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rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
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rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
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rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
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rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
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}
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static void rtl_hw_phy_config(struct net_device *dev)
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@ -4216,7 +4210,7 @@ static void r8168_pll_power_down(struct rtl8169_private *tp)
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case RTL_GIGA_MAC_VER_41:
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case RTL_GIGA_MAC_VER_49:
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rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
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0xfc000000, ERIAR_EXGMAC);
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0xfc000000);
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RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
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break;
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}
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@ -4245,7 +4239,7 @@ static void r8168_pll_power_up(struct rtl8169_private *tp)
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case RTL_GIGA_MAC_VER_49:
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RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
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rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
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0x00000000, ERIAR_EXGMAC);
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0x00000000);
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break;
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}
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@ -4996,14 +4990,14 @@ static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
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if (tp->dev->mtu <= ETH_DATA_LEN)
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rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
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rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
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rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
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rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
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rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
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rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
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rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
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rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
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rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
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rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
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rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
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rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002);
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rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006);
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rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
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rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
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rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00);
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rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
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RTL_W8(tp, MaxTxPacketSize, EarlySize);
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@ -5029,16 +5023,16 @@ static void rtl_hw_start_8168f(struct rtl8169_private *tp)
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rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
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rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
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rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
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rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
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rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
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rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
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rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
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rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
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rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
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rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
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rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
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rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
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rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
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rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002);
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rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006);
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rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01);
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rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00);
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rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00);
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rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00);
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rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
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rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
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RTL_W8(tp, MaxTxPacketSize, EarlySize);
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@ -5065,7 +5059,7 @@ static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
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rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
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rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
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rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
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/* Adjust EEE LED frequency */
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RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
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@ -5085,37 +5079,37 @@ static void rtl_hw_start_8411(struct rtl8169_private *tp)
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rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
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rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
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rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000);
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}
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static void rtl_hw_start_8168g(struct rtl8169_private *tp)
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{
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rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
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rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
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rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
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rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
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rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002);
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rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38);
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rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48);
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rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006);
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rtl_set_def_aspm_entry_latency(tp);
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rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
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rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
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rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
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rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
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rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01);
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||||
rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00);
|
||||
rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
|
||||
|
||||
RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
|
||||
RTL_W8(tp, MaxTxPacketSize, EarlySize);
|
||||
|
||||
rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
|
||||
rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
|
||||
rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
|
||||
rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
|
||||
|
||||
/* Adjust EEE LED frequency */
|
||||
RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
|
||||
|
||||
rtl8168_config_eee_mac(tp);
|
||||
|
||||
rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
|
||||
rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
|
||||
rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
|
||||
rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000);
|
||||
|
||||
rtl_pcie_state_l2l3_disable(tp);
|
||||
}
|
||||
|
|
@ -5189,29 +5183,29 @@ static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
|
|||
rtl_hw_aspm_clkreq_enable(tp, false);
|
||||
rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
|
||||
|
||||
rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
|
||||
rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
|
||||
rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
|
||||
rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
|
||||
rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002);
|
||||
rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38);
|
||||
rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48);
|
||||
rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006);
|
||||
|
||||
rtl_set_def_aspm_entry_latency(tp);
|
||||
|
||||
rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
|
||||
|
||||
rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
|
||||
rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
|
||||
rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01);
|
||||
rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00);
|
||||
|
||||
rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
|
||||
rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00);
|
||||
|
||||
rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
|
||||
rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00);
|
||||
|
||||
rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
|
||||
rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
|
||||
|
||||
RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
|
||||
RTL_W8(tp, MaxTxPacketSize, EarlySize);
|
||||
|
||||
rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
|
||||
rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
|
||||
rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
|
||||
rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
|
||||
|
||||
/* Adjust EEE LED frequency */
|
||||
RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
|
||||
|
|
@ -5223,7 +5217,7 @@ static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
|
|||
|
||||
RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
|
||||
|
||||
rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
|
||||
rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000);
|
||||
|
||||
rtl_pcie_state_l2l3_disable(tp);
|
||||
|
||||
|
|
@ -5273,34 +5267,34 @@ static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
|
|||
{
|
||||
rtl8168ep_stop_cmac(tp);
|
||||
|
||||
rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
|
||||
rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
|
||||
rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
|
||||
rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
|
||||
rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002);
|
||||
rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f);
|
||||
rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f);
|
||||
rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006);
|
||||
|
||||
rtl_set_def_aspm_entry_latency(tp);
|
||||
|
||||
rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
|
||||
|
||||
rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
|
||||
rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
|
||||
rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01);
|
||||
rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00);
|
||||
|
||||
rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
|
||||
rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00);
|
||||
|
||||
rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
|
||||
rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
|
||||
|
||||
RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
|
||||
RTL_W8(tp, MaxTxPacketSize, EarlySize);
|
||||
|
||||
rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
|
||||
rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
|
||||
rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
|
||||
rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
|
||||
|
||||
/* Adjust EEE LED frequency */
|
||||
RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
|
||||
|
||||
rtl8168_config_eee_mac(tp);
|
||||
|
||||
rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
|
||||
rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
|
||||
|
||||
RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
|
||||
|
||||
|
|
@ -5480,13 +5474,13 @@ static void rtl_hw_start_8402(struct rtl8169_private *tp)
|
|||
|
||||
rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
|
||||
|
||||
rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
|
||||
rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
|
||||
rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
|
||||
rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
|
||||
rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
|
||||
rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
|
||||
rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
|
||||
rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002);
|
||||
rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006);
|
||||
rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01);
|
||||
rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00);
|
||||
rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
|
||||
rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
|
||||
rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);
|
||||
|
||||
rtl_pcie_state_l2l3_disable(tp);
|
||||
}
|
||||
|
|
@ -6958,13 +6952,13 @@ static void rtl_read_mac_address(struct rtl8169_private *tp,
|
|||
switch (tp->mac_version) {
|
||||
case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
|
||||
case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
|
||||
value = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
|
||||
value = rtl_eri_read(tp, 0xe0);
|
||||
mac_addr[0] = (value >> 0) & 0xff;
|
||||
mac_addr[1] = (value >> 8) & 0xff;
|
||||
mac_addr[2] = (value >> 16) & 0xff;
|
||||
mac_addr[3] = (value >> 24) & 0xff;
|
||||
|
||||
value = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
|
||||
value = rtl_eri_read(tp, 0xe4);
|
||||
mac_addr[4] = (value >> 0) & 0xff;
|
||||
mac_addr[5] = (value >> 8) & 0xff;
|
||||
break;
|
||||
|
|
|
|||
Загрузка…
Ссылка в новой задаче