p54pci: rx tasklet refactoring
This patch moves the all of p54pci's receiver code out of the bloated interrupt handler routine and into a less critical tasklet. Signed-off-by: Christian Lamparter <chunkeey@web.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Christian Lamparter
John W. Linville
Родитель
84df3ed30b
Коммит
7262d59366
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@ -3,6 +3,7 @@
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* Linux device driver for PCI based Prism54
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*
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* Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
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* Copyright (c) 2008, Christian Lamparter <chunkeey@web.de>
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*
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* Based on the islsm (softmac prism54) driver, which is:
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* Copyright 2004-2006 Jean-Baptiste Note <jean-baptiste.note@m4x.org>, et al.
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@ -237,20 +238,22 @@ static int p54p_read_eeprom(struct ieee80211_hw *dev)
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return err;
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}
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static void p54p_refill_rx_ring(struct ieee80211_hw *dev)
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static void p54p_refill_rx_ring(struct ieee80211_hw *dev,
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int ring_index, struct p54p_desc *ring, u32 ring_limit,
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struct sk_buff **rx_buf)
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{
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struct p54p_priv *priv = dev->priv;
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struct p54p_ring_control *ring_control = priv->ring_control;
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u32 limit, host_idx, idx;
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u32 limit, idx, i;
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host_idx = le32_to_cpu(ring_control->host_idx[0]);
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limit = host_idx;
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limit -= le32_to_cpu(ring_control->device_idx[0]);
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limit = ARRAY_SIZE(ring_control->rx_data) - limit;
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idx = le32_to_cpu(ring_control->host_idx[ring_index]);
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limit = idx;
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limit -= le32_to_cpu(ring_control->device_idx[ring_index]);
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limit = ring_limit - limit;
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idx = host_idx % ARRAY_SIZE(ring_control->rx_data);
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i = idx % ring_limit;
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while (limit-- > 1) {
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struct p54p_desc *desc = &ring_control->rx_data[idx];
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struct p54p_desc *desc = &ring[i];
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if (!desc->host_addr) {
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struct sk_buff *skb;
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@ -267,16 +270,106 @@ static void p54p_refill_rx_ring(struct ieee80211_hw *dev)
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desc->device_addr = 0; // FIXME: necessary?
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desc->len = cpu_to_le16(MAX_RX_SIZE);
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desc->flags = 0;
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priv->rx_buf[idx] = skb;
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rx_buf[i] = skb;
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}
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i++;
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idx++;
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host_idx++;
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idx %= ARRAY_SIZE(ring_control->rx_data);
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i %= ring_limit;
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}
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wmb();
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ring_control->host_idx[0] = cpu_to_le32(host_idx);
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ring_control->host_idx[ring_index] = cpu_to_le32(idx);
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}
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static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index,
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int ring_index, struct p54p_desc *ring, u32 ring_limit,
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struct sk_buff **rx_buf)
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{
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struct p54p_priv *priv = dev->priv;
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struct p54p_ring_control *ring_control = priv->ring_control;
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struct p54p_desc *desc;
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u32 idx, i;
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i = (*index) % ring_limit;
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(*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
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idx %= ring_limit;
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while (i != idx) {
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u16 len;
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struct sk_buff *skb;
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desc = &ring[i];
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len = le16_to_cpu(desc->len);
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skb = rx_buf[i];
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if (!skb)
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continue;
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skb_put(skb, len);
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if (p54_rx(dev, skb)) {
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pci_unmap_single(priv->pdev,
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le32_to_cpu(desc->host_addr),
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MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
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rx_buf[i] = NULL;
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desc->host_addr = 0;
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} else {
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skb_trim(skb, 0);
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desc->len = cpu_to_le16(MAX_RX_SIZE);
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}
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i++;
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i %= ring_limit;
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}
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p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf);
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}
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/* caller must hold priv->lock */
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static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index,
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int ring_index, struct p54p_desc *ring, u32 ring_limit,
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void **tx_buf)
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{
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struct p54p_priv *priv = dev->priv;
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struct p54p_ring_control *ring_control = priv->ring_control;
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struct p54p_desc *desc;
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u32 idx, i;
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i = (*index) % ring_limit;
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(*index) = idx = le32_to_cpu(ring_control->device_idx[1]);
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idx %= ring_limit;
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while (i != idx) {
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desc = &ring[i];
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kfree(tx_buf[i]);
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tx_buf[i] = NULL;
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pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
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le16_to_cpu(desc->len), PCI_DMA_TODEVICE);
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desc->host_addr = 0;
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desc->device_addr = 0;
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desc->len = 0;
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desc->flags = 0;
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i++;
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i %= ring_limit;
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}
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}
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static void p54p_rx_tasklet(unsigned long dev_id)
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{
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struct ieee80211_hw *dev = (struct ieee80211_hw *)dev_id;
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struct p54p_priv *priv = dev->priv;
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struct p54p_ring_control *ring_control = priv->ring_control;
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p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt,
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ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt);
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p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data,
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ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data);
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wmb();
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P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
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}
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static irqreturn_t p54p_interrupt(int irq, void *dev_id)
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@ -298,65 +391,18 @@ static irqreturn_t p54p_interrupt(int irq, void *dev_id)
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reg &= P54P_READ(int_enable);
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if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE)) {
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struct p54p_desc *desc;
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u32 idx, i;
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i = priv->tx_idx;
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i %= ARRAY_SIZE(ring_control->tx_data);
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priv->tx_idx = idx = le32_to_cpu(ring_control->device_idx[1]);
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idx %= ARRAY_SIZE(ring_control->tx_data);
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p54p_check_tx_ring(dev, &priv->tx_idx_mgmt,
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3, ring_control->tx_mgmt,
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ARRAY_SIZE(ring_control->tx_mgmt),
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priv->tx_buf_mgmt);
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while (i != idx) {
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desc = &ring_control->tx_data[i];
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if (priv->tx_buf[i]) {
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kfree(priv->tx_buf[i]);
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priv->tx_buf[i] = NULL;
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}
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p54p_check_tx_ring(dev, &priv->tx_idx_data,
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1, ring_control->tx_data,
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ARRAY_SIZE(ring_control->tx_data),
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priv->tx_buf_data);
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pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
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le16_to_cpu(desc->len), PCI_DMA_TODEVICE);
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tasklet_schedule(&priv->rx_tasklet);
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desc->host_addr = 0;
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desc->device_addr = 0;
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desc->len = 0;
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desc->flags = 0;
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i++;
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i %= ARRAY_SIZE(ring_control->tx_data);
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}
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i = priv->rx_idx;
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i %= ARRAY_SIZE(ring_control->rx_data);
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priv->rx_idx = idx = le32_to_cpu(ring_control->device_idx[0]);
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idx %= ARRAY_SIZE(ring_control->rx_data);
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while (i != idx) {
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u16 len;
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struct sk_buff *skb;
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desc = &ring_control->rx_data[i];
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len = le16_to_cpu(desc->len);
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skb = priv->rx_buf[i];
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skb_put(skb, len);
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if (p54_rx(dev, skb)) {
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pci_unmap_single(priv->pdev,
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le32_to_cpu(desc->host_addr),
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MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
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priv->rx_buf[i] = NULL;
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desc->host_addr = 0;
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} else {
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skb_trim(skb, 0);
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desc->len = cpu_to_le16(MAX_RX_SIZE);
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}
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i++;
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i %= ARRAY_SIZE(ring_control->rx_data);
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}
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p54p_refill_rx_ring(dev);
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wmb();
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P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
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} else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
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complete(&priv->boot_comp);
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@ -392,7 +438,7 @@ static void p54p_tx(struct ieee80211_hw *dev, struct p54_control_hdr *data,
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ring_control->host_idx[1] = cpu_to_le32(idx + 1);
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if (free_on_tx)
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priv->tx_buf[i] = data;
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priv->tx_buf_data[i] = data;
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spin_unlock_irqrestore(&priv->lock, flags);
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@ -420,8 +466,14 @@ static int p54p_open(struct ieee80211_hw *dev)
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}
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memset(priv->ring_control, 0, sizeof(*priv->ring_control));
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priv->rx_idx = priv->tx_idx = 0;
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p54p_refill_rx_ring(dev);
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priv->rx_idx_data = priv->tx_idx_data = 0;
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priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0;
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p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data,
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ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data);
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p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt,
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ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt);
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p54p_upload_firmware(dev);
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@ -465,6 +517,8 @@ static void p54p_stop(struct ieee80211_hw *dev)
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unsigned int i;
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struct p54p_desc *desc;
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tasklet_kill(&priv->rx_tasklet);
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P54P_WRITE(int_enable, cpu_to_le32(0));
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P54P_READ(int_enable);
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udelay(10);
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@ -473,26 +527,51 @@ static void p54p_stop(struct ieee80211_hw *dev)
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P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
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for (i = 0; i < ARRAY_SIZE(priv->rx_buf); i++) {
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for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) {
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desc = &ring_control->rx_data[i];
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if (desc->host_addr)
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pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
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pci_unmap_single(priv->pdev,
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le32_to_cpu(desc->host_addr),
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MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
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kfree_skb(priv->rx_buf[i]);
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priv->rx_buf[i] = NULL;
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kfree_skb(priv->rx_buf_data[i]);
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priv->rx_buf_data[i] = NULL;
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}
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for (i = 0; i < ARRAY_SIZE(priv->tx_buf); i++) {
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for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) {
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desc = &ring_control->rx_mgmt[i];
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if (desc->host_addr)
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pci_unmap_single(priv->pdev,
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le32_to_cpu(desc->host_addr),
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MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
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kfree_skb(priv->rx_buf_mgmt[i]);
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priv->rx_buf_mgmt[i] = NULL;
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}
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for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) {
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desc = &ring_control->tx_data[i];
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if (desc->host_addr)
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pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
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le16_to_cpu(desc->len), PCI_DMA_TODEVICE);
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pci_unmap_single(priv->pdev,
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le32_to_cpu(desc->host_addr),
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le16_to_cpu(desc->len),
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PCI_DMA_TODEVICE);
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kfree(priv->tx_buf[i]);
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priv->tx_buf[i] = NULL;
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kfree(priv->tx_buf_data[i]);
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priv->tx_buf_data[i] = NULL;
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}
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memset(ring_control, 0, sizeof(ring_control));
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for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) {
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desc = &ring_control->tx_mgmt[i];
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if (desc->host_addr)
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pci_unmap_single(priv->pdev,
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le32_to_cpu(desc->host_addr),
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le16_to_cpu(desc->len),
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PCI_DMA_TODEVICE);
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kfree(priv->tx_buf_mgmt[i]);
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priv->tx_buf_mgmt[i] = NULL;
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}
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memset(ring_control, 0, sizeof(*ring_control));
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}
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static int __devinit p54p_probe(struct pci_dev *pdev,
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@ -585,6 +664,7 @@ static int __devinit p54p_probe(struct pci_dev *pdev,
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priv->common.tx = p54p_tx;
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spin_lock_init(&priv->lock);
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tasklet_init(&priv->rx_tasklet, p54p_rx_tasklet, (unsigned long)dev);
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err = ieee80211_register_hw(dev);
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if (err) {
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@ -92,13 +92,17 @@ struct p54p_priv {
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struct p54_common common;
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struct pci_dev *pdev;
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struct p54p_csr __iomem *map;
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struct tasklet_struct rx_tasklet;
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spinlock_t lock;
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struct p54p_ring_control *ring_control;
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dma_addr_t ring_control_dma;
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u32 rx_idx, tx_idx;
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struct sk_buff *rx_buf[8];
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void *tx_buf[32];
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u32 rx_idx_data, tx_idx_data;
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u32 rx_idx_mgmt, tx_idx_mgmt;
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struct sk_buff *rx_buf_data[8];
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struct sk_buff *rx_buf_mgmt[4];
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void *tx_buf_data[32];
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void *tx_buf_mgmt[4];
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struct completion boot_comp;
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};
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