gpio: Add Cadence GPIO driver
This patch adds a driver for Cadence GPIO controller. It can be enabled with GPIO_CADENCE Kconfig option. It uses generic GPIO infrastructure and works as an interrupt controller. At the moment it only supports level sensitive irqs. Signed-off-by: Jan Kotas <jank@cadence.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Jan Kotas
Linus Walleij
Родитель
e4b194aa0b
Коммит
72ab2f7631
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@ -160,6 +160,14 @@ config GPIO_BRCMSTB
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help
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Say yes here to enable GPIO support for Broadcom STB (BCM7XXX) SoCs.
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config GPIO_CADENCE
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tristate "Cadence GPIO support"
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depends on OF_GPIO
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select GPIO_GENERIC
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select GPIOLIB_IRQCHIP
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help
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Say yes here to enable support for Cadence GPIO controller.
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config GPIO_CLPS711X
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tristate "CLPS711X GPIO support"
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depends on ARCH_CLPS711X || COMPILE_TEST
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@ -37,6 +37,7 @@ obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o
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obj-$(CONFIG_GPIO_BD9571MWV) += gpio-bd9571mwv.o
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obj-$(CONFIG_GPIO_BRCMSTB) += gpio-brcmstb.o
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obj-$(CONFIG_GPIO_BT8XX) += gpio-bt8xx.o
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obj-$(CONFIG_GPIO_CADENCE) += gpio-cadence.o
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obj-$(CONFIG_GPIO_CLPS711X) += gpio-clps711x.o
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obj-$(CONFIG_GPIO_CS5535) += gpio-cs5535.o
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obj-$(CONFIG_GPIO_CRYSTAL_COVE) += gpio-crystalcove.o
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@ -0,0 +1,291 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2017-2018 Cadence
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*
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* Authors:
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* Jan Kotas <jank@cadence.com>
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* Boris Brezillon <boris.brezillon@free-electrons.com>
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*/
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#include <linux/gpio/driver.h>
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#define CDNS_GPIO_BYPASS_MODE 0x00
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#define CDNS_GPIO_DIRECTION_MODE 0x04
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#define CDNS_GPIO_OUTPUT_EN 0x08
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#define CDNS_GPIO_OUTPUT_VALUE 0x0c
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#define CDNS_GPIO_INPUT_VALUE 0x10
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#define CDNS_GPIO_IRQ_MASK 0x14
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#define CDNS_GPIO_IRQ_EN 0x18
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#define CDNS_GPIO_IRQ_DIS 0x1c
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#define CDNS_GPIO_IRQ_STATUS 0x20
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#define CDNS_GPIO_IRQ_TYPE 0x24
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#define CDNS_GPIO_IRQ_VALUE 0x28
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#define CDNS_GPIO_IRQ_ANY_EDGE 0x2c
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struct cdns_gpio_chip {
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struct gpio_chip gc;
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struct clk *pclk;
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void __iomem *regs;
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u32 bypass_orig;
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};
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static int cdns_gpio_request(struct gpio_chip *chip, unsigned int offset)
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{
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struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);
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unsigned long flags;
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spin_lock_irqsave(&chip->bgpio_lock, flags);
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iowrite32(ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE) & ~BIT(offset),
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cgpio->regs + CDNS_GPIO_BYPASS_MODE);
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spin_unlock_irqrestore(&chip->bgpio_lock, flags);
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return 0;
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}
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static void cdns_gpio_free(struct gpio_chip *chip, unsigned int offset)
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{
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struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);
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unsigned long flags;
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spin_lock_irqsave(&chip->bgpio_lock, flags);
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iowrite32(ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE) |
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(BIT(offset) & cgpio->bypass_orig),
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cgpio->regs + CDNS_GPIO_BYPASS_MODE);
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spin_unlock_irqrestore(&chip->bgpio_lock, flags);
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}
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static void cdns_gpio_irq_mask(struct irq_data *d)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
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struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);
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iowrite32(BIT(d->hwirq), cgpio->regs + CDNS_GPIO_IRQ_DIS);
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}
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static void cdns_gpio_irq_unmask(struct irq_data *d)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
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struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);
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iowrite32(BIT(d->hwirq), cgpio->regs + CDNS_GPIO_IRQ_EN);
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}
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static int cdns_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
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struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);
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unsigned long flags;
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u32 int_value;
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u32 int_type;
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u32 mask = BIT(d->hwirq);
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int ret = 0;
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spin_lock_irqsave(&chip->bgpio_lock, flags);
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int_value = ioread32(cgpio->regs + CDNS_GPIO_IRQ_VALUE) & ~mask;
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int_type = ioread32(cgpio->regs + CDNS_GPIO_IRQ_TYPE) & ~mask;
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/*
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* The GPIO controller doesn't have an ACK register.
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* All interrupt statuses are cleared on a status register read.
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* Don't support edge interrupts for now.
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*/
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if (type == IRQ_TYPE_LEVEL_HIGH) {
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int_type |= mask;
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int_value |= mask;
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} else if (type == IRQ_TYPE_LEVEL_LOW) {
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int_type |= mask;
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} else {
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ret = -EINVAL;
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goto err_irq_type;
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}
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iowrite32(int_value, cgpio->regs + CDNS_GPIO_IRQ_VALUE);
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iowrite32(int_type, cgpio->regs + CDNS_GPIO_IRQ_TYPE);
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err_irq_type:
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spin_unlock_irqrestore(&chip->bgpio_lock, flags);
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return ret;
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}
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static void cdns_gpio_irq_handler(struct irq_desc *desc)
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{
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struct gpio_chip *chip = irq_desc_get_handler_data(desc);
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struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);
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struct irq_chip *irqchip = irq_desc_get_chip(desc);
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unsigned long status;
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int hwirq;
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chained_irq_enter(irqchip, desc);
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status = ioread32(cgpio->regs + CDNS_GPIO_IRQ_STATUS) &
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~ioread32(cgpio->regs + CDNS_GPIO_IRQ_MASK);
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for_each_set_bit(hwirq, &status, chip->ngpio)
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generic_handle_irq(irq_find_mapping(chip->irq.domain, hwirq));
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chained_irq_exit(irqchip, desc);
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}
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static struct irq_chip cdns_gpio_irqchip = {
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.name = "cdns-gpio",
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.irq_mask = cdns_gpio_irq_mask,
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.irq_unmask = cdns_gpio_irq_unmask,
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.irq_set_type = cdns_gpio_irq_set_type
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};
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static int cdns_gpio_probe(struct platform_device *pdev)
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{
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struct cdns_gpio_chip *cgpio;
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struct resource *res;
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int ret, irq;
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u32 dir_prev;
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u32 num_gpios = 32;
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cgpio = devm_kzalloc(&pdev->dev, sizeof(*cgpio), GFP_KERNEL);
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if (!cgpio)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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cgpio->regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(cgpio->regs))
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return PTR_ERR(cgpio->regs);
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of_property_read_u32(pdev->dev.of_node, "ngpios", &num_gpios);
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if (num_gpios > 32) {
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dev_err(&pdev->dev, "ngpios must be less or equal 32\n");
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return -EINVAL;
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}
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/*
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* Set all pins as inputs by default, otherwise:
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* gpiochip_lock_as_irq:
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* tried to flag a GPIO set as output for IRQ
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* Generic GPIO driver stores the direction value internally,
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* so it needs to be changed before bgpio_init() is called.
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*/
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dir_prev = ioread32(cgpio->regs + CDNS_GPIO_DIRECTION_MODE);
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iowrite32(GENMASK(num_gpios - 1, 0),
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cgpio->regs + CDNS_GPIO_DIRECTION_MODE);
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ret = bgpio_init(&cgpio->gc, &pdev->dev, 4,
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cgpio->regs + CDNS_GPIO_INPUT_VALUE,
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cgpio->regs + CDNS_GPIO_OUTPUT_VALUE,
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NULL,
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NULL,
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cgpio->regs + CDNS_GPIO_DIRECTION_MODE,
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BGPIOF_READ_OUTPUT_REG_SET);
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if (ret) {
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dev_err(&pdev->dev, "Failed to register generic gpio, %d\n",
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ret);
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goto err_revert_dir;
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}
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cgpio->gc.label = dev_name(&pdev->dev);
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cgpio->gc.ngpio = num_gpios;
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cgpio->gc.parent = &pdev->dev;
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cgpio->gc.base = -1;
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cgpio->gc.owner = THIS_MODULE;
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cgpio->gc.request = cdns_gpio_request;
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cgpio->gc.free = cdns_gpio_free;
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cgpio->pclk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(cgpio->pclk)) {
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ret = PTR_ERR(cgpio->pclk);
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dev_err(&pdev->dev,
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"Failed to retrieve peripheral clock, %d\n", ret);
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goto err_revert_dir;
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}
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ret = clk_prepare_enable(cgpio->pclk);
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if (ret) {
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dev_err(&pdev->dev,
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"Failed to enable the peripheral clock, %d\n", ret);
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goto err_revert_dir;
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}
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ret = devm_gpiochip_add_data(&pdev->dev, &cgpio->gc, cgpio);
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if (ret < 0) {
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dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret);
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goto err_disable_clk;
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}
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/*
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* irq_chip support
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*/
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irq = platform_get_irq(pdev, 0);
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if (irq >= 0) {
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ret = gpiochip_irqchip_add(&cgpio->gc, &cdns_gpio_irqchip,
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0, handle_level_irq,
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IRQ_TYPE_NONE);
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if (ret) {
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dev_err(&pdev->dev, "Could not add irqchip, %d\n",
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ret);
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goto err_disable_clk;
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}
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gpiochip_set_chained_irqchip(&cgpio->gc, &cdns_gpio_irqchip,
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irq, cdns_gpio_irq_handler);
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}
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cgpio->bypass_orig = ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE);
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/*
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* Enable gpio outputs, ignored for input direction
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*/
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iowrite32(GENMASK(num_gpios - 1, 0),
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cgpio->regs + CDNS_GPIO_OUTPUT_EN);
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iowrite32(0, cgpio->regs + CDNS_GPIO_BYPASS_MODE);
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platform_set_drvdata(pdev, cgpio);
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return 0;
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err_disable_clk:
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clk_disable_unprepare(cgpio->pclk);
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err_revert_dir:
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iowrite32(dir_prev, cgpio->regs + CDNS_GPIO_DIRECTION_MODE);
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return ret;
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}
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static int cdns_gpio_remove(struct platform_device *pdev)
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{
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struct cdns_gpio_chip *cgpio = platform_get_drvdata(pdev);
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iowrite32(cgpio->bypass_orig, cgpio->regs + CDNS_GPIO_BYPASS_MODE);
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clk_disable_unprepare(cgpio->pclk);
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return 0;
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}
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static const struct of_device_id cdns_of_ids[] = {
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{ .compatible = "cdns,gpio-r1p02" },
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{ /* sentinel */ },
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};
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static struct platform_driver cdns_gpio_driver = {
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.driver = {
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.name = "cdns-gpio",
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.of_match_table = cdns_of_ids,
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},
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.probe = cdns_gpio_probe,
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.remove = cdns_gpio_remove,
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};
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module_platform_driver(cdns_gpio_driver);
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MODULE_AUTHOR("Jan Kotas <jank@cadence.com>");
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MODULE_DESCRIPTION("Cadence GPIO driver");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:cdns-gpio");
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