drm/i915/suspend: Flush register writes before busy-waiting.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
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d5dd96cb28
Коммит
72bcb26909
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@ -395,16 +395,20 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
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if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
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I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A &
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~DPLL_VCO_ENABLE);
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DRM_UDELAY(150);
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POSTING_READ(dpll_a_reg);
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udelay(150);
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}
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I915_WRITE(fpa0_reg, dev_priv->saveFPA0);
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I915_WRITE(fpa1_reg, dev_priv->saveFPA1);
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/* Actually enable it */
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I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A);
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DRM_UDELAY(150);
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if (IS_I965G(dev) && !IS_IRONLAKE(dev))
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POSTING_READ(dpll_a_reg);
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udelay(150);
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if (IS_I965G(dev) && !IS_IRONLAKE(dev)) {
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I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
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DRM_UDELAY(150);
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POSTING_READ(DPLL_A_MD);
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}
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udelay(150);
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/* Restore mode */
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I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
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@ -460,16 +464,20 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
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if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
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I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B &
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~DPLL_VCO_ENABLE);
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DRM_UDELAY(150);
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POSTING_READ(dpll_b_reg);
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udelay(150);
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}
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I915_WRITE(fpb0_reg, dev_priv->saveFPB0);
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I915_WRITE(fpb1_reg, dev_priv->saveFPB1);
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/* Actually enable it */
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I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B);
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DRM_UDELAY(150);
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if (IS_I965G(dev) && !IS_IRONLAKE(dev))
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POSTING_READ(dpll_b_reg);
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udelay(150);
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if (IS_I965G(dev) && !IS_IRONLAKE(dev)) {
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I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
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DRM_UDELAY(150);
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POSTING_READ(DPLL_B_MD);
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}
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udelay(150);
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/* Restore mode */
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I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
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@ -730,7 +738,8 @@ void i915_restore_display(struct drm_device *dev)
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I915_WRITE(VGA0, dev_priv->saveVGA0);
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I915_WRITE(VGA1, dev_priv->saveVGA1);
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I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
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DRM_UDELAY(150);
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POSTING_READ(VGA_PD);
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udelay(150);
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i915_restore_vga(dev);
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}
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