thermal: exynos: add ->tmu_initialize method
Add ->tmu_initialize method to struct exynos_tmu_data and use it in exynos_tmu_initialize(). Then add ->tmu_initialize implementations for Exynos4210, Exynos4412+ and Exynos5440. Finally remove no longer needed reg->threshold_th[0,1], reg->intclr_[fall,rise]_shift and reg->intclr_[rise,fall]_mask abstractions. There are more improvements available in the future on top of this patch like merging HW_TRIP level setting with setting of other levels for Exynos4412+ or adding separate method for clearing IRQs using INTCLEAR register (for Exynos5420, Exynos5260 and Exynos4412+). There should be no functional changes caused by this patch. Cc: Amit Daniel Kachhap <amit.daniel@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Eduardo Valentin <edubezval@gmail.com> Cc: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
This commit is contained in:
Bartlomiej Zolnierkiewicz
Eduardo Valentin
Родитель
fe87789cd4
Коммит
72d1100b73
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@ -52,6 +52,7 @@
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* @temp_error2: fused value of the second point trim.
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* @regulator: pointer to the TMU regulator structure.
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* @reg_conf: pointer to structure to register with core thermal.
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* @tmu_initialize: SoC specific TMU initialization method
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*/
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struct exynos_tmu_data {
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int id;
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@ -66,6 +67,7 @@ struct exynos_tmu_data {
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u8 temp_error1, temp_error2;
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struct regulator *regulator;
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struct thermal_sensor_conf *reg_conf;
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int (*tmu_initialize)(struct platform_device *pdev);
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};
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/*
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@ -180,118 +182,13 @@ static u32 get_th_reg(struct exynos_tmu_data *data, u32 threshold, bool falling)
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static int exynos_tmu_initialize(struct platform_device *pdev)
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{
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struct exynos_tmu_data *data = platform_get_drvdata(pdev);
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struct exynos_tmu_platform_data *pdata = data->pdata;
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const struct exynos_tmu_registers *reg = pdata->registers;
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unsigned int status, trim_info = 0, con, ctrl;
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unsigned int rising_threshold = 0, falling_threshold = 0;
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int ret = 0, threshold_code, i;
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int ret;
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mutex_lock(&data->lock);
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clk_enable(data->clk);
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if (!IS_ERR(data->clk_sec))
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clk_enable(data->clk_sec);
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if (data->soc != SOC_ARCH_EXYNOS5440) {
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status = readb(data->base + EXYNOS_TMU_REG_STATUS);
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if (!status) {
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ret = -EBUSY;
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goto out;
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}
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}
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if (data->soc == SOC_ARCH_EXYNOS3250 ||
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data->soc == SOC_ARCH_EXYNOS4412 ||
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data->soc == SOC_ARCH_EXYNOS5250) {
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if (data->soc == SOC_ARCH_EXYNOS3250) {
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ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON1);
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ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE;
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writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON1);
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}
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ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON2);
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ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE;
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writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON2);
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}
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/* Save trimming info in order to perform calibration */
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if (data->soc == SOC_ARCH_EXYNOS5440) {
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/*
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* For exynos5440 soc triminfo value is swapped between TMU0 and
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* TMU2, so the below logic is needed.
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*/
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switch (data->id) {
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case 0:
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trim_info = readl(data->base +
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EXYNOS5440_EFUSE_SWAP_OFFSET + EXYNOS5440_TMU_S0_7_TRIM);
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break;
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case 1:
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trim_info = readl(data->base + EXYNOS5440_TMU_S0_7_TRIM);
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break;
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case 2:
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trim_info = readl(data->base -
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EXYNOS5440_EFUSE_SWAP_OFFSET + EXYNOS5440_TMU_S0_7_TRIM);
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}
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} else {
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/* On exynos5420 the triminfo register is in the shared space */
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if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO)
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trim_info = readl(data->base_second +
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EXYNOS_TMU_REG_TRIMINFO);
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else
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trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
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}
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sanitize_temp_error(data, trim_info);
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if (data->soc == SOC_ARCH_EXYNOS4210) {
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/* Write temperature code for threshold */
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threshold_code = temp_to_code(data, pdata->threshold);
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writeb(threshold_code,
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data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP);
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for (i = 0; i < pdata->non_hw_trigger_levels; i++)
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writeb(pdata->trigger_levels[i], data->base +
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reg->threshold_th0 + i * sizeof(reg->threshold_th0));
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exynos_tmu_clear_irqs(data);
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} else {
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/* Write temperature code for rising and falling threshold */
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rising_threshold = readl(data->base + reg->threshold_th0);
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rising_threshold = get_th_reg(data, rising_threshold, false);
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if (data->soc != SOC_ARCH_EXYNOS5440)
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falling_threshold = get_th_reg(data, 0, true);
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writel(rising_threshold,
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data->base + reg->threshold_th0);
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writel(falling_threshold,
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data->base + reg->threshold_th1);
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exynos_tmu_clear_irqs(data);
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/* if last threshold limit is also present */
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i = pdata->max_trigger_level - 1;
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if (pdata->trigger_levels[i] &&
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(pdata->trigger_type[i] == HW_TRIP)) {
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threshold_code = temp_to_code(data,
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pdata->trigger_levels[i]);
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if (data->soc != SOC_ARCH_EXYNOS5440) {
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/* 1-4 level to be assigned in th0 reg */
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rising_threshold &= ~(0xff << 8 * i);
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rising_threshold |= threshold_code << 8 * i;
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writel(rising_threshold,
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data->base + EXYNOS_THD_TEMP_RISE);
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} else {
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/* 5th level to be assigned in th2 reg */
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rising_threshold =
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threshold_code << EXYNOS5440_TMU_TH_RISE4_SHIFT;
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writel(rising_threshold,
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data->base + EXYNOS5440_TMU_S0_7_TH2);
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}
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con = readl(data->base + reg->tmu_ctrl);
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con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
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writel(con, data->base + reg->tmu_ctrl);
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}
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}
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/*Clear the PMIN in the common TMU register*/
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if (data->soc == SOC_ARCH_EXYNOS5440 && !data->id)
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writel(0, data->base_second + EXYNOS5440_TMU_PMIN);
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out:
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ret = data->tmu_initialize(pdev);
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clk_disable(data->clk);
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mutex_unlock(&data->lock);
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if (!IS_ERR(data->clk_sec))
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@ -347,6 +244,143 @@ static void exynos_tmu_control(struct platform_device *pdev, bool on)
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mutex_unlock(&data->lock);
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}
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static int exynos4210_tmu_initialize(struct platform_device *pdev)
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{
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struct exynos_tmu_data *data = platform_get_drvdata(pdev);
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struct exynos_tmu_platform_data *pdata = data->pdata;
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unsigned int status;
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int ret = 0, threshold_code, i;
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status = readb(data->base + EXYNOS_TMU_REG_STATUS);
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if (!status) {
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ret = -EBUSY;
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goto out;
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}
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sanitize_temp_error(data, readl(data->base + EXYNOS_TMU_REG_TRIMINFO));
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/* Write temperature code for threshold */
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threshold_code = temp_to_code(data, pdata->threshold);
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writeb(threshold_code, data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP);
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for (i = 0; i < pdata->non_hw_trigger_levels; i++)
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writeb(pdata->trigger_levels[i], data->base +
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EXYNOS4210_TMU_REG_TRIG_LEVEL0 + i * 4);
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exynos_tmu_clear_irqs(data);
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out:
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return ret;
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}
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static int exynos4412_tmu_initialize(struct platform_device *pdev)
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{
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struct exynos_tmu_data *data = platform_get_drvdata(pdev);
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struct exynos_tmu_platform_data *pdata = data->pdata;
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unsigned int status, trim_info, con, ctrl, rising_threshold;
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int ret = 0, threshold_code, i;
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status = readb(data->base + EXYNOS_TMU_REG_STATUS);
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if (!status) {
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ret = -EBUSY;
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goto out;
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}
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if (data->soc == SOC_ARCH_EXYNOS3250 ||
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data->soc == SOC_ARCH_EXYNOS4412 ||
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data->soc == SOC_ARCH_EXYNOS5250) {
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if (data->soc == SOC_ARCH_EXYNOS3250) {
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ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON1);
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ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE;
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writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON1);
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}
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ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON2);
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ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE;
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writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON2);
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}
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/* On exynos5420 the triminfo register is in the shared space */
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if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO)
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trim_info = readl(data->base_second + EXYNOS_TMU_REG_TRIMINFO);
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else
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trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
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sanitize_temp_error(data, trim_info);
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/* Write temperature code for rising and falling threshold */
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rising_threshold = readl(data->base + EXYNOS_THD_TEMP_RISE);
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rising_threshold = get_th_reg(data, rising_threshold, false);
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writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE);
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writel(get_th_reg(data, 0, true), data->base + EXYNOS_THD_TEMP_FALL);
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exynos_tmu_clear_irqs(data);
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/* if last threshold limit is also present */
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i = pdata->max_trigger_level - 1;
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if (pdata->trigger_levels[i] && pdata->trigger_type[i] == HW_TRIP) {
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threshold_code = temp_to_code(data, pdata->trigger_levels[i]);
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/* 1-4 level to be assigned in th0 reg */
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rising_threshold &= ~(0xff << 8 * i);
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rising_threshold |= threshold_code << 8 * i;
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writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE);
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con = readl(data->base + EXYNOS_TMU_REG_CONTROL);
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con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
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writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
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}
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out:
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return ret;
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}
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static int exynos5440_tmu_initialize(struct platform_device *pdev)
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{
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struct exynos_tmu_data *data = platform_get_drvdata(pdev);
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struct exynos_tmu_platform_data *pdata = data->pdata;
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unsigned int trim_info = 0, con, rising_threshold;
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int ret = 0, threshold_code, i;
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/*
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* For exynos5440 soc triminfo value is swapped between TMU0 and
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* TMU2, so the below logic is needed.
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*/
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switch (data->id) {
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case 0:
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trim_info = readl(data->base + EXYNOS5440_EFUSE_SWAP_OFFSET +
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EXYNOS5440_TMU_S0_7_TRIM);
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break;
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case 1:
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trim_info = readl(data->base + EXYNOS5440_TMU_S0_7_TRIM);
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break;
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case 2:
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trim_info = readl(data->base - EXYNOS5440_EFUSE_SWAP_OFFSET +
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EXYNOS5440_TMU_S0_7_TRIM);
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}
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sanitize_temp_error(data, trim_info);
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/* Write temperature code for rising and falling threshold */
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rising_threshold = readl(data->base + EXYNOS5440_TMU_S0_7_TH0);
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rising_threshold = get_th_reg(data, rising_threshold, false);
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writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH0);
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writel(0, data->base + EXYNOS5440_TMU_S0_7_TH1);
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exynos_tmu_clear_irqs(data);
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/* if last threshold limit is also present */
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i = pdata->max_trigger_level - 1;
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if (pdata->trigger_levels[i] && pdata->trigger_type[i] == HW_TRIP) {
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threshold_code = temp_to_code(data, pdata->trigger_levels[i]);
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/* 5th level to be assigned in th2 reg */
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rising_threshold =
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threshold_code << EXYNOS5440_TMU_TH_RISE4_SHIFT;
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writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH2);
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con = readl(data->base + EXYNOS5440_TMU_S0_7_CTRL);
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con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
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writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL);
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}
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/* Clear the PMIN in the common TMU register */
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if (!data->id)
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writel(0, data->base_second + EXYNOS5440_TMU_PMIN);
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return ret;
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}
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static int exynos_tmu_read(struct exynos_tmu_data *data)
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{
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struct exynos_tmu_platform_data *pdata = data->pdata;
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@ -639,16 +673,24 @@ static int exynos_tmu_probe(struct platform_device *pdev)
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goto err_clk_sec;
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}
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if (pdata->type == SOC_ARCH_EXYNOS3250 ||
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pdata->type == SOC_ARCH_EXYNOS4210 ||
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pdata->type == SOC_ARCH_EXYNOS4412 ||
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pdata->type == SOC_ARCH_EXYNOS5250 ||
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pdata->type == SOC_ARCH_EXYNOS5260 ||
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pdata->type == SOC_ARCH_EXYNOS5420 ||
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pdata->type == SOC_ARCH_EXYNOS5420_TRIMINFO ||
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pdata->type == SOC_ARCH_EXYNOS5440)
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data->soc = pdata->type;
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else {
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data->soc = pdata->type;
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switch (data->soc) {
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case SOC_ARCH_EXYNOS4210:
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data->tmu_initialize = exynos4210_tmu_initialize;
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break;
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case SOC_ARCH_EXYNOS3250:
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case SOC_ARCH_EXYNOS4412:
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case SOC_ARCH_EXYNOS5250:
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case SOC_ARCH_EXYNOS5260:
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case SOC_ARCH_EXYNOS5420:
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case SOC_ARCH_EXYNOS5420_TRIMINFO:
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data->tmu_initialize = exynos4412_tmu_initialize;
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break;
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case SOC_ARCH_EXYNOS5440:
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data->tmu_initialize = exynos5440_tmu_initialize;
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break;
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default:
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ret = -EINVAL;
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dev_err(&pdev->dev, "Platform not supported\n");
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goto err_clk;
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@ -73,8 +73,6 @@ enum soc_type {
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* slightly across different exynos SOC's.
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* @tmu_ctrl: TMU main controller register.
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* @tmu_cur_temp: register containing the current temperature of the TMU.
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* @threshold_th0: Register containing first set of rising levels.
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* @threshold_th1: Register containing second set of rising levels.
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* @tmu_inten: register containing the different threshold interrupt
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enable bits.
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* @inten_rise0_shift: shift bits of rising 0 interrupt bits.
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@ -91,9 +89,6 @@ struct exynos_tmu_registers {
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u32 tmu_cur_temp;
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u32 threshold_th0;
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u32 threshold_th1;
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u32 tmu_inten;
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u32 inten_rise0_shift;
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u32 inten_rise1_shift;
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@ -28,7 +28,6 @@
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static const struct exynos_tmu_registers exynos4210_tmu_registers = {
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
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.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
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.threshold_th0 = EXYNOS4210_TMU_REG_TRIG_LEVEL0,
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.tmu_inten = EXYNOS_TMU_REG_INTEN,
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.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
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.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
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@ -83,8 +82,6 @@ struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
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static const struct exynos_tmu_registers exynos3250_tmu_registers = {
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
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.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
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.threshold_th0 = EXYNOS_THD_TEMP_RISE,
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.threshold_th1 = EXYNOS_THD_TEMP_FALL,
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.tmu_inten = EXYNOS_TMU_REG_INTEN,
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.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
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.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
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@ -152,8 +149,6 @@ struct exynos_tmu_init_data const exynos3250_default_tmu_data = {
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static const struct exynos_tmu_registers exynos4412_tmu_registers = {
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
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.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
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.threshold_th0 = EXYNOS_THD_TEMP_RISE,
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.threshold_th1 = EXYNOS_THD_TEMP_FALL,
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.tmu_inten = EXYNOS_TMU_REG_INTEN,
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.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
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.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
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@ -234,8 +229,6 @@ struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
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static const struct exynos_tmu_registers exynos5260_tmu_registers = {
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
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.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
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.threshold_th0 = EXYNOS_THD_TEMP_RISE,
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.threshold_th1 = EXYNOS_THD_TEMP_FALL,
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.tmu_inten = EXYNOS5260_TMU_REG_INTEN,
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.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
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.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
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@ -306,8 +299,6 @@ struct exynos_tmu_init_data const exynos5260_default_tmu_data = {
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static const struct exynos_tmu_registers exynos5420_tmu_registers = {
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
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.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
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.threshold_th0 = EXYNOS_THD_TEMP_RISE,
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.threshold_th1 = EXYNOS_THD_TEMP_FALL,
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.tmu_inten = EXYNOS_TMU_REG_INTEN,
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.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
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.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
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@ -385,8 +376,6 @@ struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
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static const struct exynos_tmu_registers exynos5440_tmu_registers = {
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.tmu_ctrl = EXYNOS5440_TMU_S0_7_CTRL,
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.tmu_cur_temp = EXYNOS5440_TMU_S0_7_TEMP,
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.threshold_th0 = EXYNOS5440_TMU_S0_7_TH0,
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.threshold_th1 = EXYNOS5440_TMU_S0_7_TH1,
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.tmu_inten = EXYNOS5440_TMU_S0_7_IRQEN,
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.inten_rise0_shift = EXYNOS5440_TMU_INTEN_RISE0_SHIFT,
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.inten_rise1_shift = EXYNOS5440_TMU_INTEN_RISE1_SHIFT,
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