powerpc: Add VSX assembler code macros
This adds the macros for the VSX load/store instruction as most binutils are not going to support this for a while. Also add VSX register save/restore macros and vsr[0-63] register definitions. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Michael Neuling
Paul Mackerras
Родитель
b962ce9d26
Коммит
72ffff5b17
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@ -24,6 +24,29 @@
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#ifdef CONFIG_VSX
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#define REST_32FPVSRS(n,c,base) \
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BEGIN_FTR_SECTION \
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b 2f; \
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END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
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REST_32FPRS(n,base); \
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b 3f; \
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2: REST_32VSRS(n,c,base); \
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3:
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#define SAVE_32FPVSRS(n,c,base) \
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BEGIN_FTR_SECTION \
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b 2f; \
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END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
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SAVE_32FPRS(n,base); \
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b 3f; \
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2: SAVE_32VSRS(n,c,base); \
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3:
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#else
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#define REST_32FPVSRS(n,b,base) REST_32FPRS(n, base)
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#define SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base)
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#endif
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/*
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* This task wants to use the FPU now.
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* On UP, disable FP for the task which had the FPU previously,
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@ -74,6 +74,15 @@ END_FTR_SECTION_IFCLR(CPU_FTR_PURR); \
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REST_10GPRS(22, base)
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#endif
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/*
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* Define what the VSX XX1 form instructions will look like, then add
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* the 128 bit load store instructions based on that.
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*/
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#define VSX_XX1(xs, ra, rb) (((xs) & 0x1f) << 21 | ((ra) << 16) | \
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((rb) << 11) | (((xs) >> 5)))
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#define STXVD2X(xs, ra, rb) .long (0x7c000798 | VSX_XX1((xs), (ra), (rb)))
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#define LXVD2X(xs, ra, rb) .long (0x7c000698 | VSX_XX1((xs), (ra), (rb)))
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#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
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#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
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@ -110,6 +119,33 @@ END_FTR_SECTION_IFCLR(CPU_FTR_PURR); \
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#define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
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#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
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/* Save the lower 32 VSRs in the thread VSR region */
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#define SAVE_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); STXVD2X(n,b,base)
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#define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
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#define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
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#define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
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#define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
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#define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
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#define REST_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); LXVD2X(n,b,base)
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#define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base)
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#define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
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#define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
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#define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
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#define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
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/* Save the upper 32 VSRs (32-63) in the thread VSX region (0-31) */
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#define SAVE_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); STXVD2X(n+32,b,base)
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#define SAVE_2VSRSU(n,b,base) SAVE_VSRU(n,b,base); SAVE_VSRU(n+1,b,base)
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#define SAVE_4VSRSU(n,b,base) SAVE_2VSRSU(n,b,base); SAVE_2VSRSU(n+2,b,base)
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#define SAVE_8VSRSU(n,b,base) SAVE_4VSRSU(n,b,base); SAVE_4VSRSU(n+4,b,base)
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#define SAVE_16VSRSU(n,b,base) SAVE_8VSRSU(n,b,base); SAVE_8VSRSU(n+8,b,base)
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#define SAVE_32VSRSU(n,b,base) SAVE_16VSRSU(n,b,base); SAVE_16VSRSU(n+16,b,base)
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#define REST_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,b,base)
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#define REST_2VSRSU(n,b,base) REST_VSRU(n,b,base); REST_VSRU(n+1,b,base)
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#define REST_4VSRSU(n,b,base) REST_2VSRSU(n,b,base); REST_2VSRSU(n+2,b,base)
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#define REST_8VSRSU(n,b,base) REST_4VSRSU(n,b,base); REST_4VSRSU(n+4,b,base)
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#define REST_16VSRSU(n,b,base) REST_8VSRSU(n,b,base); REST_8VSRSU(n+8,b,base)
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#define REST_32VSRSU(n,b,base) REST_16VSRSU(n,b,base); REST_16VSRSU(n+16,b,base)
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#define SAVE_EVR(n,s,base) evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
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#define SAVE_2EVRS(n,s,base) SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
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#define SAVE_4EVRS(n,s,base) SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base)
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@ -540,6 +576,73 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
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#define vr30 30
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#define vr31 31
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/* VSX Registers (VSRs) */
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#define vsr0 0
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#define vsr1 1
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#define vsr2 2
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#define vsr3 3
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#define vsr4 4
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#define vsr5 5
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#define vsr6 6
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#define vsr7 7
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#define vsr8 8
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#define vsr9 9
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#define vsr10 10
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#define vsr11 11
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#define vsr12 12
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#define vsr13 13
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#define vsr14 14
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#define vsr15 15
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#define vsr16 16
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#define vsr17 17
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#define vsr18 18
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#define vsr19 19
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#define vsr20 20
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#define vsr21 21
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#define vsr22 22
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#define vsr23 23
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#define vsr24 24
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#define vsr25 25
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#define vsr26 26
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#define vsr27 27
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#define vsr28 28
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#define vsr29 29
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#define vsr30 30
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#define vsr31 31
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#define vsr32 32
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#define vsr33 33
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#define vsr34 34
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#define vsr35 35
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#define vsr36 36
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#define vsr37 37
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#define vsr38 38
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#define vsr39 39
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#define vsr40 40
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#define vsr41 41
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#define vsr42 42
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#define vsr43 43
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#define vsr44 44
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#define vsr45 45
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#define vsr46 46
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#define vsr47 47
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#define vsr48 48
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#define vsr49 49
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#define vsr50 50
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#define vsr51 51
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#define vsr52 52
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#define vsr53 53
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#define vsr54 54
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#define vsr55 55
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#define vsr56 56
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#define vsr57 57
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#define vsr58 58
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#define vsr59 59
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#define vsr60 60
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#define vsr61 61
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#define vsr62 62
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#define vsr63 63
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/* SPE Registers (EVPRs) */
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#define evr0 0
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