[POWERPC] cpm2: CPM2 interrupt controller fix
This contains important fixes for the CPM2 PIC code. Eliminated CPM_IRQ_OFFSET, pulling the respective interrupt numbers from the interrupt mapping. Updated devicetree files to reflect that. Changed direct IC-related IO accesses to the IO accessors. Fixed all the sense values to keep coherency with ipic. In the current code, CPM2 stuff will have no IRQs and hence could be hardly usable. Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Vitaly Bordug
Paul Mackerras
Родитель
c19cdcb1b8
Коммит
73844ecbaa
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@ -53,6 +53,13 @@
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reg = <00000000 4000000 f4500000 00000020>;
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};
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chosen {
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name = "chosen";
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linux,platform = <0>;
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interrupt-controller = <10c00>;
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linux,phandle = <400>;
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};
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soc8272@f0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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@ -71,7 +78,7 @@
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ethernet-phy@0 {
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linux,phandle = <2452000>;
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interrupt-parent = <10c00>;
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interrupts = <19 1>;
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interrupts = <17 4>;
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reg = <0>;
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bitbang = [ 12 12 13 02 02 01 ];
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device_type = "ethernet-phy";
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@ -79,7 +86,7 @@
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ethernet-phy@1 {
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linux,phandle = <2452001>;
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interrupt-parent = <10c00>;
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interrupts = <19 1>;
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interrupts = <17 4>;
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bitbang = [ 12 12 13 02 02 01 ];
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reg = <3>;
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device_type = "ethernet-phy";
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@ -90,7 +97,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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device_type = "network";
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device-id = <2>;
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device-id = <1>;
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compatible = "fs_enet";
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model = "FCC";
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reg = <11300 20 8400 100 11380 30>;
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@ -104,7 +111,7 @@
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ethernet@25000 {
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device_type = "network";
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device-id = <3>;
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device-id = <2>;
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compatible = "fs_enet";
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model = "FCC";
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reg = <11320 20 8500 100 113b0 30>;
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@ -133,7 +140,7 @@
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device_type = "serial";
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compatible = "cpm_uart";
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model = "SCC";
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device-id = <2>;
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device-id = <1>;
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reg = <11a00 20 8000 100>;
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current-speed = <1c200>;
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interrupts = <28 2>;
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@ -147,7 +154,7 @@
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device_type = "serial";
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compatible = "cpm_uart";
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model = "SCC";
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device-id = <5>;
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device-id = <4>;
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reg = <11a60 20 8300 100>;
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current-speed = <1c200>;
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interrupts = <2b 2>;
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@ -181,24 +188,24 @@
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interrupt-map = <
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/* IDSEL 0x16 */
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b000 0 0 1 f8200000 40 0
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b000 0 0 2 f8200000 41 0
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b000 0 0 3 f8200000 42 0
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b000 0 0 4 f8200000 43 0
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b000 0 0 1 f8200000 40 8
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b000 0 0 2 f8200000 41 8
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b000 0 0 3 f8200000 42 8
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b000 0 0 4 f8200000 43 8
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/* IDSEL 0x17 */
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b800 0 0 1 f8200000 43 0
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b800 0 0 2 f8200000 40 0
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b800 0 0 3 f8200000 41 0
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b800 0 0 4 f8200000 42 0
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b800 0 0 1 f8200000 43 8
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b800 0 0 2 f8200000 40 8
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b800 0 0 3 f8200000 41 8
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b800 0 0 4 f8200000 42 8
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/* IDSEL 0x18 */
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c000 0 0 1 f8200000 42 0
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c000 0 0 2 f8200000 43 0
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c000 0 0 3 f8200000 40 0
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c000 0 0 4 f8200000 41 0>;
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c000 0 0 1 f8200000 42 8
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c000 0 0 2 f8200000 43 8
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c000 0 0 3 f8200000 40 8
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c000 0 0 4 f8200000 41 8>;
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interrupt-parent = <10c00>;
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interrupts = <14 3>;
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interrupts = <14 8>;
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bus-range = <0 0>;
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ranges = <02000000 0 80000000 80000000 0 40000000
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01000000 0 00000000 f6000000 0 02000000>;
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@ -210,7 +217,7 @@
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model = "SEC2";
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compatible = "talitos";
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reg = <30000 10000>;
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interrupts = <b 0>;
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interrupts = <b 2>;
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interrupt-parent = <10c00>;
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num-channels = <4>;
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channel-fifo-len = <18>;
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@ -200,7 +200,7 @@
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a800 0 0 4 40000 31 1>;
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interrupt-parent = <40000>;
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interrupts = <42 0>;
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interrupts = <8 0>;
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bus-range = <0 0>;
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ranges = <02000000 0 80000000 80000000 0 20000000
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01000000 0 00000000 e2000000 0 01000000>;
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@ -250,7 +250,7 @@
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rx-clock = <1>;
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tx-clock = <1>;
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current-speed = <1c200>;
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interrupts = <64 1>;
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interrupts = <28 8>;
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interrupt-parent = <90c00>;
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};
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@ -264,7 +264,7 @@
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rx-clock = <2>;
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tx-clock = <2>;
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current-speed = <1c200>;
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interrupts = <65 1>;
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interrupts = <29 8>;
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interrupt-parent = <90c00>;
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};
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@ -278,7 +278,7 @@
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clock-setup = <ff00ffff 250000>;
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rx-clock = <15>;
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tx-clock = <16>;
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interrupts = <5d 1>;
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interrupts = <21 8>;
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interrupt-parent = <90c00>;
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phy-handle = <2452002>;
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};
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@ -293,7 +293,7 @@
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clock-setup = <ffff00ff 3700>;
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rx-clock = <17>;
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tx-clock = <18>;
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interrupts = <5e 1>;
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interrupts = <22 8>;
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interrupt-parent = <90c00>;
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phy-handle = <2452003>;
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};
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@ -36,9 +36,20 @@
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#include <asm/mpc8260.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/fs_pd.h>
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#include "cpm2_pic.h"
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/* External IRQS */
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#define CPM2_IRQ_EXT1 19
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#define CPM2_IRQ_EXT7 25
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/* Port C IRQS */
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#define CPM2_IRQ_PORTC15 48
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#define CPM2_IRQ_PORTC0 63
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static intctl_cpm2_t *cpm2_intctl;
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static struct device_node *cpm2_pic_node;
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static struct irq_host *cpm2_pic_host;
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#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
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@ -68,68 +79,55 @@ static const u_char irq_to_siubit[] = {
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24, 25, 26, 27, 28, 29, 30, 31,
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};
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static void cpm2_mask_irq(unsigned int irq_nr)
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static void cpm2_mask_irq(unsigned int virq)
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{
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int bit, word;
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volatile uint *simr;
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irq_nr -= CPM_IRQ_OFFSET;
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unsigned int irq_nr = virq_to_hw(virq);
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bit = irq_to_siubit[irq_nr];
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word = irq_to_siureg[irq_nr];
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simr = &(cpm2_intctl->ic_simrh);
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ppc_cached_irq_mask[word] &= ~(1 << bit);
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simr[word] = ppc_cached_irq_mask[word];
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out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]);
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}
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static void cpm2_unmask_irq(unsigned int irq_nr)
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static void cpm2_unmask_irq(unsigned int virq)
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{
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int bit, word;
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volatile uint *simr;
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irq_nr -= CPM_IRQ_OFFSET;
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unsigned int irq_nr = virq_to_hw(virq);
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bit = irq_to_siubit[irq_nr];
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word = irq_to_siureg[irq_nr];
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simr = &(cpm2_intctl->ic_simrh);
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ppc_cached_irq_mask[word] |= 1 << bit;
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simr[word] = ppc_cached_irq_mask[word];
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out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]);
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}
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static void cpm2_mask_and_ack(unsigned int irq_nr)
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static void cpm2_ack(unsigned int virq)
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{
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int bit, word;
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volatile uint *simr, *sipnr;
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irq_nr -= CPM_IRQ_OFFSET;
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unsigned int irq_nr = virq_to_hw(virq);
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bit = irq_to_siubit[irq_nr];
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word = irq_to_siureg[irq_nr];
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simr = &(cpm2_intctl->ic_simrh);
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sipnr = &(cpm2_intctl->ic_sipnrh);
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ppc_cached_irq_mask[word] &= ~(1 << bit);
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simr[word] = ppc_cached_irq_mask[word];
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sipnr[word] = 1 << bit;
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out_be32(&cpm2_intctl->ic_sipnrh + word, 1 << bit);
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}
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static void cpm2_end_irq(unsigned int irq_nr)
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static void cpm2_end_irq(unsigned int virq)
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{
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int bit, word;
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volatile uint *simr;
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unsigned int irq_nr = virq_to_hw(virq);
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if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))
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&& irq_desc[irq_nr].action) {
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irq_nr -= CPM_IRQ_OFFSET;
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bit = irq_to_siubit[irq_nr];
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word = irq_to_siureg[irq_nr];
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simr = &(cpm2_intctl->ic_simrh);
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ppc_cached_irq_mask[word] |= 1 << bit;
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simr[word] = ppc_cached_irq_mask[word];
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out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]);
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/*
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* Work around large numbers of spurious IRQs on PowerPC 82xx
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* systems.
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@ -138,13 +136,59 @@ static void cpm2_end_irq(unsigned int irq_nr)
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}
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}
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static int cpm2_set_irq_type(unsigned int virq, unsigned int flow_type)
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{
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unsigned int src = virq_to_hw(virq);
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struct irq_desc *desc = get_irq_desc(virq);
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unsigned int vold, vnew, edibit;
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if (flow_type == IRQ_TYPE_NONE)
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flow_type = IRQ_TYPE_LEVEL_LOW;
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if (flow_type & IRQ_TYPE_EDGE_RISING) {
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printk(KERN_ERR "CPM2 PIC: sense type 0x%x not supported\n",
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flow_type);
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return -EINVAL;
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}
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desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
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desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
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if (flow_type & IRQ_TYPE_LEVEL_LOW) {
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desc->status |= IRQ_LEVEL;
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desc->handle_irq = handle_level_irq;
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} else
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desc->handle_irq = handle_edge_irq;
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/* internal IRQ senses are LEVEL_LOW
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* EXT IRQ and Port C IRQ senses are programmable
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*/
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if (src >= CPM2_IRQ_EXT1 && src <= CPM2_IRQ_EXT7)
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edibit = (14 - (src - CPM2_IRQ_EXT1));
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else
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if (src >= CPM2_IRQ_PORTC15 && src <= CPM2_IRQ_PORTC0)
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edibit = (31 - (src - CPM2_IRQ_PORTC15));
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else
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return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL;
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vold = in_be32(&cpm2_intctl->ic_siexr);
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if ((flow_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_FALLING)
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vnew = vold | (1 << edibit);
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else
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vnew = vold & ~(1 << edibit);
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if (vold != vnew)
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out_be32(&cpm2_intctl->ic_siexr, vnew);
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return 0;
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}
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static struct irq_chip cpm2_pic = {
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.typename = " CPM2 SIU ",
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.enable = cpm2_unmask_irq,
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.disable = cpm2_mask_irq,
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.mask = cpm2_mask_irq,
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.unmask = cpm2_unmask_irq,
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.mask_ack = cpm2_mask_and_ack,
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.end = cpm2_end_irq,
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.ack = cpm2_ack,
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.eoi = cpm2_end_irq,
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.set_type = cpm2_set_irq_type,
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};
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unsigned int cpm2_get_irq(void)
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@ -154,17 +198,17 @@ unsigned int cpm2_get_irq(void)
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/* For CPM2, read the SIVEC register and shift the bits down
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* to get the irq number. */
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bits = cpm2_intctl->ic_sivec;
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bits = in_be32(&cpm2_intctl->ic_sivec);
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irq = bits >> 26;
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if (irq == 0)
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return(-1);
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return irq+CPM_IRQ_OFFSET;
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return irq_linear_revmap(cpm2_pic_host, irq);
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}
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static int cpm2_pic_host_match(struct irq_host *h, struct device_node *node)
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{
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return cpm2_pic_node == NULL || cpm2_pic_node == node;
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return cpm2_pic_node == node;
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}
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static int cpm2_pic_host_map(struct irq_host *h, unsigned int virq,
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@ -177,39 +221,21 @@ static int cpm2_pic_host_map(struct irq_host *h, unsigned int virq,
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return 0;
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}
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static void cpm2_host_unmap(struct irq_host *h, unsigned int virq)
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{
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/* Make sure irq is masked in hardware */
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cpm2_mask_irq(virq);
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/* remove chip and handler */
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set_irq_chip_and_handler(virq, NULL, NULL);
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}
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static int cpm2_pic_host_xlate(struct irq_host *h, struct device_node *ct,
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u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq, unsigned int *out_flags)
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{
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static const unsigned char map_cpm2_senses[4] = {
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IRQ_TYPE_LEVEL_LOW,
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IRQ_TYPE_LEVEL_HIGH,
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IRQ_TYPE_EDGE_FALLING,
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IRQ_TYPE_EDGE_RISING,
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};
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*out_hwirq = intspec[0];
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if (intsize > 1 && intspec[1] < 4)
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*out_flags = map_cpm2_senses[intspec[1]];
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if (intsize > 1)
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*out_flags = intspec[1];
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else
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*out_flags = IRQ_TYPE_NONE;
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return 0;
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}
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static struct irq_host_ops cpm2_pic_host_ops = {
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.match = cpm2_pic_host_match,
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.map = cpm2_pic_host_map,
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.unmap = cpm2_host_unmap,
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.xlate = cpm2_pic_host_xlate,
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};
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|
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@ -217,32 +243,34 @@ void cpm2_pic_init(struct device_node *node)
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{
|
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int i;
|
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|
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cpm2_intctl = cpm2_map(im_intctl);
|
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|
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/* Clear the CPM IRQ controller, in case it has any bits set
|
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* from the bootloader
|
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*/
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|
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/* Mask out everything */
|
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|
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cpm2_intctl->ic_simrh = 0x00000000;
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cpm2_intctl->ic_simrl = 0x00000000;
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out_be32(&cpm2_intctl->ic_simrh, 0x00000000);
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out_be32(&cpm2_intctl->ic_simrl, 0x00000000);
|
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|
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wmb();
|
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|
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/* Ack everything */
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cpm2_intctl->ic_sipnrh = 0xffffffff;
|
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cpm2_intctl->ic_sipnrl = 0xffffffff;
|
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out_be32(&cpm2_intctl->ic_sipnrh, 0xffffffff);
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out_be32(&cpm2_intctl->ic_sipnrl, 0xffffffff);
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wmb();
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|
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/* Dummy read of the vector */
|
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i = cpm2_intctl->ic_sivec;
|
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i = in_be32(&cpm2_intctl->ic_sivec);
|
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rmb();
|
||||
|
||||
/* Initialize the default interrupt mapping priorities,
|
||||
* in case the boot rom changed something on us.
|
||||
*/
|
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cpm2_intctl->ic_sicr = 0;
|
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cpm2_intctl->ic_scprrh = 0x05309770;
|
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cpm2_intctl->ic_scprrl = 0x05309770;
|
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out_be16(&cpm2_intctl->ic_sicr, 0);
|
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out_be32(&cpm2_intctl->ic_scprrh, 0x05309770);
|
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out_be32(&cpm2_intctl->ic_scprrl, 0x05309770);
|
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|
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/* create a legacy host */
|
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cpm2_pic_node = of_node_get(node);
|
||||
|
|
|
|||
|
|
@ -1,8 +1,6 @@
|
|||
#ifndef _PPC_KERNEL_CPM2_H
|
||||
#define _PPC_KERNEL_CPM2_H
|
||||
|
||||
extern intctl_cpm2_t *cpm2_intctl;
|
||||
|
||||
extern unsigned int cpm2_get_irq(void);
|
||||
|
||||
extern void cpm2_pic_init(struct device_node*);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* Since there are many different boards and no standard configuration,
|
||||
* we have a unique include file for each. Rather than change every
|
||||
* file that has to include MPC8260 configuration, they all include
|
||||
* this one and the configuration switching is done here.
|
||||
*/
|
||||
#ifdef __KERNEL__
|
||||
#ifndef __ASM_PPC_MPC8260_H__
|
||||
#define __ASM_PPC_MPC8260_H__
|
||||
|
||||
|
||||
#ifdef CONFIG_8260
|
||||
|
||||
#if defined(CONFIG_PQ2ADS) || defined (CONFIG_PQ2FADS)
|
||||
#include <platforms/82xx/pq2ads.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI_8260
|
||||
#include <platforms/82xx/m82xx_pci.h>
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_8260 */
|
||||
#endif /* !__ASM_PPC_MPC8260_H__ */
|
||||
#endif /* __KERNEL__ */
|
||||
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