ASoC: sun4i-i2s: Add support for H6 I2S
H6 I2S is very similar to that in H3, except it supports up to 16 channels. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Marcus Cooper <codekipper@gmail.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Clément Péron <peron.clem@gmail.com> Link: https://lore.kernel.org/r/20201030144648.397824-4-peron.clem@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Jernej Skrabec
Mark Brown
Родитель
c779e2de0a
Коммит
73adf87b7a
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@ -124,6 +124,21 @@
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#define SUN8I_I2S_RX_CHAN_SEL_REG 0x54
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#define SUN8I_I2S_RX_CHAN_MAP_REG 0x58
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/* Defines required for sun50i-h6 support */
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#define SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET_MASK GENMASK(21, 20)
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#define SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET(offset) ((offset) << 20)
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#define SUN50I_H6_I2S_TX_CHAN_SEL_MASK GENMASK(19, 16)
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#define SUN50I_H6_I2S_TX_CHAN_SEL(chan) ((chan - 1) << 16)
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#define SUN50I_H6_I2S_TX_CHAN_EN_MASK GENMASK(15, 0)
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#define SUN50I_H6_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1))
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#define SUN50I_H6_I2S_TX_CHAN_MAP0_REG 0x44
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#define SUN50I_H6_I2S_TX_CHAN_MAP1_REG 0x48
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#define SUN50I_H6_I2S_RX_CHAN_SEL_REG 0x64
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#define SUN50I_H6_I2S_RX_CHAN_MAP0_REG 0x68
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#define SUN50I_H6_I2S_RX_CHAN_MAP1_REG 0x6C
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struct sun4i_i2s;
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/**
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@ -476,6 +491,60 @@ static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
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return 0;
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}
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static int sun50i_h6_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
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unsigned int channels, unsigned int slots,
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unsigned int slot_width)
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{
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unsigned int lrck_period;
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/* Map the channels for playback and capture */
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regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP0_REG, 0xFEDCBA98);
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regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP1_REG, 0x76543210);
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regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP0_REG, 0xFEDCBA98);
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regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP1_REG, 0x76543210);
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/* Configure the channels */
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regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
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SUN50I_H6_I2S_TX_CHAN_SEL_MASK,
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SUN50I_H6_I2S_TX_CHAN_SEL(channels));
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regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_SEL_REG,
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SUN50I_H6_I2S_TX_CHAN_SEL_MASK,
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SUN50I_H6_I2S_TX_CHAN_SEL(channels));
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regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
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SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK,
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SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels));
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regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
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SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK,
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SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels));
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switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_DSP_A:
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case SND_SOC_DAIFMT_DSP_B:
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lrck_period = slot_width * slots;
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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case SND_SOC_DAIFMT_RIGHT_J:
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case SND_SOC_DAIFMT_I2S:
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lrck_period = slot_width;
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break;
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default:
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return -EINVAL;
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}
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regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
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SUN8I_I2S_FMT0_LRCK_PERIOD_MASK,
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SUN8I_I2S_FMT0_LRCK_PERIOD(lrck_period));
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regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
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SUN50I_H6_I2S_TX_CHAN_EN_MASK,
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SUN50I_H6_I2S_TX_CHAN_EN(channels));
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return 0;
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}
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static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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@ -703,6 +772,108 @@ static int sun8i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s,
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return 0;
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}
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static int sun50i_h6_i2s_set_soc_fmt(const struct sun4i_i2s *i2s,
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unsigned int fmt)
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{
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u32 mode, val;
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u8 offset;
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/*
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* DAI clock polarity
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*
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* The setup for LRCK contradicts the datasheet, but under a
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* scope it's clear that the LRCK polarity is reversed
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* compared to the expected polarity on the bus.
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*/
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_IB_IF:
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/* Invert both clocks */
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val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED;
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break;
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case SND_SOC_DAIFMT_IB_NF:
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/* Invert bit clock */
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val = SUN8I_I2S_FMT0_BCLK_POLARITY_INVERTED |
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SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
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break;
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case SND_SOC_DAIFMT_NB_IF:
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/* Invert frame clock */
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val = 0;
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break;
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case SND_SOC_DAIFMT_NB_NF:
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val = SUN8I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
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break;
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default:
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return -EINVAL;
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}
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regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
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SUN8I_I2S_FMT0_LRCLK_POLARITY_MASK |
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SUN8I_I2S_FMT0_BCLK_POLARITY_MASK,
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val);
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/* DAI Mode */
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_DSP_A:
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mode = SUN8I_I2S_CTRL_MODE_PCM;
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offset = 1;
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break;
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case SND_SOC_DAIFMT_DSP_B:
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mode = SUN8I_I2S_CTRL_MODE_PCM;
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offset = 0;
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break;
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case SND_SOC_DAIFMT_I2S:
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mode = SUN8I_I2S_CTRL_MODE_LEFT;
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offset = 1;
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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mode = SUN8I_I2S_CTRL_MODE_LEFT;
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offset = 0;
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break;
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case SND_SOC_DAIFMT_RIGHT_J:
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mode = SUN8I_I2S_CTRL_MODE_RIGHT;
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offset = 0;
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break;
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default:
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return -EINVAL;
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}
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regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
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SUN8I_I2S_CTRL_MODE_MASK, mode);
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regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
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SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET_MASK,
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SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET(offset));
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regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_SEL_REG,
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SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET_MASK,
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SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET(offset));
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/* DAI clock master masks */
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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/* BCLK and LRCLK master */
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val = SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT;
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break;
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case SND_SOC_DAIFMT_CBM_CFM:
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/* BCLK and LRCLK slave */
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val = 0;
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break;
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default:
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return -EINVAL;
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}
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regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
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SUN8I_I2S_CTRL_BCLK_OUT | SUN8I_I2S_CTRL_LRCK_OUT,
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val);
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return 0;
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}
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static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
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{
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struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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@ -983,6 +1154,22 @@ static const struct reg_default sun8i_i2s_reg_defaults[] = {
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{ SUN8I_I2S_RX_CHAN_MAP_REG, 0x00000000 },
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};
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static const struct reg_default sun50i_h6_i2s_reg_defaults[] = {
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{ SUN4I_I2S_CTRL_REG, 0x00060000 },
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{ SUN4I_I2S_FMT0_REG, 0x00000033 },
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{ SUN4I_I2S_FMT1_REG, 0x00000030 },
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{ SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 },
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{ SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },
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{ SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
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{ SUN8I_I2S_CHAN_CFG_REG, 0x00000000 },
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{ SUN8I_I2S_TX_CHAN_SEL_REG, 0x00000000 },
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{ SUN50I_H6_I2S_TX_CHAN_MAP0_REG, 0x00000000 },
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{ SUN50I_H6_I2S_TX_CHAN_MAP1_REG, 0x00000000 },
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{ SUN50I_H6_I2S_RX_CHAN_SEL_REG, 0x00000000 },
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{ SUN50I_H6_I2S_RX_CHAN_MAP0_REG, 0x00000000 },
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{ SUN50I_H6_I2S_RX_CHAN_MAP1_REG, 0x00000000 },
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};
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static const struct regmap_config sun4i_i2s_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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@ -1010,6 +1197,19 @@ static const struct regmap_config sun8i_i2s_regmap_config = {
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.volatile_reg = sun8i_i2s_volatile_reg,
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};
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static const struct regmap_config sun50i_h6_i2s_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = SUN50I_H6_I2S_RX_CHAN_MAP1_REG,
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.cache_type = REGCACHE_FLAT,
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.reg_defaults = sun50i_h6_i2s_reg_defaults,
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.num_reg_defaults = ARRAY_SIZE(sun50i_h6_i2s_reg_defaults),
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.writeable_reg = sun4i_i2s_wr_reg,
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.readable_reg = sun8i_i2s_rd_reg,
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.volatile_reg = sun8i_i2s_volatile_reg,
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};
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static int sun4i_i2s_runtime_resume(struct device *dev)
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{
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struct sun4i_i2s *i2s = dev_get_drvdata(dev);
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@ -1168,6 +1368,24 @@ static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = {
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.set_fmt = sun4i_i2s_set_soc_fmt,
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};
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static const struct sun4i_i2s_quirks sun50i_h6_i2s_quirks = {
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.has_reset = true,
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.reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
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.sun4i_i2s_regmap = &sun50i_h6_i2s_regmap_config,
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.field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8),
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.field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2),
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.field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6),
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.bclk_dividers = sun8i_i2s_clk_div,
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.num_bclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div),
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.mclk_dividers = sun8i_i2s_clk_div,
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.num_mclk_dividers = ARRAY_SIZE(sun8i_i2s_clk_div),
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.get_bclk_parent_rate = sun8i_i2s_get_bclk_parent_rate,
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.get_sr = sun8i_i2s_get_sr_wss,
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.get_wss = sun8i_i2s_get_sr_wss,
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.set_chan_cfg = sun50i_h6_i2s_set_chan_cfg,
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.set_fmt = sun50i_h6_i2s_set_soc_fmt,
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};
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static int sun4i_i2s_init_regmap_fields(struct device *dev,
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struct sun4i_i2s *i2s)
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{
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@ -1337,6 +1555,10 @@ static const struct of_device_id sun4i_i2s_match[] = {
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.compatible = "allwinner,sun50i-a64-codec-i2s",
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.data = &sun50i_a64_codec_i2s_quirks,
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},
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{
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.compatible = "allwinner,sun50i-h6-i2s",
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.data = &sun50i_h6_i2s_quirks,
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},
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{}
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};
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MODULE_DEVICE_TABLE(of, sun4i_i2s_match);
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