iommu/arm-smmu-v3: Add second level of context descriptor table
The SMMU can support up to 20 bits of SSID. Add a second level of page tables to accommodate this. Devices that support more than 1024 SSIDs now have a table of 1024 L1 entries (8kB), pointing to tables of 1024 context descriptors (64kB), allocated on demand. Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
Jean-Philippe Brucker
Will Deacon
Родитель
492ddc79e0
Коммит
73af06f589
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@ -223,6 +223,7 @@
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#define STRTAB_STE_0_S1FMT GENMASK_ULL(5, 4)
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#define STRTAB_STE_0_S1FMT_LINEAR 0
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#define STRTAB_STE_0_S1FMT_64K_L2 2
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#define STRTAB_STE_0_S1CTXPTR_MASK GENMASK_ULL(51, 6)
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#define STRTAB_STE_0_S1CDMAX GENMASK_ULL(63, 59)
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@ -269,7 +270,20 @@
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#define STRTAB_STE_3_S2TTB_MASK GENMASK_ULL(51, 4)
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/* Context descriptor (stage-1 only) */
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/*
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* Context descriptors.
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*
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* Linear: when less than 1024 SSIDs are supported
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* 2lvl: at most 1024 L1 entries,
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* 1024 lazy entries per table.
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*/
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#define CTXDESC_SPLIT 10
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#define CTXDESC_L2_ENTRIES (1 << CTXDESC_SPLIT)
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#define CTXDESC_L1_DESC_DWORDS 1
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#define CTXDESC_L1_DESC_V (1UL << 0)
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#define CTXDESC_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 12)
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#define CTXDESC_CD_DWORDS 8
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#define CTXDESC_CD_0_TCR_T0SZ GENMASK_ULL(5, 0)
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#define CTXDESC_CD_0_TCR_TG0 GENMASK_ULL(7, 6)
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@ -558,9 +572,15 @@ struct arm_smmu_ctx_desc {
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u64 mair;
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};
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struct arm_smmu_l1_ctx_desc {
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__le64 *l2ptr;
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dma_addr_t l2ptr_dma;
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};
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struct arm_smmu_ctx_desc_cfg {
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__le64 *cdtab;
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dma_addr_t cdtab_dma;
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struct arm_smmu_l1_ctx_desc *l1_desc;
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unsigned int num_l1_ents;
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};
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@ -1490,6 +1510,57 @@ static void arm_smmu_sync_cd(struct arm_smmu_domain *smmu_domain,
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arm_smmu_cmdq_issue_sync(smmu);
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}
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static int arm_smmu_alloc_cd_leaf_table(struct arm_smmu_device *smmu,
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struct arm_smmu_l1_ctx_desc *l1_desc)
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{
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size_t size = CTXDESC_L2_ENTRIES * (CTXDESC_CD_DWORDS << 3);
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l1_desc->l2ptr = dmam_alloc_coherent(smmu->dev, size,
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&l1_desc->l2ptr_dma, GFP_KERNEL);
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if (!l1_desc->l2ptr) {
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dev_warn(smmu->dev,
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"failed to allocate context descriptor table\n");
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return -ENOMEM;
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}
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return 0;
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}
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static void arm_smmu_write_cd_l1_desc(__le64 *dst,
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struct arm_smmu_l1_ctx_desc *l1_desc)
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{
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u64 val = (l1_desc->l2ptr_dma & CTXDESC_L1_DESC_L2PTR_MASK) |
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CTXDESC_L1_DESC_V;
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WRITE_ONCE(*dst, cpu_to_le64(val));
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}
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static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_domain *smmu_domain,
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u32 ssid)
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{
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__le64 *l1ptr;
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unsigned int idx;
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struct arm_smmu_l1_ctx_desc *l1_desc;
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struct arm_smmu_device *smmu = smmu_domain->smmu;
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struct arm_smmu_ctx_desc_cfg *cdcfg = &smmu_domain->s1_cfg.cdcfg;
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if (smmu_domain->s1_cfg.s1fmt == STRTAB_STE_0_S1FMT_LINEAR)
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return cdcfg->cdtab + ssid * CTXDESC_CD_DWORDS;
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idx = ssid >> CTXDESC_SPLIT;
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l1_desc = &cdcfg->l1_desc[idx];
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if (!l1_desc->l2ptr) {
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if (arm_smmu_alloc_cd_leaf_table(smmu, l1_desc))
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return NULL;
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l1ptr = cdcfg->cdtab + idx * CTXDESC_L1_DESC_DWORDS;
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arm_smmu_write_cd_l1_desc(l1ptr, l1_desc);
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/* An invalid L1CD can be cached */
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arm_smmu_sync_cd(smmu_domain, ssid, false);
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}
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idx = ssid & (CTXDESC_L2_ENTRIES - 1);
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return l1_desc->l2ptr + idx * CTXDESC_CD_DWORDS;
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}
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static int arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain,
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int ssid, struct arm_smmu_ctx_desc *cd)
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{
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@ -1504,9 +1575,15 @@ static int arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain,
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*/
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u64 val;
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bool cd_live;
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__le64 *cdptr;
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struct arm_smmu_device *smmu = smmu_domain->smmu;
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__le64 *cdptr = smmu_domain->s1_cfg.cdcfg.cdtab + ssid *
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CTXDESC_CD_DWORDS;
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if (WARN_ON(ssid >= (1 << smmu_domain->s1_cfg.s1cdmax)))
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return -E2BIG;
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cdptr = arm_smmu_get_cd_ptr(smmu_domain, ssid);
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if (!cdptr)
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return -ENOMEM;
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val = le64_to_cpu(cdptr[0]);
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cd_live = !!(val & CTXDESC_CD_0_V);
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@ -1562,29 +1639,78 @@ static int arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain,
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static int arm_smmu_alloc_cd_tables(struct arm_smmu_domain *smmu_domain)
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{
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int ret;
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size_t l1size;
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size_t max_contexts;
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struct arm_smmu_device *smmu = smmu_domain->smmu;
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struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg;
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struct arm_smmu_ctx_desc_cfg *cdcfg = &cfg->cdcfg;
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cfg->s1fmt = STRTAB_STE_0_S1FMT_LINEAR;
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max_contexts = 1 << cfg->s1cdmax;
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if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB) ||
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max_contexts <= CTXDESC_L2_ENTRIES) {
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cfg->s1fmt = STRTAB_STE_0_S1FMT_LINEAR;
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cdcfg->num_l1_ents = max_contexts;
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l1size = max_contexts * (CTXDESC_CD_DWORDS << 3);
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} else {
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cfg->s1fmt = STRTAB_STE_0_S1FMT_64K_L2;
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cdcfg->num_l1_ents = DIV_ROUND_UP(max_contexts,
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CTXDESC_L2_ENTRIES);
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cdcfg->l1_desc = devm_kcalloc(smmu->dev, cdcfg->num_l1_ents,
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sizeof(*cdcfg->l1_desc),
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GFP_KERNEL);
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if (!cdcfg->l1_desc)
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return -ENOMEM;
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l1size = cdcfg->num_l1_ents * (CTXDESC_L1_DESC_DWORDS << 3);
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}
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cdcfg->num_l1_ents = 1UL << cfg->s1cdmax;
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l1size = cdcfg->num_l1_ents * (CTXDESC_CD_DWORDS << 3);
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cdcfg->cdtab = dmam_alloc_coherent(smmu->dev, l1size, &cdcfg->cdtab_dma,
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GFP_KERNEL);
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if (!cdcfg->cdtab) {
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dev_warn(smmu->dev, "failed to allocate context descriptor\n");
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return -ENOMEM;
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ret = -ENOMEM;
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goto err_free_l1;
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}
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return 0;
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err_free_l1:
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if (cdcfg->l1_desc) {
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devm_kfree(smmu->dev, cdcfg->l1_desc);
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cdcfg->l1_desc = NULL;
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}
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return ret;
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}
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static void arm_smmu_free_cd_tables(struct arm_smmu_domain *smmu_domain)
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{
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int i;
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size_t size, l1size;
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struct arm_smmu_device *smmu = smmu_domain->smmu;
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struct arm_smmu_ctx_desc_cfg *cdcfg = &smmu_domain->s1_cfg.cdcfg;
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size_t l1size = cdcfg->num_l1_ents * (CTXDESC_CD_DWORDS << 3);
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if (cdcfg->l1_desc) {
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size = CTXDESC_L2_ENTRIES * (CTXDESC_CD_DWORDS << 3);
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for (i = 0; i < cdcfg->num_l1_ents; i++) {
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if (!cdcfg->l1_desc[i].l2ptr)
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continue;
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dmam_free_coherent(smmu->dev, size,
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cdcfg->l1_desc[i].l2ptr,
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cdcfg->l1_desc[i].l2ptr_dma);
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}
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devm_kfree(smmu->dev, cdcfg->l1_desc);
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cdcfg->l1_desc = NULL;
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l1size = cdcfg->num_l1_ents * (CTXDESC_L1_DESC_DWORDS << 3);
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} else {
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l1size = cdcfg->num_l1_ents * (CTXDESC_CD_DWORDS << 3);
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}
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dmam_free_coherent(smmu->dev, l1size, cdcfg->cdtab, cdcfg->cdtab_dma);
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cdcfg->cdtab_dma = 0;
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