iommu/exynos: Add support for v5 SYSMMU
This patch adds support for v5 of SYSMMU controller, found in Samsung Exynos 5433 SoCs. The main difference of v5 is support for 36-bit physical address space and some changes in register layout and core clocks hanging. This patch also adds support for ARM64 architecture, which is used by Exynos 5433 SoCs. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
This commit is contained in:
Marek Szyprowski
Joerg Roedel
Родитель
e6802707fb
Коммит
740a01eee9
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@ -35,9 +35,10 @@ Required properties:
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- interrupts: An interrupt specifier for interrupt signal of System MMU,
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according to the format defined by a particular interrupt
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controller.
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- clock-names: Should be "sysmmu" if the System MMU is needed to gate its clock.
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- clock-names: Should be "sysmmu" or a pair of "aclk" and "pclk" to gate
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SYSMMU core clocks.
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Optional "master" if the clock to the System MMU is gated by
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another gate clock other than "sysmmu" (usually main gate clock
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another gate clock other core (usually main gate clock
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of peripheral device this SYSMMU belongs to).
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- clocks: Phandles for respective clocks described by clock-names.
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- power-domains: Required if the System MMU is needed to gate its power.
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@ -243,7 +243,7 @@ config TEGRA_IOMMU_SMMU
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config EXYNOS_IOMMU
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bool "Exynos IOMMU Support"
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depends on ARCH_EXYNOS && ARM && MMU
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depends on ARCH_EXYNOS && MMU
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select IOMMU_API
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select ARM_DMA_USE_IOMMU
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help
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@ -1,6 +1,5 @@
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/* linux/drivers/iommu/exynos_iommu.c
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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/*
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* Copyright (c) 2011,2016 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify
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@ -55,17 +54,25 @@ typedef u32 sysmmu_pte_t;
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#define lv2ent_small(pent) ((*(pent) & 2) == 2)
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#define lv2ent_large(pent) ((*(pent) & 3) == 1)
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static u32 sysmmu_page_offset(sysmmu_iova_t iova, u32 size)
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{
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return iova & (size - 1);
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}
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/*
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* v1.x - v3.x SYSMMU supports 32bit physical and 32bit virtual address spaces
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* v5.0 introduced support for 36bit physical address space by shifting
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* all page entry values by 4 bits.
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* All SYSMMU controllers in the system support the address spaces of the same
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* size, so PG_ENT_SHIFT can be initialized on first SYSMMU probe to proper
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* value (0 or 4).
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*/
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static short PG_ENT_SHIFT = -1;
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#define SYSMMU_PG_ENT_SHIFT 0
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#define SYSMMU_V5_PG_ENT_SHIFT 4
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#define section_phys(sent) (*(sent) & SECT_MASK)
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#define section_offs(iova) sysmmu_page_offset((iova), SECT_SIZE)
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#define lpage_phys(pent) (*(pent) & LPAGE_MASK)
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#define lpage_offs(iova) sysmmu_page_offset((iova), LPAGE_SIZE)
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#define spage_phys(pent) (*(pent) & SPAGE_MASK)
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#define spage_offs(iova) sysmmu_page_offset((iova), SPAGE_SIZE)
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#define sect_to_phys(ent) (((phys_addr_t) ent) << PG_ENT_SHIFT)
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#define section_phys(sent) (sect_to_phys(*(sent)) & SECT_MASK)
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#define section_offs(iova) (iova & (SECT_SIZE - 1))
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#define lpage_phys(pent) (sect_to_phys(*(pent)) & LPAGE_MASK)
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#define lpage_offs(iova) (iova & (LPAGE_SIZE - 1))
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#define spage_phys(pent) (sect_to_phys(*(pent)) & SPAGE_MASK)
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#define spage_offs(iova) (iova & (SPAGE_SIZE - 1))
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#define NUM_LV1ENTRIES 4096
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#define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE)
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@ -84,13 +91,12 @@ static u32 lv2ent_offset(sysmmu_iova_t iova)
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#define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t))
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#define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE)
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#define lv2table_base(sent) (sect_to_phys(*(sent) & 0xFFFFFFC0))
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#define lv2table_base(sent) (*(sent) & 0xFFFFFC00)
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#define mk_lv1ent_sect(pa) ((pa) | 2)
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#define mk_lv1ent_page(pa) ((pa) | 1)
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#define mk_lv2ent_lpage(pa) ((pa) | 1)
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#define mk_lv2ent_spage(pa) ((pa) | 2)
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#define mk_lv1ent_sect(pa) ((pa >> PG_ENT_SHIFT) | 2)
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#define mk_lv1ent_page(pa) ((pa >> PG_ENT_SHIFT) | 1)
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#define mk_lv2ent_lpage(pa) ((pa >> PG_ENT_SHIFT) | 1)
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#define mk_lv2ent_spage(pa) ((pa >> PG_ENT_SHIFT) | 2)
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#define CTRL_ENABLE 0x5
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#define CTRL_BLOCK 0x7
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@ -98,14 +104,23 @@ static u32 lv2ent_offset(sysmmu_iova_t iova)
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#define CFG_LRU 0x1
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#define CFG_QOS(n) ((n & 0xF) << 7)
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#define CFG_MASK 0x0150FFFF /* Selecting bit 0-15, 20, 22 and 24 */
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#define CFG_ACGEN (1 << 24) /* System MMU 3.3 only */
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#define CFG_SYSSEL (1 << 22) /* System MMU 3.2 only */
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#define CFG_FLPDCACHE (1 << 20) /* System MMU 3.2+ only */
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/* common registers */
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#define REG_MMU_CTRL 0x000
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#define REG_MMU_CFG 0x004
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#define REG_MMU_STATUS 0x008
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#define REG_MMU_VERSION 0x034
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#define MMU_MAJ_VER(val) ((val) >> 7)
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#define MMU_MIN_VER(val) ((val) & 0x7F)
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#define MMU_RAW_VER(reg) (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */
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#define MAKE_MMU_VER(maj, min) ((((maj) & 0xF) << 7) | ((min) & 0x7F))
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/* v1.x - v3.x registers */
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#define REG_MMU_FLUSH 0x00C
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#define REG_MMU_FLUSH_ENTRY 0x010
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#define REG_PT_BASE_ADDR 0x014
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@ -117,18 +132,14 @@ static u32 lv2ent_offset(sysmmu_iova_t iova)
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#define REG_AR_FAULT_ADDR 0x02C
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#define REG_DEFAULT_SLAVE_ADDR 0x030
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#define REG_MMU_VERSION 0x034
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#define MMU_MAJ_VER(val) ((val) >> 7)
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#define MMU_MIN_VER(val) ((val) & 0x7F)
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#define MMU_RAW_VER(reg) (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */
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#define MAKE_MMU_VER(maj, min) ((((maj) & 0xF) << 7) | ((min) & 0x7F))
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#define REG_PB0_SADDR 0x04C
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#define REG_PB0_EADDR 0x050
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#define REG_PB1_SADDR 0x054
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#define REG_PB1_EADDR 0x058
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/* v5.x registers */
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#define REG_V5_PT_BASE_PFN 0x00C
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#define REG_V5_MMU_FLUSH_ALL 0x010
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#define REG_V5_MMU_FLUSH_ENTRY 0x014
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#define REG_V5_INT_STATUS 0x060
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#define REG_V5_INT_CLEAR 0x064
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#define REG_V5_FAULT_AR_VA 0x070
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#define REG_V5_FAULT_AW_VA 0x080
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#define has_sysmmu(dev) (dev->archdata.iommu != NULL)
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@ -169,6 +180,19 @@ static const struct sysmmu_fault_info sysmmu_faults[] = {
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{ 7, REG_AW_FAULT_ADDR, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE },
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};
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static const struct sysmmu_fault_info sysmmu_v5_faults[] = {
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{ 0, REG_V5_FAULT_AR_VA, "AR PTW", IOMMU_FAULT_READ },
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{ 1, REG_V5_FAULT_AR_VA, "AR PAGE", IOMMU_FAULT_READ },
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{ 2, REG_V5_FAULT_AR_VA, "AR MULTI-HIT", IOMMU_FAULT_READ },
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{ 3, REG_V5_FAULT_AR_VA, "AR ACCESS PROTECTION", IOMMU_FAULT_READ },
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{ 4, REG_V5_FAULT_AR_VA, "AR SECURITY PROTECTION", IOMMU_FAULT_READ },
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{ 16, REG_V5_FAULT_AW_VA, "AW PTW", IOMMU_FAULT_WRITE },
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{ 17, REG_V5_FAULT_AW_VA, "AW PAGE", IOMMU_FAULT_WRITE },
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{ 18, REG_V5_FAULT_AW_VA, "AW MULTI-HIT", IOMMU_FAULT_WRITE },
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{ 19, REG_V5_FAULT_AW_VA, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE },
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{ 20, REG_V5_FAULT_AW_VA, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE },
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};
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/*
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* This structure is attached to dev.archdata.iommu of the master device
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* on device add, contains a list of SYSMMU controllers defined by device tree,
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@ -205,6 +229,8 @@ struct sysmmu_drvdata {
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struct device *master; /* master device (owner) */
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void __iomem *sfrbase; /* our registers */
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struct clk *clk; /* SYSMMU's clock */
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struct clk *aclk; /* SYSMMU's aclk clock */
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struct clk *pclk; /* SYSMMU's pclk clock */
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struct clk *clk_master; /* master's device clock */
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int activations; /* number of calls to sysmmu_enable */
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spinlock_t lock; /* lock for modyfying state */
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@ -262,7 +288,10 @@ static bool sysmmu_block(struct sysmmu_drvdata *data)
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static void __sysmmu_tlb_invalidate(struct sysmmu_drvdata *data)
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{
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__raw_writel(0x1, data->sfrbase + REG_MMU_FLUSH);
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if (MMU_MAJ_VER(data->version) < 5)
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__raw_writel(0x1, data->sfrbase + REG_MMU_FLUSH);
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else
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__raw_writel(0x1, data->sfrbase + REG_V5_MMU_FLUSH_ALL);
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}
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static void __sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data,
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@ -271,15 +300,23 @@ static void __sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data,
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unsigned int i;
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for (i = 0; i < num_inv; i++) {
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__raw_writel((iova & SPAGE_MASK) | 1,
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data->sfrbase + REG_MMU_FLUSH_ENTRY);
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if (MMU_MAJ_VER(data->version) < 5)
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__raw_writel((iova & SPAGE_MASK) | 1,
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data->sfrbase + REG_MMU_FLUSH_ENTRY);
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else
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__raw_writel((iova & SPAGE_MASK) | 1,
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data->sfrbase + REG_V5_MMU_FLUSH_ENTRY);
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iova += SPAGE_SIZE;
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}
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}
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static void __sysmmu_set_ptbase(struct sysmmu_drvdata *data, phys_addr_t pgd)
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{
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__raw_writel(pgd, data->sfrbase + REG_PT_BASE_ADDR);
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if (MMU_MAJ_VER(data->version) < 5)
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__raw_writel(pgd, data->sfrbase + REG_PT_BASE_ADDR);
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else
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__raw_writel(pgd >> PAGE_SHIFT,
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data->sfrbase + REG_V5_PT_BASE_PFN);
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__sysmmu_tlb_invalidate(data);
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}
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@ -290,6 +327,8 @@ static void __sysmmu_get_version(struct sysmmu_drvdata *data)
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clk_enable(data->clk_master);
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clk_enable(data->clk);
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clk_enable(data->pclk);
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clk_enable(data->aclk);
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ver = __raw_readl(data->sfrbase + REG_MMU_VERSION);
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@ -302,6 +341,8 @@ static void __sysmmu_get_version(struct sysmmu_drvdata *data)
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dev_dbg(data->sysmmu, "hardware version: %d.%d\n",
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MMU_MAJ_VER(data->version), MMU_MIN_VER(data->version));
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clk_disable(data->aclk);
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clk_disable(data->pclk);
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clk_disable(data->clk);
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clk_disable(data->clk_master);
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}
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@ -326,19 +367,31 @@ static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
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{
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/* SYSMMU is in blocked state when interrupt occurred. */
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struct sysmmu_drvdata *data = dev_id;
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const struct sysmmu_fault_info *finfo = sysmmu_faults;
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int i, n = ARRAY_SIZE(sysmmu_faults);
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unsigned int itype;
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const struct sysmmu_fault_info *finfo;
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unsigned int i, n, itype;
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sysmmu_iova_t fault_addr = -1;
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unsigned short reg_status, reg_clear;
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int ret = -ENOSYS;
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WARN_ON(!is_sysmmu_active(data));
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if (MMU_MAJ_VER(data->version) < 5) {
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reg_status = REG_INT_STATUS;
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reg_clear = REG_INT_CLEAR;
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finfo = sysmmu_faults;
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n = ARRAY_SIZE(sysmmu_faults);
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} else {
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reg_status = REG_V5_INT_STATUS;
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reg_clear = REG_V5_INT_CLEAR;
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finfo = sysmmu_v5_faults;
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n = ARRAY_SIZE(sysmmu_v5_faults);
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}
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spin_lock(&data->lock);
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clk_enable(data->clk_master);
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itype = __ffs(__raw_readl(data->sfrbase + REG_INT_STATUS));
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itype = __ffs(__raw_readl(data->sfrbase + reg_status));
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for (i = 0; i < n; i++, finfo++)
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if (finfo->bit == itype)
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break;
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@ -355,7 +408,7 @@ static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
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/* fault is not recovered by fault handler */
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BUG_ON(ret != 0);
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__raw_writel(1 << itype, data->sfrbase + REG_INT_CLEAR);
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__raw_writel(1 << itype, data->sfrbase + reg_clear);
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sysmmu_unblock(data);
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@ -373,6 +426,8 @@ static void __sysmmu_disable_nocount(struct sysmmu_drvdata *data)
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__raw_writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL);
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__raw_writel(0, data->sfrbase + REG_MMU_CFG);
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clk_disable(data->aclk);
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clk_disable(data->pclk);
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clk_disable(data->clk);
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clk_disable(data->clk_master);
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}
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@ -421,6 +476,8 @@ static void __sysmmu_enable_nocount(struct sysmmu_drvdata *data)
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{
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clk_enable(data->clk_master);
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clk_enable(data->clk);
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clk_enable(data->pclk);
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clk_enable(data->aclk);
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__raw_writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
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@ -544,22 +601,47 @@ static int __init exynos_sysmmu_probe(struct platform_device *pdev)
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}
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data->clk = devm_clk_get(dev, "sysmmu");
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if (IS_ERR(data->clk)) {
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dev_err(dev, "Failed to get clock!\n");
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return PTR_ERR(data->clk);
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} else {
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if (!IS_ERR(data->clk)) {
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ret = clk_prepare(data->clk);
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if (ret) {
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dev_err(dev, "Failed to prepare clk\n");
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return ret;
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}
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} else {
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data->clk = NULL;
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}
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data->aclk = devm_clk_get(dev, "aclk");
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if (!IS_ERR(data->aclk)) {
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ret = clk_prepare(data->aclk);
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if (ret) {
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dev_err(dev, "Failed to prepare aclk\n");
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return ret;
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}
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} else {
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data->aclk = NULL;
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}
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data->pclk = devm_clk_get(dev, "pclk");
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if (!IS_ERR(data->pclk)) {
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ret = clk_prepare(data->pclk);
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if (ret) {
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dev_err(dev, "Failed to prepare pclk\n");
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return ret;
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}
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} else {
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data->pclk = NULL;
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}
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if (!data->clk && (!data->aclk || !data->pclk)) {
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dev_err(dev, "Failed to get device clock(s)!\n");
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return -ENOSYS;
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}
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data->clk_master = devm_clk_get(dev, "master");
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if (!IS_ERR(data->clk_master)) {
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ret = clk_prepare(data->clk_master);
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if (ret) {
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clk_unprepare(data->clk);
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dev_err(dev, "Failed to prepare master's clk\n");
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return ret;
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}
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@ -573,6 +655,13 @@ static int __init exynos_sysmmu_probe(struct platform_device *pdev)
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platform_set_drvdata(pdev, data);
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__sysmmu_get_version(data);
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if (PG_ENT_SHIFT < 0) {
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if (MMU_MAJ_VER(data->version) < 5)
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PG_ENT_SHIFT = SYSMMU_PG_ENT_SHIFT;
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else
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PG_ENT_SHIFT = SYSMMU_V5_PG_ENT_SHIFT;
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}
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pm_runtime_enable(dev);
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return 0;
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@ -637,6 +726,8 @@ static struct iommu_domain *exynos_iommu_domain_alloc(unsigned type)
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dma_addr_t handle;
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int i;
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/* Check if correct PTE offsets are initialized */
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BUG_ON(PG_ENT_SHIFT < 0 || !dma_dev);
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domain = kzalloc(sizeof(*domain), GFP_KERNEL);
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if (!domain)
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@ -816,7 +907,7 @@ static sysmmu_pte_t *alloc_lv2entry(struct exynos_iommu_domain *domain,
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bool need_flush_flpd_cache = lv1ent_zero(sent);
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pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
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BUG_ON((unsigned int)pent & (LV2TABLE_SIZE - 1));
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BUG_ON((phys_addr_t)pent & (LV2TABLE_SIZE - 1));
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||||
if (!pent)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
|
|
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|||
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