drm/radeon/kms/evergreen: add soft reset function
Works pretty similarly to r6xx/r7xx. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher
Dave Airlie
Родитель
0fcdb61e78
Коммит
747943ea18
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@ -511,10 +511,79 @@ bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
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return false;
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}
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static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
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{
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struct evergreen_mc_save save;
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u32 srbm_reset = 0;
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u32 grbm_reset = 0;
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dev_info(rdev->dev, "GPU softreset \n");
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dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
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RREG32(GRBM_STATUS));
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dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
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RREG32(GRBM_STATUS_SE0));
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dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
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RREG32(GRBM_STATUS_SE1));
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dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
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RREG32(SRBM_STATUS));
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evergreen_mc_stop(rdev, &save);
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if (evergreen_mc_wait_for_idle(rdev)) {
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dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
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}
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/* Disable CP parsing/prefetching */
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WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
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/* reset all the gfx blocks */
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grbm_reset = (SOFT_RESET_CP |
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SOFT_RESET_CB |
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SOFT_RESET_DB |
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SOFT_RESET_PA |
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SOFT_RESET_SC |
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SOFT_RESET_SPI |
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SOFT_RESET_SH |
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SOFT_RESET_SX |
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SOFT_RESET_TC |
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SOFT_RESET_TA |
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SOFT_RESET_VC |
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SOFT_RESET_VGT);
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dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
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WREG32(GRBM_SOFT_RESET, grbm_reset);
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(void)RREG32(GRBM_SOFT_RESET);
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udelay(50);
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WREG32(GRBM_SOFT_RESET, 0);
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(void)RREG32(GRBM_SOFT_RESET);
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/* reset all the system blocks */
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srbm_reset = SRBM_SOFT_RESET_ALL_MASK;
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dev_info(rdev->dev, " SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
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WREG32(SRBM_SOFT_RESET, srbm_reset);
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(void)RREG32(SRBM_SOFT_RESET);
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udelay(50);
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WREG32(SRBM_SOFT_RESET, 0);
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(void)RREG32(SRBM_SOFT_RESET);
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/* Wait a little for things to settle down */
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udelay(50);
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dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
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RREG32(GRBM_STATUS));
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dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
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RREG32(GRBM_STATUS_SE0));
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dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
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RREG32(GRBM_STATUS_SE1));
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dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
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RREG32(SRBM_STATUS));
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/* After reset we need to reinit the asic as GPU often endup in an
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* incoherent state.
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*/
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atom_asic_init(rdev->mode_info.atom_context);
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evergreen_mc_resume(rdev, &save);
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return 0;
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}
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int evergreen_asic_reset(struct radeon_device *rdev)
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{
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/* FIXME: implement for evergreen */
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return 0;
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return evergreen_gpu_soft_reset(rdev);
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}
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static int evergreen_startup(struct radeon_device *rdev)
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@ -78,10 +78,53 @@
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#define GRBM_CNTL 0x8000
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#define GRBM_READ_TIMEOUT(x) ((x) << 0)
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#define GRBM_SOFT_RESET 0x8020
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#define SOFT_RESET_CP (1<<0)
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#define SOFT_RESET_CP (1 << 0)
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#define SOFT_RESET_CB (1 << 1)
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#define SOFT_RESET_DB (1 << 3)
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#define SOFT_RESET_PA (1 << 5)
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#define SOFT_RESET_SC (1 << 6)
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#define SOFT_RESET_SPI (1 << 8)
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#define SOFT_RESET_SH (1 << 9)
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#define SOFT_RESET_SX (1 << 10)
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#define SOFT_RESET_TC (1 << 11)
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#define SOFT_RESET_TA (1 << 12)
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#define SOFT_RESET_VC (1 << 13)
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#define SOFT_RESET_VGT (1 << 14)
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#define GRBM_STATUS 0x8010
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#define CMDFIFO_AVAIL_MASK 0x0000000F
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#define GUI_ACTIVE (1<<31)
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#define SRBM_RQ_PENDING (1 << 5)
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#define CF_RQ_PENDING (1 << 7)
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#define PF_RQ_PENDING (1 << 8)
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#define GRBM_EE_BUSY (1 << 10)
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#define SX_CLEAN (1 << 11)
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#define DB_CLEAN (1 << 12)
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#define CB_CLEAN (1 << 13)
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#define TA_BUSY (1 << 14)
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#define VGT_BUSY_NO_DMA (1 << 16)
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#define VGT_BUSY (1 << 17)
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#define SX_BUSY (1 << 20)
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#define SH_BUSY (1 << 21)
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#define SPI_BUSY (1 << 22)
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#define SC_BUSY (1 << 24)
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#define PA_BUSY (1 << 25)
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#define DB_BUSY (1 << 26)
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#define CP_COHERENCY_BUSY (1 << 28)
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#define CP_BUSY (1 << 29)
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#define CB_BUSY (1 << 30)
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#define GUI_ACTIVE (1 << 31)
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#define GRBM_STATUS_SE0 0x8014
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#define GRBM_STATUS_SE1 0x8018
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#define SE_SX_CLEAN (1 << 0)
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#define SE_DB_CLEAN (1 << 1)
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#define SE_CB_CLEAN (1 << 2)
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#define SE_TA_BUSY (1 << 25)
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#define SE_SX_BUSY (1 << 26)
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#define SE_SPI_BUSY (1 << 27)
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#define SE_SH_BUSY (1 << 28)
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#define SE_SC_BUSY (1 << 29)
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#define SE_DB_BUSY (1 << 30)
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#define SE_CB_BUSY (1 << 31)
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#define HDP_HOST_PATH_CNTL 0x2C00
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#define HDP_NONSURFACE_BASE 0x2C04
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@ -266,5 +309,21 @@
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#define WAIT_UNTIL 0x8040
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#define SRBM_STATUS 0x0E50
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#define SRBM_SOFT_RESET 0x0E60
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#define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6
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#define SOFT_RESET_BIF (1 << 1)
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#define SOFT_RESET_CG (1 << 2)
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#define SOFT_RESET_DC (1 << 5)
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#define SOFT_RESET_GRBM (1 << 8)
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#define SOFT_RESET_HDP (1 << 9)
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#define SOFT_RESET_IH (1 << 10)
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#define SOFT_RESET_MC (1 << 11)
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#define SOFT_RESET_RLC (1 << 13)
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#define SOFT_RESET_ROM (1 << 14)
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#define SOFT_RESET_SEM (1 << 15)
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#define SOFT_RESET_VMC (1 << 17)
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#define SOFT_RESET_TST (1 << 21)
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#define SOFT_RESET_REGBB (1 << 22)
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#define SOFT_RESET_ORB (1 << 23)
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#endif
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