[PATCH] EDAC: cleanup code for clearing initial errors
Fix xxx_probe1() functions so they call xxx_get_error_info() functions to clear initial errors. This is simpler and cleaner than duplicating the low-level code for accessing PCI config space. Signed-off-by: David S. Peterson <dsp@llnl.gov> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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749ede5744
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@ -211,6 +211,7 @@ static int amd76x_probe1(struct pci_dev *pdev, int dev_idx)
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};
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u32 ems;
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u32 ems_mode;
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struct amd76x_error_info discard;
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debugf0("%s()\n", __func__);
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@ -270,9 +271,7 @@ static int amd76x_probe1(struct pci_dev *pdev, int dev_idx)
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csrow->edac_mode = ems_modes[ems_mode];
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}
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/* clear counters */
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pci_write_bits32(mci->pdev, AMD76X_ECC_MODE_STATUS, (u32) (0x3 << 8),
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(u32) (0x3 << 8));
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amd76x_get_error_info(mci, &discard); /* clear counters */
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if (edac_mc_add_mc(mci)) {
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debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
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@ -747,8 +747,6 @@ static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
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int rc = -ENODEV;
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int index;
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u16 pci_data;
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u32 stat32;
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u16 stat16;
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u8 stat8;
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struct mem_ctl_info *mci = NULL;
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struct e752x_pvt *pvt = NULL;
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@ -760,6 +758,7 @@ static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
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u32 dra;
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unsigned long last_cumul_size;
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struct pci_dev *dev = NULL;
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struct e752x_error_info discard;
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debugf0("%s(): mci\n", __func__);
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debugf0("Starting Probe1\n");
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@ -938,24 +937,7 @@ static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
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pci_write_config_byte(dev, E752X_DRAM_ERRMASK, 0x00);
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pci_write_config_byte(dev, E752X_DRAM_SMICMD, 0x00);
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/* clear other MCH errors */
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pci_read_config_dword(dev, E752X_FERR_GLOBAL, &stat32);
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pci_write_config_dword(dev, E752X_FERR_GLOBAL, stat32);
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pci_read_config_dword(dev, E752X_NERR_GLOBAL, &stat32);
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pci_write_config_dword(dev, E752X_NERR_GLOBAL, stat32);
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pci_read_config_byte(dev, E752X_HI_FERR, &stat8);
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pci_write_config_byte(dev, E752X_HI_FERR, stat8);
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pci_read_config_byte(dev, E752X_HI_NERR, &stat8);
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pci_write_config_byte(dev, E752X_HI_NERR, stat8);
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pci_read_config_dword(dev, E752X_SYSBUS_FERR, &stat32);
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pci_write_config_dword(dev, E752X_SYSBUS_FERR, stat32);
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pci_read_config_byte(dev, E752X_BUF_FERR, &stat8);
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pci_write_config_byte(dev, E752X_BUF_FERR, stat8);
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pci_read_config_byte(dev, E752X_BUF_NERR, &stat8);
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pci_write_config_byte(dev, E752X_BUF_NERR, stat8);
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pci_read_config_word(dev, E752X_DRAM_FERR, &stat16);
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pci_write_config_word(dev, E752X_DRAM_FERR, stat16);
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pci_read_config_word(dev, E752X_DRAM_NERR, &stat16);
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pci_write_config_word(dev, E752X_DRAM_NERR, stat16);
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e752x_get_error_info(mci, &discard);
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/* get this far and it's successful */
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debugf3("%s(): success\n", __func__);
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@ -357,7 +357,7 @@ static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
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int drc_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */
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u32 dra;
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unsigned long last_cumul_size;
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struct e7xxx_error_info discard;
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debugf0("%s(): mci\n", __func__);
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@ -470,8 +470,7 @@ static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
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pvt->tolm, pvt->remapbase, pvt->remaplimit);
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/* clear any pending errors, or initial state bits */
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pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_FERR, 0x03, 0x03);
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pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_NERR, 0x03, 0x03);
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e7xxx_get_error_info(mci, &discard);
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if (edac_mc_add_mc(mci) != 0) {
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debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
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@ -2095,9 +2095,6 @@ static int __init edac_mc_init(void)
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*/
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clear_pci_parity_errors();
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/* perform check for first time to harvest boot leftovers */
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do_edac_check();
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/* Create the MC sysfs entires */
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if (edac_sysfs_memctrl_setup()) {
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edac_printk(KERN_ERR, EDAC_MC,
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@ -134,6 +134,7 @@ static int i82860_probe1(struct pci_dev *pdev, int dev_idx)
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int index;
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struct mem_ctl_info *mci = NULL;
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unsigned long last_cumul_size;
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struct i82860_error_info discard;
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u16 mchcfg_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */
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@ -200,8 +201,7 @@ static int i82860_probe1(struct pci_dev *pdev, int dev_idx)
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csrow->edac_mode = mchcfg_ddim ? EDAC_SECDED : EDAC_NONE;
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}
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/* clear counters */
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pci_write_bits16(mci->pdev, I82860_ERRSTS, 0x0003, 0x0003);
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i82860_get_error_info(mci, &discard); /* clear counters */
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if (edac_mc_add_mc(mci)) {
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debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
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@ -286,6 +286,7 @@ static int i82875p_probe1(struct pci_dev *pdev, int dev_idx)
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u32 drc_chan; /* Number of channels 0=1chan,1=2chan */
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u32 nr_chans;
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u32 drc_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */
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struct i82875p_error_info discard;
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debugf0("%s()\n", __func__);
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@ -397,8 +398,7 @@ static int i82875p_probe1(struct pci_dev *pdev, int dev_idx)
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csrow->edac_mode = drc_ddim ? EDAC_SECDED : EDAC_NONE;
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}
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/* clear counters */
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pci_write_bits16(mci->pdev, I82875P_ERRSTS, 0x0081, 0x0081);
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i82875p_get_error_info(mci, &discard); /* clear counters */
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if (edac_mc_add_mc(mci)) {
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debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
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@ -219,7 +219,7 @@ static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
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u32 scrub_disabled;
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u32 sdram_refresh_rate;
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u32 row_high_limit_last = 0;
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u32 eap_init_bits;
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struct r82600_error_info discard;
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debugf0("%s()\n", __func__);
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@ -311,8 +311,7 @@ static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
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row_high_limit_last = row_high_limit;
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}
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/* clear counters */
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/* FIXME should we? */
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r82600_get_error_info(mci, &discard); /* clear counters */
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if (edac_mc_add_mc(mci)) {
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debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
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@ -321,19 +320,12 @@ static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
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/* get this far and it's successful */
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/* Clear error flags to allow next error to be reported [p.62] */
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/* Test systems seem to always have the UE flag raised on boot */
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eap_init_bits = BIT(0) & BIT(1);
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if (disable_hardware_scrub) {
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eap_init_bits |= BIT(31);
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debugf3("%s(): Disabling Hardware Scrub (scrub on error)\n",
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__func__);
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pci_write_bits32(mci->pdev, R82600_EAP, BIT(31), BIT(31));
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}
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pci_write_bits32(mci->pdev, R82600_EAP, eap_init_bits,
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eap_init_bits);
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debugf3("%s(): success\n", __func__);
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return 0;
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