drm/exynos/hdmi: simplify HDMI-PHY power sequence
Currently driver tries to set specific HDMI-PHY registers in three situations: - before reset, - before power off, - after applying HDMI-PHY configuration. First two cases seems to be unnecessary - register contents will be lost anyway. The third case can be merged with HDMI-PHY configuration by fixing the last byte of configuration data. The patch has been tested with following platforms: - exynos4210-universal_c210, - exynos4412-odroidu3, - exynos5422-odroidxu3. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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Коммит
74a74ff4e6
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@ -148,7 +148,7 @@ static const struct hdmiphy_config hdmiphy_v13_configs[] = {
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0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
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0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
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0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
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0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
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0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x80,
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},
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},
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{
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@ -157,7 +157,7 @@ static const struct hdmiphy_config hdmiphy_v13_configs[] = {
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0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
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0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
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0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
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0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
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0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x80,
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},
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},
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{
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@ -166,7 +166,7 @@ static const struct hdmiphy_config hdmiphy_v13_configs[] = {
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0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
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0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9,
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0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
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0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x00,
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0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x80,
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},
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},
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{
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@ -175,7 +175,7 @@ static const struct hdmiphy_config hdmiphy_v13_configs[] = {
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0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40,
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0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba,
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0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0,
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0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x00,
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0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x80,
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},
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},
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{
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@ -184,7 +184,7 @@ static const struct hdmiphy_config hdmiphy_v13_configs[] = {
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0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40,
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0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba,
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0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
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0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x00,
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0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x80,
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},
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},
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};
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@ -214,7 +214,7 @@ static const struct hdmiphy_config hdmiphy_v14_configs[] = {
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0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
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0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
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0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
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0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
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0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
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},
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},
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{
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@ -277,7 +277,7 @@ static const struct hdmiphy_config hdmiphy_v14_configs[] = {
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0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08,
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0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
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0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
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0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
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0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
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},
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},
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{
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@ -340,7 +340,7 @@ static const struct hdmiphy_config hdmiphy_v14_configs[] = {
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0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08,
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0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
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0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
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0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
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0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
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},
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},
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};
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@ -563,26 +563,6 @@ static inline void hdmi_reg_writemask(struct hdmi_context *hdata,
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writel(value, hdata->regs + reg_id);
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}
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static int hdmiphy_reg_writeb(struct hdmi_context *hdata,
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u32 reg_offset, u8 value)
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{
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if (hdata->hdmiphy_port) {
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u8 buffer[2];
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int ret;
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buffer[0] = reg_offset;
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buffer[1] = value;
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ret = i2c_master_send(hdata->hdmiphy_port, buffer, 2);
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if (ret == 2)
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return 0;
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return ret;
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} else {
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writeb(value, hdata->regs_hdmiphy + (reg_offset<<2));
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return 0;
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}
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}
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static int hdmiphy_reg_write_buf(struct hdmi_context *hdata,
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u32 reg_offset, const u8 *buf, u32 len)
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{
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@ -1598,10 +1578,6 @@ static void hdmiphy_conf_reset(struct hdmi_context *hdata)
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clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_pixel);
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clk_prepare_enable(hdata->res.sclk_hdmi);
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/* operation mode */
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hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
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HDMI_PHY_ENABLE_MODE_SET);
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/* reset hdmiphy */
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hdmi_reg_writemask(hdata, HDMI_PHY_RSTOUT, ~0, HDMI_PHY_SW_RSTOUT);
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usleep_range(10000, 12000);
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@ -1609,48 +1585,6 @@ static void hdmiphy_conf_reset(struct hdmi_context *hdata)
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usleep_range(10000, 12000);
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}
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static void hdmiphy_poweron(struct hdmi_context *hdata)
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{
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if (hdata->drv_data->type != HDMI_TYPE14)
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return;
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DRM_DEBUG_KMS("\n");
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/* For PHY Mode Setting */
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hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
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HDMI_PHY_ENABLE_MODE_SET);
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/* Phy Power On */
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hdmiphy_reg_writeb(hdata, HDMIPHY_POWER,
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HDMI_PHY_POWER_ON);
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/* For PHY Mode Setting */
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hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
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HDMI_PHY_DISABLE_MODE_SET);
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/* PHY SW Reset */
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hdmiphy_conf_reset(hdata);
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}
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static void hdmiphy_poweroff(struct hdmi_context *hdata)
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{
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if (hdata->drv_data->type != HDMI_TYPE14)
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return;
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DRM_DEBUG_KMS("\n");
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/* PHY SW Reset */
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hdmiphy_conf_reset(hdata);
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/* For PHY Mode Setting */
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hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
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HDMI_PHY_ENABLE_MODE_SET);
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/* PHY Power Off */
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hdmiphy_reg_writeb(hdata, HDMIPHY_POWER,
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HDMI_PHY_POWER_OFF);
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/* For PHY Mode Setting */
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hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
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HDMI_PHY_DISABLE_MODE_SET);
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}
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static void hdmiphy_conf_apply(struct hdmi_context *hdata)
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{
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int ret;
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@ -1671,14 +1605,6 @@ static void hdmiphy_conf_apply(struct hdmi_context *hdata)
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}
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usleep_range(10000, 12000);
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ret = hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE,
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HDMI_PHY_DISABLE_MODE_SET);
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if (ret) {
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DRM_ERROR("failed to enable hdmiphy\n");
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return;
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}
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}
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static void hdmi_conf_apply(struct hdmi_context *hdata)
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@ -1736,7 +1662,6 @@ static void hdmi_enable(struct drm_encoder *encoder)
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clk_prepare_enable(res->hdmi);
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clk_prepare_enable(res->sclk_hdmi);
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hdmiphy_poweron(hdata);
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hdmi_conf_apply(hdata);
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}
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@ -1767,8 +1692,6 @@ static void hdmi_disable(struct drm_encoder *encoder)
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/* HDMI System Disable */
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hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_EN);
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hdmiphy_poweroff(hdata);
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cancel_delayed_work(&hdata->hotplug_work);
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clk_disable_unprepare(res->sclk_hdmi);
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