cxgb4: Add support for cim_qcfg entry in debugfs
Adds debug log to get cim queue config Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Hariprasad Shenai
David S. Miller
Родитель
f1ff24aa95
Коммит
74b3092c45
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@ -1041,6 +1041,7 @@ int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
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int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
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const unsigned int *valp);
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int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
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void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
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const char *t4_get_port_type_description(enum fw_port_type port_type);
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void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
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void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
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@ -168,6 +168,75 @@ static const struct file_operations cim_la_fops = {
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.release = seq_release_private
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};
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static int cim_qcfg_show(struct seq_file *seq, void *v)
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{
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static const char * const qname[] = {
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"TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI",
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"ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI",
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"SGE0-RX", "SGE1-RX"
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};
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int i;
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struct adapter *adap = seq->private;
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u16 base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
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u16 size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
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u32 stat[(4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5))];
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u16 thres[CIM_NUM_IBQ];
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u32 obq_wr_t4[2 * CIM_NUM_OBQ], *wr;
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u32 obq_wr_t5[2 * CIM_NUM_OBQ_T5];
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u32 *p = stat;
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int cim_num_obq = is_t4(adap->params.chip) ?
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CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
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i = t4_cim_read(adap, is_t4(adap->params.chip) ? UP_IBQ_0_RDADDR_A :
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UP_IBQ_0_SHADOW_RDADDR_A,
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ARRAY_SIZE(stat), stat);
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if (!i) {
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if (is_t4(adap->params.chip)) {
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i = t4_cim_read(adap, UP_OBQ_0_REALADDR_A,
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ARRAY_SIZE(obq_wr_t4), obq_wr_t4);
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wr = obq_wr_t4;
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} else {
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i = t4_cim_read(adap, UP_OBQ_0_SHADOW_REALADDR_A,
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ARRAY_SIZE(obq_wr_t5), obq_wr_t5);
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wr = obq_wr_t5;
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}
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}
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if (i)
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return i;
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t4_read_cimq_cfg(adap, base, size, thres);
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seq_printf(seq,
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" Queue Base Size Thres RdPtr WrPtr SOP EOP Avail\n");
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for (i = 0; i < CIM_NUM_IBQ; i++, p += 4)
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seq_printf(seq, "%7s %5x %5u %5u %6x %4x %4u %4u %5u\n",
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qname[i], base[i], size[i], thres[i],
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IBQRDADDR_G(p[0]), IBQWRADDR_G(p[1]),
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QUESOPCNT_G(p[3]), QUEEOPCNT_G(p[3]),
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QUEREMFLITS_G(p[2]) * 16);
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for ( ; i < CIM_NUM_IBQ + cim_num_obq; i++, p += 4, wr += 2)
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seq_printf(seq, "%7s %5x %5u %12x %4x %4u %4u %5u\n",
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qname[i], base[i], size[i],
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QUERDADDR_G(p[0]) & 0x3fff, wr[0] - base[i],
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QUESOPCNT_G(p[3]), QUEEOPCNT_G(p[3]),
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QUEREMFLITS_G(p[2]) * 16);
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return 0;
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}
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static int cim_qcfg_open(struct inode *inode, struct file *file)
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{
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return single_open(file, cim_qcfg_show, inode->i_private);
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}
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static const struct file_operations cim_qcfg_fops = {
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.owner = THIS_MODULE,
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.open = cim_qcfg_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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/* Firmware Device Log dump. */
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static const char * const devlog_level_strings[] = {
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[FW_DEVLOG_LEVEL_EMERG] = "EMERG",
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@ -443,6 +512,7 @@ int t4_setup_debugfs(struct adapter *adap)
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static struct t4_debugfs_entry t4_debugfs_files[] = {
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{ "cim_la", &cim_la_fops, S_IRUSR, 0 },
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{ "cim_qcfg", &cim_qcfg_fops, S_IRUSR, 0 },
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{ "devlog", &devlog_fops, S_IRUSR, 0 },
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{ "l2t", &t4_l2t_fops, S_IRUSR, 0},
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};
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@ -4325,6 +4325,41 @@ int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
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return 0;
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}
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/**
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* t4_read_cimq_cfg - read CIM queue configuration
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* @adap: the adapter
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* @base: holds the queue base addresses in bytes
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* @size: holds the queue sizes in bytes
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* @thres: holds the queue full thresholds in bytes
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*
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* Returns the current configuration of the CIM queues, starting with
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* the IBQs, then the OBQs.
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*/
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void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
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{
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unsigned int i, v;
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int cim_num_obq = is_t4(adap->params.chip) ?
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CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
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for (i = 0; i < CIM_NUM_IBQ; i++) {
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t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
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QUENUMSELECT_V(i));
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v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
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/* value is in 256-byte units */
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*base++ = CIMQBASE_G(v) * 256;
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*size++ = CIMQSIZE_G(v) * 256;
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*thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
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}
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for (i = 0; i < cim_num_obq; i++) {
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t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
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QUENUMSELECT_V(i));
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v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
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/* value is in 256-byte units */
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*base++ = CIMQBASE_G(v) * 256;
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*size++ = CIMQSIZE_G(v) * 256;
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}
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}
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/**
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* t4_cim_read - read a block from CIM internal address space
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* @adap: the adapter
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@ -56,6 +56,9 @@ enum {
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};
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enum {
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CIM_NUM_IBQ = 6, /* # of CIM IBQs */
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CIM_NUM_OBQ = 6, /* # of CIM OBQs */
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CIM_NUM_OBQ_T5 = 8, /* # of CIM OBQs for T5 adapter */
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CIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */
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};
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@ -2096,4 +2096,59 @@
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#define UPDBGLACAPTPCONLY_V(x) ((x) << UPDBGLACAPTPCONLY_S)
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#define UPDBGLACAPTPCONLY_F UPDBGLACAPTPCONLY_V(1U)
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#define CIM_QUEUE_CONFIG_REF_A 0x7b48
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#define CIM_QUEUE_CONFIG_CTRL_A 0x7b4c
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#define CIMQSIZE_S 24
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#define CIMQSIZE_M 0x3fU
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#define CIMQSIZE_G(x) (((x) >> CIMQSIZE_S) & CIMQSIZE_M)
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#define CIMQBASE_S 16
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#define CIMQBASE_M 0x3fU
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#define CIMQBASE_G(x) (((x) >> CIMQBASE_S) & CIMQBASE_M)
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#define QUEFULLTHRSH_S 0
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#define QUEFULLTHRSH_M 0x1ffU
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#define QUEFULLTHRSH_G(x) (((x) >> QUEFULLTHRSH_S) & QUEFULLTHRSH_M)
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#define UP_IBQ_0_RDADDR_A 0x10
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#define UP_IBQ_0_SHADOW_RDADDR_A 0x280
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#define UP_OBQ_0_REALADDR_A 0x104
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#define UP_OBQ_0_SHADOW_REALADDR_A 0x394
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#define IBQRDADDR_S 0
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#define IBQRDADDR_M 0x1fffU
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#define IBQRDADDR_G(x) (((x) >> IBQRDADDR_S) & IBQRDADDR_M)
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#define IBQWRADDR_S 0
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#define IBQWRADDR_M 0x1fffU
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#define IBQWRADDR_G(x) (((x) >> IBQWRADDR_S) & IBQWRADDR_M)
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#define QUERDADDR_S 0
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#define QUERDADDR_M 0x7fffU
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#define QUERDADDR_G(x) (((x) >> QUERDADDR_S) & QUERDADDR_M)
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#define QUEREMFLITS_S 0
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#define QUEREMFLITS_M 0x7ffU
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#define QUEREMFLITS_G(x) (((x) >> QUEREMFLITS_S) & QUEREMFLITS_M)
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#define QUEEOPCNT_S 16
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#define QUEEOPCNT_M 0xfffU
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#define QUEEOPCNT_G(x) (((x) >> QUEEOPCNT_S) & QUEEOPCNT_M)
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#define QUESOPCNT_S 0
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#define QUESOPCNT_M 0xfffU
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#define QUESOPCNT_G(x) (((x) >> QUESOPCNT_S) & QUESOPCNT_M)
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#define OBQSELECT_S 4
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#define OBQSELECT_V(x) ((x) << OBQSELECT_S)
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#define OBQSELECT_F OBQSELECT_V(1U)
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#define IBQSELECT_S 3
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#define IBQSELECT_V(x) ((x) << IBQSELECT_S)
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#define IBQSELECT_F IBQSELECT_V(1U)
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#define QUENUMSELECT_S 0
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#define QUENUMSELECT_V(x) ((x) << QUENUMSELECT_S)
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#endif /* __T4_REGS_H */
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