sh: SH-2A FPU support.
Signed-off-by: Kieran Bingham <kbingham@mpc-data.co.uk> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
Родитель
a8f67f4b4d
Коммит
74d99a5e26
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@ -161,6 +161,7 @@ config CPU_SUBTYPE_SH7619
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config CPU_SUBTYPE_SH7203
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bool "Support SH7203 processor"
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select CPU_SH2A
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select CPU_HAS_FPU
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config CPU_SUBTYPE_SH7206
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bool "Support SH7206 processor"
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@ -169,6 +170,7 @@ config CPU_SUBTYPE_SH7206
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config CPU_SUBTYPE_SH7263
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bool "Support SH7263 processor"
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select CPU_SH2A
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select CPU_HAS_FPU
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# SH-3 Processor Support
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@ -20,10 +20,6 @@ isa-$(CONFIG_CPU_SH4AL_DSP) := sh4al
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isa-$(CONFIG_CPU_SH5) := shmedia
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isa-$(CONFIG_SH_DSP) := $(isa-y)-dsp
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ifndef CONFIG_MMU
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isa-y := $(isa-y)-nommu
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endif
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ifndef CONFIG_SH_DSP
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ifndef CONFIG_SH_FPU
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isa-y := $(isa-y)-nofpu
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@ -149,6 +149,14 @@ ENTRY(exception_handler)
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mov #32,r8
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cmp/hs r8,r9
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bt trap_entry ! 64 > vec >= 32 is trap
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#if defined(CONFIG_SH_FPU)
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mov #13,r8
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cmp/eq r8,r9
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bt 10f ! fpu
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nop
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#endif
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mov.l 4f,r8
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mov r9,r4
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shll2 r9
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@ -158,6 +166,10 @@ ENTRY(exception_handler)
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cmp/eq r9,r8
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bf 3f
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mov.l 8f,r8 ! unhandled exception
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#if defined(CONFIG_SH_FPU)
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10:
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mov.l 9f, r8 ! unhandled exception
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#endif
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3:
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mov.l 5f,r10
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jmp @r8
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@ -177,7 +189,10 @@ interrupt_entry:
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6: .long ret_from_irq
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7: .long do_IRQ
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8: .long do_exception_error
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#ifdef CONFIG_SH_FPU
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9: .long fpu_error_trap_handler
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#endif
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trap_entry:
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mov #0x30,r8
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cmp/ge r8,r9 ! vector 0x20-0x2f is systemcall
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@ -6,6 +6,8 @@ obj-y := common.o probe.o opcode_helper.o
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common-y += $(addprefix ../sh2/, ex.o entry.o)
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obj-$(CONFIG_SH_FPU) += fpu.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7263) += setup-sh7203.o clock-sh7203.o
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@ -0,0 +1,633 @@
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/*
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* Save/restore floating point context for signal handlers.
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*
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* Copyright (C) 1999, 2000 Kaz Kojima & Niibe Yutaka
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* FIXME! These routines can be optimized in big endian case.
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*/
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#include <linux/sched.h>
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#include <linux/signal.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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/* The PR (precision) bit in the FP Status Register must be clear when
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* an frchg instruction is executed, otherwise the instruction is undefined.
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* Executing frchg with PR set causes a trap on some SH4 implementations.
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*/
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#define FPSCR_RCHG 0x00000000
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/*
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* Save FPU registers onto task structure.
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* Assume called with FPU enabled (SR.FD=0).
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*/
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void
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save_fpu(struct task_struct *tsk, struct pt_regs *regs)
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{
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unsigned long dummy;
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clear_tsk_thread_flag(tsk, TIF_USEDFPU);
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enable_fpu();
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asm volatile("sts.l fpul, @-%0\n\t"
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"sts.l fpscr, @-%0\n\t"
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"fmov.s fr15, @-%0\n\t"
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"fmov.s fr14, @-%0\n\t"
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"fmov.s fr13, @-%0\n\t"
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"fmov.s fr12, @-%0\n\t"
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"fmov.s fr11, @-%0\n\t"
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"fmov.s fr10, @-%0\n\t"
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"fmov.s fr9, @-%0\n\t"
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"fmov.s fr8, @-%0\n\t"
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"fmov.s fr7, @-%0\n\t"
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"fmov.s fr6, @-%0\n\t"
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"fmov.s fr5, @-%0\n\t"
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"fmov.s fr4, @-%0\n\t"
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"fmov.s fr3, @-%0\n\t"
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"fmov.s fr2, @-%0\n\t"
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"fmov.s fr1, @-%0\n\t"
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"fmov.s fr0, @-%0\n\t"
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"lds %3, fpscr\n\t"
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: "=r" (dummy)
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: "0" ((char *)(&tsk->thread.fpu.hard.status)),
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"r" (FPSCR_RCHG),
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"r" (FPSCR_INIT)
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: "memory");
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disable_fpu();
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release_fpu(regs);
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}
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static void
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restore_fpu(struct task_struct *tsk)
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{
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unsigned long dummy;
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enable_fpu();
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asm volatile("fmov.s @%0+, fr0\n\t"
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"fmov.s @%0+, fr1\n\t"
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"fmov.s @%0+, fr2\n\t"
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"fmov.s @%0+, fr3\n\t"
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"fmov.s @%0+, fr4\n\t"
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"fmov.s @%0+, fr5\n\t"
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"fmov.s @%0+, fr6\n\t"
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"fmov.s @%0+, fr7\n\t"
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"fmov.s @%0+, fr8\n\t"
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"fmov.s @%0+, fr9\n\t"
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"fmov.s @%0+, fr10\n\t"
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"fmov.s @%0+, fr11\n\t"
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"fmov.s @%0+, fr12\n\t"
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"fmov.s @%0+, fr13\n\t"
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"fmov.s @%0+, fr14\n\t"
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"fmov.s @%0+, fr15\n\t"
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"lds.l @%0+, fpscr\n\t"
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"lds.l @%0+, fpul\n\t"
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: "=r" (dummy)
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: "0" (&tsk->thread.fpu), "r" (FPSCR_RCHG)
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: "memory");
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disable_fpu();
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}
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/*
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* Load the FPU with signalling NANS. This bit pattern we're using
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* has the property that no matter wether considered as single or as
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* double precission represents signaling NANS.
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*/
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static void
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fpu_init(void)
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{
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enable_fpu();
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asm volatile("lds %0, fpul\n\t"
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"fsts fpul, fr0\n\t"
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"fsts fpul, fr1\n\t"
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"fsts fpul, fr2\n\t"
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"fsts fpul, fr3\n\t"
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"fsts fpul, fr4\n\t"
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"fsts fpul, fr5\n\t"
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"fsts fpul, fr6\n\t"
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"fsts fpul, fr7\n\t"
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"fsts fpul, fr8\n\t"
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"fsts fpul, fr9\n\t"
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"fsts fpul, fr10\n\t"
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"fsts fpul, fr11\n\t"
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"fsts fpul, fr12\n\t"
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"fsts fpul, fr13\n\t"
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"fsts fpul, fr14\n\t"
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"fsts fpul, fr15\n\t"
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"lds %2, fpscr\n\t"
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: /* no output */
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: "r" (0), "r" (FPSCR_RCHG), "r" (FPSCR_INIT));
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disable_fpu();
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}
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/*
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* Emulate arithmetic ops on denormalized number for some FPU insns.
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*/
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/* denormalized float * float */
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static int denormal_mulf(int hx, int hy)
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{
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unsigned int ix, iy;
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unsigned long long m, n;
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int exp, w;
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ix = hx & 0x7fffffff;
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iy = hy & 0x7fffffff;
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if (iy < 0x00800000 || ix == 0)
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return ((hx ^ hy) & 0x80000000);
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exp = (iy & 0x7f800000) >> 23;
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ix &= 0x007fffff;
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iy = (iy & 0x007fffff) | 0x00800000;
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m = (unsigned long long)ix * iy;
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n = m;
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w = -1;
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while (n) { n >>= 1; w++; }
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/* FIXME: use guard bits */
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exp += w - 126 - 46;
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if (exp > 0)
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ix = ((int) (m >> (w - 23)) & 0x007fffff) | (exp << 23);
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else if (exp + 22 >= 0)
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ix = (int) (m >> (w - 22 - exp)) & 0x007fffff;
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else
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ix = 0;
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ix |= (hx ^ hy) & 0x80000000;
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return ix;
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}
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/* denormalized double * double */
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static void mult64(unsigned long long x, unsigned long long y,
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unsigned long long *highp, unsigned long long *lowp)
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{
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unsigned long long sub0, sub1, sub2, sub3;
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unsigned long long high, low;
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sub0 = (x >> 32) * (unsigned long) (y >> 32);
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sub1 = (x & 0xffffffffLL) * (unsigned long) (y >> 32);
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sub2 = (x >> 32) * (unsigned long) (y & 0xffffffffLL);
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sub3 = (x & 0xffffffffLL) * (unsigned long) (y & 0xffffffffLL);
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low = sub3;
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high = 0LL;
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sub3 += (sub1 << 32);
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if (low > sub3)
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high++;
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low = sub3;
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sub3 += (sub2 << 32);
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if (low > sub3)
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high++;
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low = sub3;
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high += (sub1 >> 32) + (sub2 >> 32);
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high += sub0;
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*lowp = low;
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*highp = high;
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}
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static inline long long rshift64(unsigned long long mh,
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unsigned long long ml, int n)
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{
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if (n >= 64)
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return mh >> (n - 64);
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return (mh << (64 - n)) | (ml >> n);
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}
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static long long denormal_muld(long long hx, long long hy)
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{
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unsigned long long ix, iy;
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unsigned long long mh, ml, nh, nl;
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int exp, w;
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ix = hx & 0x7fffffffffffffffLL;
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iy = hy & 0x7fffffffffffffffLL;
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if (iy < 0x0010000000000000LL || ix == 0)
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return ((hx ^ hy) & 0x8000000000000000LL);
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exp = (iy & 0x7ff0000000000000LL) >> 52;
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ix &= 0x000fffffffffffffLL;
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iy = (iy & 0x000fffffffffffffLL) | 0x0010000000000000LL;
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mult64(ix, iy, &mh, &ml);
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nh = mh;
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nl = ml;
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w = -1;
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if (nh) {
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while (nh) { nh >>= 1; w++;}
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w += 64;
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} else
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while (nl) { nl >>= 1; w++;}
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/* FIXME: use guard bits */
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exp += w - 1022 - 52 * 2;
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if (exp > 0)
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ix = (rshift64(mh, ml, w - 52) & 0x000fffffffffffffLL)
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| ((long long)exp << 52);
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else if (exp + 51 >= 0)
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ix = rshift64(mh, ml, w - 51 - exp) & 0x000fffffffffffffLL;
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else
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ix = 0;
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ix |= (hx ^ hy) & 0x8000000000000000LL;
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return ix;
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}
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/* ix - iy where iy: denormal and ix, iy >= 0 */
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static int denormal_subf1(unsigned int ix, unsigned int iy)
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{
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int frac;
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int exp;
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if (ix < 0x00800000)
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return ix - iy;
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exp = (ix & 0x7f800000) >> 23;
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if (exp - 1 > 31)
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return ix;
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iy >>= exp - 1;
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if (iy == 0)
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return ix;
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frac = (ix & 0x007fffff) | 0x00800000;
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frac -= iy;
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while (frac < 0x00800000) {
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if (--exp == 0)
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return frac;
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frac <<= 1;
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}
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return (exp << 23) | (frac & 0x007fffff);
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}
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/* ix + iy where iy: denormal and ix, iy >= 0 */
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static int denormal_addf1(unsigned int ix, unsigned int iy)
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{
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int frac;
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int exp;
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if (ix < 0x00800000)
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return ix + iy;
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exp = (ix & 0x7f800000) >> 23;
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if (exp - 1 > 31)
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return ix;
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iy >>= exp - 1;
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if (iy == 0)
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return ix;
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frac = (ix & 0x007fffff) | 0x00800000;
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frac += iy;
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if (frac >= 0x01000000) {
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frac >>= 1;
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++exp;
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}
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return (exp << 23) | (frac & 0x007fffff);
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}
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static int denormal_addf(int hx, int hy)
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{
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unsigned int ix, iy;
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int sign;
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if ((hx ^ hy) & 0x80000000) {
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sign = hx & 0x80000000;
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ix = hx & 0x7fffffff;
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iy = hy & 0x7fffffff;
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if (iy < 0x00800000) {
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ix = denormal_subf1(ix, iy);
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if (ix < 0) {
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ix = -ix;
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sign ^= 0x80000000;
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}
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} else {
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ix = denormal_subf1(iy, ix);
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sign ^= 0x80000000;
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}
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} else {
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sign = hx & 0x80000000;
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ix = hx & 0x7fffffff;
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iy = hy & 0x7fffffff;
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if (iy < 0x00800000)
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ix = denormal_addf1(ix, iy);
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else
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ix = denormal_addf1(iy, ix);
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}
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return sign | ix;
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}
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/* ix - iy where iy: denormal and ix, iy >= 0 */
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static long long denormal_subd1(unsigned long long ix, unsigned long long iy)
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{
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long long frac;
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int exp;
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if (ix < 0x0010000000000000LL)
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return ix - iy;
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exp = (ix & 0x7ff0000000000000LL) >> 52;
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if (exp - 1 > 63)
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return ix;
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iy >>= exp - 1;
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if (iy == 0)
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return ix;
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frac = (ix & 0x000fffffffffffffLL) | 0x0010000000000000LL;
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frac -= iy;
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while (frac < 0x0010000000000000LL) {
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if (--exp == 0)
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return frac;
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frac <<= 1;
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}
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return ((long long)exp << 52) | (frac & 0x000fffffffffffffLL);
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}
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/* ix + iy where iy: denormal and ix, iy >= 0 */
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static long long denormal_addd1(unsigned long long ix, unsigned long long iy)
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{
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long long frac;
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long long exp;
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if (ix < 0x0010000000000000LL)
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return ix + iy;
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exp = (ix & 0x7ff0000000000000LL) >> 52;
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if (exp - 1 > 63)
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return ix;
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iy >>= exp - 1;
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if (iy == 0)
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return ix;
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frac = (ix & 0x000fffffffffffffLL) | 0x0010000000000000LL;
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frac += iy;
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if (frac >= 0x0020000000000000LL) {
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frac >>= 1;
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++exp;
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}
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return (exp << 52) | (frac & 0x000fffffffffffffLL);
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}
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static long long denormal_addd(long long hx, long long hy)
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{
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unsigned long long ix, iy;
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long long sign;
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if ((hx ^ hy) & 0x8000000000000000LL) {
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sign = hx & 0x8000000000000000LL;
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ix = hx & 0x7fffffffffffffffLL;
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iy = hy & 0x7fffffffffffffffLL;
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if (iy < 0x0010000000000000LL) {
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ix = denormal_subd1(ix, iy);
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if (ix < 0) {
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ix = -ix;
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sign ^= 0x8000000000000000LL;
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}
|
||||
} else {
|
||||
ix = denormal_subd1(iy, ix);
|
||||
sign ^= 0x8000000000000000LL;
|
||||
}
|
||||
} else {
|
||||
sign = hx & 0x8000000000000000LL;
|
||||
ix = hx & 0x7fffffffffffffffLL;
|
||||
iy = hy & 0x7fffffffffffffffLL;
|
||||
if (iy < 0x0010000000000000LL)
|
||||
ix = denormal_addd1(ix, iy);
|
||||
else
|
||||
ix = denormal_addd1(iy, ix);
|
||||
}
|
||||
|
||||
return sign | ix;
|
||||
}
|
||||
|
||||
/**
|
||||
* denormal_to_double - Given denormalized float number,
|
||||
* store double float
|
||||
*
|
||||
* @fpu: Pointer to sh_fpu_hard structure
|
||||
* @n: Index to FP register
|
||||
*/
|
||||
static void
|
||||
denormal_to_double (struct sh_fpu_hard_struct *fpu, int n)
|
||||
{
|
||||
unsigned long du, dl;
|
||||
unsigned long x = fpu->fpul;
|
||||
int exp = 1023 - 126;
|
||||
|
||||
if (x != 0 && (x & 0x7f800000) == 0) {
|
||||
du = (x & 0x80000000);
|
||||
while ((x & 0x00800000) == 0) {
|
||||
x <<= 1;
|
||||
exp--;
|
||||
}
|
||||
x &= 0x007fffff;
|
||||
du |= (exp << 20) | (x >> 3);
|
||||
dl = x << 29;
|
||||
|
||||
fpu->fp_regs[n] = du;
|
||||
fpu->fp_regs[n+1] = dl;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* ieee_fpe_handler - Handle denormalized number exception
|
||||
*
|
||||
* @regs: Pointer to register structure
|
||||
*
|
||||
* Returns 1 when it's handled (should not cause exception).
|
||||
*/
|
||||
static int
|
||||
ieee_fpe_handler (struct pt_regs *regs)
|
||||
{
|
||||
unsigned short insn = *(unsigned short *) regs->pc;
|
||||
unsigned short finsn;
|
||||
unsigned long nextpc;
|
||||
int nib[4] = {
|
||||
(insn >> 12) & 0xf,
|
||||
(insn >> 8) & 0xf,
|
||||
(insn >> 4) & 0xf,
|
||||
insn & 0xf};
|
||||
|
||||
if (nib[0] == 0xb ||
|
||||
(nib[0] == 0x4 && nib[2] == 0x0 && nib[3] == 0xb)) /* bsr & jsr */
|
||||
regs->pr = regs->pc + 4;
|
||||
if (nib[0] == 0xa || nib[0] == 0xb) { /* bra & bsr */
|
||||
nextpc = regs->pc + 4 + ((short) ((insn & 0xfff) << 4) >> 3);
|
||||
finsn = *(unsigned short *) (regs->pc + 2);
|
||||
} else if (nib[0] == 0x8 && nib[1] == 0xd) { /* bt/s */
|
||||
if (regs->sr & 1)
|
||||
nextpc = regs->pc + 4 + ((char) (insn & 0xff) << 1);
|
||||
else
|
||||
nextpc = regs->pc + 4;
|
||||
finsn = *(unsigned short *) (regs->pc + 2);
|
||||
} else if (nib[0] == 0x8 && nib[1] == 0xf) { /* bf/s */
|
||||
if (regs->sr & 1)
|
||||
nextpc = regs->pc + 4;
|
||||
else
|
||||
nextpc = regs->pc + 4 + ((char) (insn & 0xff) << 1);
|
||||
finsn = *(unsigned short *) (regs->pc + 2);
|
||||
} else if (nib[0] == 0x4 && nib[3] == 0xb &&
|
||||
(nib[2] == 0x0 || nib[2] == 0x2)) { /* jmp & jsr */
|
||||
nextpc = regs->regs[nib[1]];
|
||||
finsn = *(unsigned short *) (regs->pc + 2);
|
||||
} else if (nib[0] == 0x0 && nib[3] == 0x3 &&
|
||||
(nib[2] == 0x0 || nib[2] == 0x2)) { /* braf & bsrf */
|
||||
nextpc = regs->pc + 4 + regs->regs[nib[1]];
|
||||
finsn = *(unsigned short *) (regs->pc + 2);
|
||||
} else if (insn == 0x000b) { /* rts */
|
||||
nextpc = regs->pr;
|
||||
finsn = *(unsigned short *) (regs->pc + 2);
|
||||
} else {
|
||||
nextpc = regs->pc + 2;
|
||||
finsn = insn;
|
||||
}
|
||||
|
||||
#define FPSCR_FPU_ERROR (1 << 17)
|
||||
|
||||
if ((finsn & 0xf1ff) == 0xf0ad) { /* fcnvsd */
|
||||
struct task_struct *tsk = current;
|
||||
|
||||
if ((tsk->thread.fpu.hard.fpscr & FPSCR_FPU_ERROR)) {
|
||||
/* FPU error */
|
||||
denormal_to_double (&tsk->thread.fpu.hard,
|
||||
(finsn >> 8) & 0xf);
|
||||
} else
|
||||
return 0;
|
||||
|
||||
regs->pc = nextpc;
|
||||
return 1;
|
||||
} else if ((finsn & 0xf00f) == 0xf002) { /* fmul */
|
||||
struct task_struct *tsk = current;
|
||||
int fpscr;
|
||||
int n, m, prec;
|
||||
unsigned int hx, hy;
|
||||
|
||||
n = (finsn >> 8) & 0xf;
|
||||
m = (finsn >> 4) & 0xf;
|
||||
hx = tsk->thread.fpu.hard.fp_regs[n];
|
||||
hy = tsk->thread.fpu.hard.fp_regs[m];
|
||||
fpscr = tsk->thread.fpu.hard.fpscr;
|
||||
prec = fpscr & (1 << 19);
|
||||
|
||||
if ((fpscr & FPSCR_FPU_ERROR)
|
||||
&& (prec && ((hx & 0x7fffffff) < 0x00100000
|
||||
|| (hy & 0x7fffffff) < 0x00100000))) {
|
||||
long long llx, lly;
|
||||
|
||||
/* FPU error because of denormal */
|
||||
llx = ((long long) hx << 32)
|
||||
| tsk->thread.fpu.hard.fp_regs[n+1];
|
||||
lly = ((long long) hy << 32)
|
||||
| tsk->thread.fpu.hard.fp_regs[m+1];
|
||||
if ((hx & 0x7fffffff) >= 0x00100000)
|
||||
llx = denormal_muld(lly, llx);
|
||||
else
|
||||
llx = denormal_muld(llx, lly);
|
||||
tsk->thread.fpu.hard.fp_regs[n] = llx >> 32;
|
||||
tsk->thread.fpu.hard.fp_regs[n+1] = llx & 0xffffffff;
|
||||
} else if ((fpscr & FPSCR_FPU_ERROR)
|
||||
&& (!prec && ((hx & 0x7fffffff) < 0x00800000
|
||||
|| (hy & 0x7fffffff) < 0x00800000))) {
|
||||
/* FPU error because of denormal */
|
||||
if ((hx & 0x7fffffff) >= 0x00800000)
|
||||
hx = denormal_mulf(hy, hx);
|
||||
else
|
||||
hx = denormal_mulf(hx, hy);
|
||||
tsk->thread.fpu.hard.fp_regs[n] = hx;
|
||||
} else
|
||||
return 0;
|
||||
|
||||
regs->pc = nextpc;
|
||||
return 1;
|
||||
} else if ((finsn & 0xf00e) == 0xf000) { /* fadd, fsub */
|
||||
struct task_struct *tsk = current;
|
||||
int fpscr;
|
||||
int n, m, prec;
|
||||
unsigned int hx, hy;
|
||||
|
||||
n = (finsn >> 8) & 0xf;
|
||||
m = (finsn >> 4) & 0xf;
|
||||
hx = tsk->thread.fpu.hard.fp_regs[n];
|
||||
hy = tsk->thread.fpu.hard.fp_regs[m];
|
||||
fpscr = tsk->thread.fpu.hard.fpscr;
|
||||
prec = fpscr & (1 << 19);
|
||||
|
||||
if ((fpscr & FPSCR_FPU_ERROR)
|
||||
&& (prec && ((hx & 0x7fffffff) < 0x00100000
|
||||
|| (hy & 0x7fffffff) < 0x00100000))) {
|
||||
long long llx, lly;
|
||||
|
||||
/* FPU error because of denormal */
|
||||
llx = ((long long) hx << 32)
|
||||
| tsk->thread.fpu.hard.fp_regs[n+1];
|
||||
lly = ((long long) hy << 32)
|
||||
| tsk->thread.fpu.hard.fp_regs[m+1];
|
||||
if ((finsn & 0xf00f) == 0xf000)
|
||||
llx = denormal_addd(llx, lly);
|
||||
else
|
||||
llx = denormal_addd(llx, lly ^ (1LL << 63));
|
||||
tsk->thread.fpu.hard.fp_regs[n] = llx >> 32;
|
||||
tsk->thread.fpu.hard.fp_regs[n+1] = llx & 0xffffffff;
|
||||
} else if ((fpscr & FPSCR_FPU_ERROR)
|
||||
&& (!prec && ((hx & 0x7fffffff) < 0x00800000
|
||||
|| (hy & 0x7fffffff) < 0x00800000))) {
|
||||
/* FPU error because of denormal */
|
||||
if ((finsn & 0xf00f) == 0xf000)
|
||||
hx = denormal_addf(hx, hy);
|
||||
else
|
||||
hx = denormal_addf(hx, hy ^ 0x80000000);
|
||||
tsk->thread.fpu.hard.fp_regs[n] = hx;
|
||||
} else
|
||||
return 0;
|
||||
|
||||
regs->pc = nextpc;
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
BUILD_TRAP_HANDLER(fpu_error)
|
||||
{
|
||||
struct task_struct *tsk = current;
|
||||
TRAP_HANDLER_DECL;
|
||||
|
||||
save_fpu(tsk, regs);
|
||||
if (ieee_fpe_handler(regs)) {
|
||||
tsk->thread.fpu.hard.fpscr &=
|
||||
~(FPSCR_CAUSE_MASK | FPSCR_FLAG_MASK);
|
||||
grab_fpu(regs);
|
||||
restore_fpu(tsk);
|
||||
set_tsk_thread_flag(tsk, TIF_USEDFPU);
|
||||
return;
|
||||
}
|
||||
|
||||
force_sig(SIGFPE, tsk);
|
||||
}
|
||||
|
||||
BUILD_TRAP_HANDLER(fpu_state_restore)
|
||||
{
|
||||
struct task_struct *tsk = current;
|
||||
TRAP_HANDLER_DECL;
|
||||
|
||||
grab_fpu(regs);
|
||||
if (!user_mode(regs)) {
|
||||
printk(KERN_ERR "BUG: FPU is used in kernel mode.\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (used_math()) {
|
||||
/* Using the FPU again. */
|
||||
restore_fpu(tsk);
|
||||
} else {
|
||||
/* First time FPU user. */
|
||||
fpu_init();
|
||||
set_used_math();
|
||||
}
|
||||
set_tsk_thread_flag(tsk, TIF_USEDFPU);
|
||||
}
|
||||
|
|
@ -36,7 +36,7 @@ ENTRY(exception_handling_table)
|
|||
.long exception_error ! address error store /* 100 */
|
||||
#endif
|
||||
#if defined(CONFIG_SH_FPU)
|
||||
.long do_fpu_error /* 120 */
|
||||
.long fpu_error_trap_handler /* 120 */
|
||||
#else
|
||||
.long exception_error /* 120 */
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -82,8 +82,8 @@ save_fpu(struct task_struct *tsk, struct pt_regs *regs)
|
|||
"r" (FPSCR_INIT)
|
||||
: "memory");
|
||||
|
||||
disable_fpu();
|
||||
release_fpu(regs);
|
||||
disable_fpu();
|
||||
release_fpu(regs);
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
@ -91,7 +91,7 @@ restore_fpu(struct task_struct *tsk)
|
|||
{
|
||||
unsigned long dummy;
|
||||
|
||||
enable_fpu();
|
||||
enable_fpu();
|
||||
asm volatile("lds %2, fpscr\n\t"
|
||||
"fmov.s @%0+, fr0\n\t"
|
||||
"fmov.s @%0+, fr1\n\t"
|
||||
|
|
@ -138,7 +138,7 @@ restore_fpu(struct task_struct *tsk)
|
|||
/*
|
||||
* Load the FPU with signalling NANS. This bit pattern we're using
|
||||
* has the property that no matter wether considered as single or as
|
||||
* double precision represents signaling NANS.
|
||||
* double precision represents signaling NANS.
|
||||
*/
|
||||
|
||||
static void
|
||||
|
|
@ -184,7 +184,7 @@ fpu_init(void)
|
|||
"lds %2, fpscr\n\t"
|
||||
: /* no output */
|
||||
: "r" (0), "r" (FPSCR_RCHG), "r" (FPSCR_INIT));
|
||||
disable_fpu();
|
||||
disable_fpu();
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -238,7 +238,6 @@ ieee_fpe_handler (struct pt_regs *regs)
|
|||
if (nib[0] == 0xb ||
|
||||
(nib[0] == 0x4 && nib[2] == 0x0 && nib[3] == 0xb)) /* bsr & jsr */
|
||||
regs->pr = regs->pc + 4;
|
||||
|
||||
if (nib[0] == 0xa || nib[0] == 0xb) { /* bra & bsr */
|
||||
nextpc = regs->pc + 4 + ((short) ((insn & 0xfff) << 4) >> 3);
|
||||
finsn = *(unsigned short *) (regs->pc + 2);
|
||||
|
|
@ -293,12 +292,10 @@ ieee_fpe_handler (struct pt_regs *regs)
|
|||
return 0;
|
||||
}
|
||||
|
||||
asmlinkage void
|
||||
do_fpu_error(unsigned long r4, unsigned long r5, unsigned long r6,
|
||||
unsigned long r7, struct pt_regs __regs)
|
||||
BUILD_TRAP_HANDLER(fpu_error)
|
||||
{
|
||||
struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
|
||||
struct task_struct *tsk = current;
|
||||
TRAP_HANDLER_DECL;
|
||||
|
||||
if (ieee_fpe_handler(regs))
|
||||
return;
|
||||
|
|
@ -308,12 +305,10 @@ do_fpu_error(unsigned long r4, unsigned long r5, unsigned long r6,
|
|||
force_sig(SIGFPE, tsk);
|
||||
}
|
||||
|
||||
asmlinkage void
|
||||
do_fpu_state_restore(unsigned long r4, unsigned long r5, unsigned long r6,
|
||||
unsigned long r7, struct pt_regs __regs)
|
||||
BUILD_TRAP_HANDLER(fpu_state_restore)
|
||||
{
|
||||
struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
|
||||
struct task_struct *tsk = current;
|
||||
TRAP_HANDLER_DECL;
|
||||
|
||||
grab_fpu(regs);
|
||||
if (!user_mode(regs)) {
|
||||
|
|
|
|||
|
|
@ -662,11 +662,6 @@ asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
|
|||
}
|
||||
#endif
|
||||
|
||||
/* arch/sh/kernel/cpu/sh4/fpu.c */
|
||||
extern int do_fpu_inst(unsigned short, struct pt_regs *);
|
||||
extern asmlinkage void do_fpu_state_restore(unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7, struct pt_regs __regs);
|
||||
|
||||
asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
|
||||
unsigned long r6, unsigned long r7,
|
||||
struct pt_regs __regs)
|
||||
|
|
@ -853,11 +848,11 @@ void __init trap_init(void)
|
|||
set_exception_table_evt(0x820, do_illegal_slot_inst);
|
||||
#elif defined(CONFIG_SH_FPU)
|
||||
#ifdef CONFIG_CPU_SUBTYPE_SHX3
|
||||
set_exception_table_evt(0xd80, do_fpu_state_restore);
|
||||
set_exception_table_evt(0xda0, do_fpu_state_restore);
|
||||
set_exception_table_evt(0xd80, fpu_state_restore_trap_handler);
|
||||
set_exception_table_evt(0xda0, fpu_state_restore_trap_handler);
|
||||
#else
|
||||
set_exception_table_evt(0x800, do_fpu_state_restore);
|
||||
set_exception_table_evt(0x820, do_fpu_state_restore);
|
||||
set_exception_table_evt(0x800, fpu_state_restore_trap_handler);
|
||||
set_exception_table_evt(0x820, fpu_state_restore_trap_handler);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -26,6 +26,8 @@ extern void save_fpu(struct task_struct *__tsk, struct pt_regs *regs);
|
|||
#define save_fpu(tsk, regs) do { } while (0)
|
||||
#endif
|
||||
|
||||
extern int do_fpu_inst(unsigned short, struct pt_regs *);
|
||||
|
||||
#define unlazy_fpu(tsk, regs) do { \
|
||||
if (test_tsk_thread_flag(tsk, TIF_USEDFPU)) { \
|
||||
save_fpu(tsk, regs); \
|
||||
|
|
|
|||
|
|
@ -25,7 +25,8 @@ struct sigcontext {
|
|||
unsigned long sc_mach;
|
||||
unsigned long sc_macl;
|
||||
|
||||
#if defined(__SH4__) || defined(CONFIG_CPU_SH4)
|
||||
#if defined(__SH4__) || defined(CONFIG_CPU_SH4) || \
|
||||
defined(__SH2A__) || defined(CONFIG_CPU_SH2A)
|
||||
/* FPU registers */
|
||||
unsigned long sc_fpregs[16];
|
||||
unsigned long sc_xfpregs[16];
|
||||
|
|
|
|||
|
|
@ -205,6 +205,8 @@ asmlinkage void name##_trap_handler(unsigned int vec, struct pt_regs *regs)
|
|||
BUILD_TRAP_HANDLER(address_error);
|
||||
BUILD_TRAP_HANDLER(debug);
|
||||
BUILD_TRAP_HANDLER(bug);
|
||||
BUILD_TRAP_HANDLER(fpu_error);
|
||||
BUILD_TRAP_HANDLER(fpu_state_restore);
|
||||
|
||||
#define arch_align_stack(x) (x)
|
||||
|
||||
|
|
|
|||
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