drm/i915: framebuffer compression for GM45+
Add support for framebuffer compression on GM45 and above. Removes some unnecessary I915_HAS_FBC checks as well (this is now part of the FBC display function). Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Jesse Barnes
Eric Anholt
Родитель
e70236a8d3
Коммит
74dff28223
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@ -1119,34 +1119,47 @@ static void i915_setup_compression(struct drm_device *dev, int size)
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return;
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}
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compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096, 4096, 0);
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if (!compressed_llb) {
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i915_warn_stolen(dev);
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return;
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cfb_base = i915_gtt_to_phys(dev, compressed_fb->start);
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if (!cfb_base) {
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DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
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drm_mm_put_block(compressed_fb);
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}
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compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096);
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if (!compressed_llb) {
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i915_warn_stolen(dev);
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return;
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if (!IS_GM45(dev)) {
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compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096,
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4096, 0);
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if (!compressed_llb) {
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i915_warn_stolen(dev);
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return;
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}
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compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096);
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if (!compressed_llb) {
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i915_warn_stolen(dev);
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return;
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}
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ll_base = i915_gtt_to_phys(dev, compressed_llb->start);
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if (!ll_base) {
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DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
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drm_mm_put_block(compressed_fb);
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drm_mm_put_block(compressed_llb);
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}
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}
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dev_priv->cfb_size = size;
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cfb_base = i915_gtt_to_phys(dev, compressed_fb->start);
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ll_base = i915_gtt_to_phys(dev, compressed_llb->start);
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if (!cfb_base || !ll_base) {
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DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
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drm_mm_put_block(compressed_fb);
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drm_mm_put_block(compressed_llb);
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if (IS_GM45(dev)) {
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g4x_disable_fbc(dev);
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I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
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} else {
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i8xx_disable_fbc(dev);
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I915_WRITE(FBC_CFB_BASE, cfb_base);
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I915_WRITE(FBC_LL_BASE, ll_base);
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}
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i8xx_disable_fbc(dev);
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DRM_DEBUG("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
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ll_base, size >> 20);
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I915_WRITE(FBC_CFB_BASE, cfb_base);
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I915_WRITE(FBC_LL_BASE, ll_base);
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}
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static int i915_load_modeset_init(struct drm_device *dev,
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@ -1194,7 +1207,7 @@ static int i915_load_modeset_init(struct drm_device *dev,
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goto out;
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/* Try to set up FBC with a reasonable compressed buffer size */
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if (IS_MOBILE(dev) && (IS_I9XX(dev) || IS_I965G(dev)) &&
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if (IS_MOBILE(dev) && (IS_I9XX(dev) || IS_I965G(dev) || IS_GM45(dev)) &&
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i915_powersave) {
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int cfb_size;
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@ -827,6 +827,7 @@ static inline void opregion_enable_asle(struct drm_device *dev) { return; }
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extern void intel_modeset_init(struct drm_device *dev);
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extern void intel_modeset_cleanup(struct drm_device *dev);
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extern void i8xx_disable_fbc(struct drm_device *dev);
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extern void g4x_disable_fbc(struct drm_device *dev);
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/**
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* Lock test for when it's just for synchronization of ring access.
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@ -351,6 +351,33 @@
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#define FBC_LL_SIZE (1536)
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/* Framebuffer compression for GM45+ */
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#define DPFC_CB_BASE 0x3200
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#define DPFC_CONTROL 0x3208
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#define DPFC_CTL_EN (1<<31)
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#define DPFC_CTL_PLANEA (0<<30)
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#define DPFC_CTL_PLANEB (1<<30)
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#define DPFC_CTL_FENCE_EN (1<<29)
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#define DPFC_SR_EN (1<<10)
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#define DPFC_CTL_LIMIT_1X (0<<6)
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#define DPFC_CTL_LIMIT_2X (1<<6)
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#define DPFC_CTL_LIMIT_4X (2<<6)
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#define DPFC_RECOMP_CTL 0x320c
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#define DPFC_RECOMP_STALL_EN (1<<27)
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#define DPFC_RECOMP_STALL_WM_SHIFT (16)
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#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
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#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
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#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
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#define DPFC_STATUS 0x3210
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#define DPFC_INVAL_SEG_SHIFT (16)
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#define DPFC_INVAL_SEG_MASK (0x07ff0000)
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#define DPFC_COMP_SEG_SHIFT (0)
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#define DPFC_COMP_SEG_MASK (0x000003ff)
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#define DPFC_STATUS2 0x3214
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#define DPFC_FENCE_YOFF 0x3218
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#define DPFC_CHICKEN 0x3224
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#define DPFC_HT_MODIFY (1<<31)
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/*
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* GPIO regs
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*/
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@ -1030,6 +1030,65 @@ static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
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return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
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}
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static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_framebuffer *fb = crtc->fb;
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struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
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struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
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DPFC_CTL_PLANEB);
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unsigned long stall_watermark = 200;
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u32 dpfc_ctl;
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dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
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dev_priv->cfb_fence = obj_priv->fence_reg;
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dev_priv->cfb_plane = intel_crtc->plane;
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dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
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if (obj_priv->tiling_mode != I915_TILING_NONE) {
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dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
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I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
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} else {
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I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
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}
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I915_WRITE(DPFC_CONTROL, dpfc_ctl);
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I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
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(stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
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(interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
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I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
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/* enable it... */
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I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
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DRM_DEBUG("enabled fbc on plane %d\n", intel_crtc->plane);
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}
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void g4x_disable_fbc(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 dpfc_ctl;
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/* Disable compression */
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dpfc_ctl = I915_READ(DPFC_CONTROL);
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dpfc_ctl &= ~DPFC_CTL_EN;
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I915_WRITE(DPFC_CONTROL, dpfc_ctl);
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intel_wait_for_vblank(dev);
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DRM_DEBUG("disabled FBC\n");
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}
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static bool g4x_fbc_enabled(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
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}
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/**
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* intel_update_fbc - enable/disable FBC as needed
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* @crtc: CRTC to point the compressor at
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@ -1097,7 +1156,7 @@ static void intel_update_fbc(struct drm_crtc *crtc,
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DRM_DEBUG("mode too large for compression, disabling\n");
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goto out_disable;
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}
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if (IS_I9XX(dev) && plane != 0) {
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if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
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DRM_DEBUG("plane not 0, disabling compression\n");
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goto out_disable;
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}
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@ -1265,7 +1324,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
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I915_READ(dspbase);
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}
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if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0))
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if ((IS_I965G(dev) || plane == 0))
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intel_update_fbc(crtc, &crtc->mode);
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intel_wait_for_vblank(dev);
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@ -1774,7 +1833,8 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
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intel_crtc_load_lut(crtc);
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intel_update_fbc(crtc, &crtc->mode);
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if ((IS_I965G(dev) || plane == 0))
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intel_update_fbc(crtc, &crtc->mode);
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/* Give the overlay scaler a chance to enable if it's on this pipe */
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//intel_crtc_dpms_video(crtc, true); TODO
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@ -2988,7 +3048,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
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/* Flush the plane changes */
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ret = intel_pipe_set_base(crtc, x, y, old_fb);
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intel_update_fbc(crtc, &crtc->mode);
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if ((IS_I965G(dev) || plane == 0))
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intel_update_fbc(crtc, &crtc->mode);
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intel_update_watermarks(dev);
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@ -3121,7 +3182,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
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drm_gem_object_unreference(intel_crtc->cursor_bo);
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}
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if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0))
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if ((IS_I965G(dev) || plane == 0))
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intel_update_fbc(crtc, &crtc->mode);
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mutex_unlock(&dev->struct_mutex);
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@ -4108,12 +4169,16 @@ static void intel_init_display(struct drm_device *dev)
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/* Only mobile has FBC, leave pointers NULL for other chips */
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if (IS_MOBILE(dev)) {
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/* 855GM needs testing */
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if (IS_I965GM(dev) || IS_I945GM(dev) || IS_I915GM(dev)) {
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if (IS_GM45(dev)) {
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dev_priv->display.fbc_enabled = g4x_fbc_enabled;
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dev_priv->display.enable_fbc = g4x_enable_fbc;
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dev_priv->display.disable_fbc = g4x_disable_fbc;
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} else if (IS_I965GM(dev) || IS_I945GM(dev) || IS_I915GM(dev)) {
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dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
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dev_priv->display.enable_fbc = i8xx_enable_fbc;
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dev_priv->display.disable_fbc = i8xx_disable_fbc;
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}
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/* 855GM needs testing */
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}
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/* Returns the core display clock speed */
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