ARM: at91: remove no-MMU at91x40 support
As there is currently no-one to take care of this old !MMU target and as its support in recent kernels is a bit rotten, remove this at91x40 support and the board file associated with it (at91eb01). There are modern ARM !MMU in Mainline now so this target is not interesting for building tests anymore. It would be better to start from these modern ARM !MMU platforms to reintroduce at91x40 support if needed. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
This commit is contained in:
Nicolas Ferre
Родитель
cac7f24298
Коммит
7538ec7d1e
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@ -1,48 +0,0 @@
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CONFIG_EXPERIMENTAL=y
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CONFIG_LOG_BUF_SHIFT=14
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CONFIG_EMBEDDED=y
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# CONFIG_HOTPLUG is not set
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# CONFIG_ELF_CORE is not set
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# CONFIG_FUTEX is not set
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# CONFIG_TIMERFD is not set
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# CONFIG_VM_EVENT_COUNTERS is not set
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# CONFIG_COMPAT_BRK is not set
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CONFIG_SLAB=y
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# CONFIG_LBDAF is not set
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# CONFIG_BLK_DEV_BSG is not set
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# CONFIG_IOSCHED_DEADLINE is not set
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# CONFIG_IOSCHED_CFQ is not set
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# CONFIG_MMU is not set
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CONFIG_ARCH_AT91=y
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CONFIG_ARCH_AT91X40=y
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CONFIG_MACH_AT91EB01=y
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CONFIG_AT91_EARLY_USART0=y
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CONFIG_CPU_ARM7TDMI=y
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CONFIG_SET_MEM_PARAM=y
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CONFIG_DRAM_BASE=0x01000000
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CONFIG_DRAM_SIZE=0x00400000
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CONFIG_FLASH_MEM_BASE=0x01400000
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CONFIG_PROCESSOR_ID=0x14000040
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CONFIG_ZBOOT_ROM_TEXT=0x0
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CONFIG_ZBOOT_ROM_BSS=0x0
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CONFIG_BINFMT_FLAT=y
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# CONFIG_SUSPEND is not set
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# CONFIG_FW_LOADER is not set
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CONFIG_MTD=y
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CONFIG_MTD_PARTITIONS=y
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CONFIG_MTD_CHAR=y
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CONFIG_MTD_BLOCK=y
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CONFIG_MTD_RAM=y
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CONFIG_MTD_ROM=y
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CONFIG_BLK_DEV_RAM=y
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# CONFIG_INPUT is not set
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# CONFIG_SERIO is not set
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# CONFIG_VT is not set
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# CONFIG_DEVKMEM is not set
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# CONFIG_HW_RANDOM is not set
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# CONFIG_HWMON is not set
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# CONFIG_USB_SUPPORT is not set
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CONFIG_EXT2_FS=y
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# CONFIG_DNOTIFY is not set
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CONFIG_ROMFS_FS=y
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# CONFIG_ENABLE_MUST_CHECK is not set
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@ -18,18 +18,14 @@ config HAVE_AT91_DBGU2
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config AT91_USE_OLD_CLK
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bool
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config AT91_PMC_UNIT
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bool
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default !ARCH_AT91X40
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config COMMON_CLK_AT91
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bool
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default AT91_PMC_UNIT && USE_OF && !AT91_USE_OLD_CLK
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default USE_OF && !AT91_USE_OLD_CLK
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select COMMON_CLK
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config OLD_CLK_AT91
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bool
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default AT91_PMC_UNIT && AT91_USE_OLD_CLK
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default AT91_USE_OLD_CLK
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config OLD_IRQ_AT91
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bool
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@ -65,16 +61,6 @@ choice
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prompt "Core type"
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config ARCH_AT91X40
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bool "ARM7 AT91X40"
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depends on !MMU
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select CPU_ARM7TDMI
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select ARCH_USES_GETTIMEOFFSET
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select OLD_IRQ_AT91
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help
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Select this if you are using one of Atmel's AT91X40 SoC.
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config SOC_SAM_V4_V5
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bool "ARM9 AT91SAM9/AT91RM9200"
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help
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@ -199,7 +185,7 @@ config SOC_AT91SAM9N12
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endif # SOC_SAM_V4_V5
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if SOC_SAM_V4_V5 || ARCH_AT91X40
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if SOC_SAM_V4_V5
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source arch/arm/mach-at91/Kconfig.non_dt
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endif
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@ -5,7 +5,6 @@ config HAVE_AT91_DATAFLASH_CARD
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choice
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prompt "Atmel AT91 Processor Devices for non DT boards"
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depends on !ARCH_AT91X40
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config ARCH_AT91_NONE
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bool "None"
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@ -317,22 +316,6 @@ endif
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# ----------------------------------------------------------
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if ARCH_AT91X40
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comment "AT91X40 Board Type"
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config MACH_AT91EB01
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bool "Atmel AT91EB01 Evaluation Kit"
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help
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Select this if you are using Atmel's AT91EB01 Evaluation Kit.
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It is also a popular target for simulators such as GDB's
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ARM simulator (commonly known as the ARMulator) and the
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Skyeye simulator.
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endif
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# ----------------------------------------------------------
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comment "AT91 Board Options"
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config MTD_AT91_DATAFLASH_CARD
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@ -26,7 +26,6 @@ obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261_devices.o
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obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263_devices.o
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obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl_devices.o
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obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45_devices.o
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obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o
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# AT91RM9200 board-specific support
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obj-$(CONFIG_MACH_ONEARM) += board-1arm.o
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@ -82,9 +81,6 @@ obj-$(CONFIG_MACH_AT91SAM9_DT) += board-dt-sam9.o
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# SAMA5 board with device-tree
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obj-$(CONFIG_MACH_SAMA5_DT) += board-dt-sama5.o
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# AT91X40 board-specific support
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obj-$(CONFIG_MACH_AT91EB01) += board-eb01.o
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# Drivers
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obj-y += leds.o
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@ -1,93 +0,0 @@
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/*
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* arch/arm/mach-at91/at91x40.c
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*
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* (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com>
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* Copyright (C) 2005 SAN People
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/proc-fns.h>
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#include <asm/system_misc.h>
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#include <asm/mach/arch.h>
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#include <mach/at91x40.h>
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#include <mach/at91_st.h>
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#include <mach/hardware.h>
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#include "at91_aic.h"
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#include "generic.h"
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/*
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* Export the clock functions for the AT91X40. Some external code common
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* to all AT91 family parts relys on this, like the gpio and serial support.
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*/
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int clk_enable(struct clk *clk)
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{
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return 0;
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}
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void clk_disable(struct clk *clk)
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{
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}
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unsigned long clk_get_rate(struct clk *clk)
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{
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return AT91X40_MASTER_CLOCK;
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}
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static void at91x40_idle(void)
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{
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/*
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* Disable the processor clock. The processor will be automatically
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* re-enabled by an interrupt or by a reset.
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*/
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__raw_writel(AT91_PS_CR_CPU, AT91_IO_P2V(AT91_PS_CR));
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cpu_do_idle();
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}
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void __init at91x40_initialize(unsigned long main_clock)
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{
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arm_pm_idle = at91x40_idle;
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}
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/*
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* The default interrupt priority levels (0 = lowest, 7 = highest).
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*/
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static unsigned int at91x40_default_irq_priority[NR_AIC_IRQS] __initdata = {
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7, /* Advanced Interrupt Controller (FIQ) */
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0, /* System Peripherals */
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0, /* USART 0 */
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0, /* USART 1 */
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2, /* Timer Counter 0 */
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2, /* Timer Counter 1 */
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2, /* Timer Counter 2 */
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0, /* Watchdog timer */
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0, /* Parallel IO Controller A */
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0, /* Reserved */
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0, /* Reserved */
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0, /* Reserved */
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0, /* Reserved */
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0, /* Reserved */
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0, /* Reserved */
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0, /* Reserved */
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0, /* External IRQ0 */
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0, /* External IRQ1 */
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0, /* External IRQ2 */
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};
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void __init at91x40_init_interrupts(unsigned int priority[NR_AIC_IRQS])
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{
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u32 extern_irq = (1 << AT91X40_ID_IRQ0) | (1 << AT91X40_ID_IRQ1)
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| (1 << AT91X40_ID_IRQ2);
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if (!priority)
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priority = at91x40_default_irq_priority;
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at91_aic_init(priority, extern_irq);
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}
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@ -1,85 +0,0 @@
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/*
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* arch/arm/mach-at91/at91x40_time.c
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*
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* (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com>
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*
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||||
* This program is free software; you can redistribute it and/or modify
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||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/time.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <mach/at91x40.h>
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#include <asm/mach/time.h>
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#include "at91_tc.h"
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#define at91_tc_read(field) \
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__raw_readl(AT91_IO_P2V(AT91_TC) + field)
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#define at91_tc_write(field, value) \
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__raw_writel(value, AT91_IO_P2V(AT91_TC) + field)
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/*
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* 3 counter/timer units present.
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*/
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#define AT91_TC_CLK0BASE 0
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#define AT91_TC_CLK1BASE 0x40
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#define AT91_TC_CLK2BASE 0x80
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static u32 at91x40_gettimeoffset(void)
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{
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return (at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 /
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(AT91X40_MASTER_CLOCK / 128)) * 1000;
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}
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static irqreturn_t at91x40_timer_interrupt(int irq, void *dev_id)
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{
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at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_SR);
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timer_tick();
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return IRQ_HANDLED;
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}
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static struct irqaction at91x40_timer_irq = {
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.name = "at91_tick",
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.flags = IRQF_TIMER,
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.handler = at91x40_timer_interrupt
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};
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void __init at91x40_timer_init(void)
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{
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unsigned int v;
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arch_gettimeoffset = at91x40_gettimeoffset;
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at91_tc_write(AT91_TC_BCR, 0);
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v = at91_tc_read(AT91_TC_BMR);
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v = (v & ~AT91_TC_TC1XC1S) | AT91_TC_TC1XC1S_NONE;
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at91_tc_write(AT91_TC_BMR, v);
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at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, AT91_TC_CLKDIS);
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at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CMR, (AT91_TC_TIMER_CLOCK4 | AT91_TC_CPCTRG));
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at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IDR, 0xffffffff);
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at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_RC, (AT91X40_MASTER_CLOCK / 128) / HZ - 1);
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at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IER, (1<<4));
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setup_irq(AT91X40_ID_TC1, &at91x40_timer_irq);
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at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN));
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}
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@ -1,52 +0,0 @@
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/*
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* arch/arm/mach-at91/board-eb01.c
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*
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* (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/irq.h>
|
||||
#include <asm/mach-types.h>
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#include <mach/hardware.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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|
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#include "at91_aic.h"
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||||
#include "board.h"
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#include "generic.h"
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static void __init at91eb01_init_irq(void)
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||||
{
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at91x40_init_interrupts(NULL);
|
||||
}
|
||||
|
||||
static void __init at91eb01_init_early(void)
|
||||
{
|
||||
at91x40_initialize(40000000);
|
||||
}
|
||||
|
||||
MACHINE_START(AT91EB01, "Atmel AT91 EB01")
|
||||
/* Maintainer: Greg Ungerer <gerg@snapgear.com> */
|
||||
.init_time = at91x40_timer_init,
|
||||
.handle_irq = at91_aic_handle_irq,
|
||||
.init_early = at91eb01_init_early,
|
||||
.init_irq = at91eb01_init_irq,
|
||||
MACHINE_END
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||||
|
||||
|
|
@ -24,14 +24,12 @@ extern void __init at91_init_sram(int bank, unsigned long base,
|
|||
/* Processors */
|
||||
extern void __init at91rm9200_set_type(int type);
|
||||
extern void __init at91_initialize(unsigned long main_clock);
|
||||
extern void __init at91x40_initialize(unsigned long main_clock);
|
||||
extern void __init at91rm9200_dt_initialize(void);
|
||||
extern void __init at91_dt_initialize(void);
|
||||
|
||||
/* Interrupts */
|
||||
extern void __init at91_init_irq_default(void);
|
||||
extern void __init at91_init_interrupts(unsigned int priority[]);
|
||||
extern void __init at91x40_init_interrupts(unsigned int priority[]);
|
||||
extern void __init at91_aic_init(unsigned int priority[],
|
||||
unsigned int ext_irq_mask);
|
||||
extern int __init at91_aic_of_init(struct device_node *node,
|
||||
|
|
@ -50,7 +48,6 @@ extern void at91rm9200_ioremap_st(u32 addr);
|
|||
extern void at91rm9200_timer_init(void);
|
||||
extern void at91sam926x_ioremap_pit(u32 addr);
|
||||
extern void at91sam926x_pit_init(int irq);
|
||||
extern void at91x40_timer_init(void);
|
||||
|
||||
/* Clocks */
|
||||
#ifdef CONFIG_OLD_CLK_AT91
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@
|
|||
#ifndef AT91_DBGU_H
|
||||
#define AT91_DBGU_H
|
||||
|
||||
#if !defined(CONFIG_ARCH_AT91X40)
|
||||
#define AT91_DBGU_CR (0x00) /* Control Register */
|
||||
#define AT91_DBGU_MR (0x04) /* Mode Register */
|
||||
#define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */
|
||||
|
|
@ -34,8 +33,6 @@
|
|||
#define AT91_DBGU_FNR (0x48) /* Force NTRST Register [SAM9 only] */
|
||||
#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */
|
||||
|
||||
#endif /* AT91_DBGU */
|
||||
|
||||
/*
|
||||
* Some AT91 parts that don't have full DEBUG units still support the ID
|
||||
* and extensions register.
|
||||
|
|
|
|||
|
|
@ -1,60 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-at91/include/mach/at91x40.h
|
||||
*
|
||||
* (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91X40_H
|
||||
#define AT91X40_H
|
||||
|
||||
/*
|
||||
* IRQ list.
|
||||
*/
|
||||
#define AT91X40_ID_USART0 2 /* USART port 0 */
|
||||
#define AT91X40_ID_USART1 3 /* USART port 1 */
|
||||
#define AT91X40_ID_TC0 4 /* Timer/Counter 0 */
|
||||
#define AT91X40_ID_TC1 5 /* Timer/Counter 1*/
|
||||
#define AT91X40_ID_TC2 6 /* Timer/Counter 2*/
|
||||
#define AT91X40_ID_WD 7 /* Watchdog? */
|
||||
#define AT91X40_ID_PIOA 8 /* Parallel IO Controller A */
|
||||
|
||||
#define AT91X40_ID_IRQ0 16 /* External IRQ 0 */
|
||||
#define AT91X40_ID_IRQ1 17 /* External IRQ 1 */
|
||||
#define AT91X40_ID_IRQ2 18 /* External IRQ 2 */
|
||||
|
||||
/*
|
||||
* System Peripherals
|
||||
*/
|
||||
#define AT91_BASE_SYS 0xffc00000
|
||||
|
||||
#define AT91_EBI 0xffe00000 /* External Bus Interface */
|
||||
#define AT91_SF 0xfff00000 /* Special Function */
|
||||
#define AT91_USART1 0xfffcc000 /* USART 1 */
|
||||
#define AT91_USART0 0xfffd0000 /* USART 0 */
|
||||
#define AT91_TC 0xfffe0000 /* Timer Counter */
|
||||
#define AT91_PIOA 0xffff0000 /* PIO Controller A */
|
||||
#define AT91_PS 0xffff4000 /* Power Save */
|
||||
#define AT91_WD 0xffff8000 /* Watchdog Timer */
|
||||
|
||||
/*
|
||||
* The AT91x40 series doesn't have a debug unit like the other AT91 parts.
|
||||
* But it does have a chip identify register and extension ID, so define at
|
||||
* least these here.
|
||||
*/
|
||||
#define AT91_DBGU_CIDR (AT91_SF + 0) /* CIDR in PS segment */
|
||||
#define AT91_DBGU_EXID (AT91_SF + 4) /* EXID in PS segment */
|
||||
|
||||
/*
|
||||
* Support defines for the simple Power Controller module.
|
||||
*/
|
||||
#define AT91_PS_CR (AT91_PS + 0) /* PS Control register */
|
||||
#define AT91_PS_CR_CPU (1 << 0) /* CPU clock disable bit */
|
||||
|
||||
#define AT91X40_MASTER_CLOCK 40000000
|
||||
|
||||
#endif /* AT91X40_H */
|
||||
|
|
@ -62,7 +62,6 @@
|
|||
#define ARCH_EXID_SAMA5D43 0x00000003
|
||||
#define ARCH_EXID_SAMA5D44 0x00000004
|
||||
|
||||
#define ARCH_FAMILY_AT91X92 0x09200000
|
||||
#define ARCH_FAMILY_AT91SAM9 0x01900000
|
||||
#define ARCH_FAMILY_AT91SAM9XE 0x02900000
|
||||
|
||||
|
|
|
|||
|
|
@ -24,9 +24,6 @@
|
|||
/* sama5d4 */
|
||||
#define AT91_BASE_DBGU2 0xfc069000
|
||||
|
||||
#if defined(CONFIG_ARCH_AT91X40)
|
||||
#include <mach/at91x40.h>
|
||||
#else
|
||||
#include <mach/at91rm9200.h>
|
||||
#include <mach/at91sam9260.h>
|
||||
#include <mach/at91sam9261.h>
|
||||
|
|
@ -51,8 +48,6 @@
|
|||
*/
|
||||
#define AT91_BASE_SYS 0xffffc000
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* On sama5d4 there is no system controller, we map some needed peripherals
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -31,7 +31,6 @@
|
|||
|
||||
void __iomem *at91_uart;
|
||||
|
||||
#if !defined(CONFIG_ARCH_AT91X40)
|
||||
static const u32 uarts_rm9200[] = {
|
||||
AT91_BASE_DBGU0,
|
||||
AT91RM9200_BASE_US0,
|
||||
|
|
@ -188,12 +187,6 @@ static inline void arch_decomp_setup(void)
|
|||
|
||||
at91_uart = NULL;
|
||||
}
|
||||
#else
|
||||
static inline void arch_decomp_setup(void)
|
||||
{
|
||||
at91_uart = NULL;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The following code assumes the serial port has already been
|
||||
|
|
|
|||
|
|
@ -418,7 +418,7 @@ void __init at91_ioremap_matrix(u32 base_addr)
|
|||
panic(pr_fmt("Impossible to ioremap at91_matrix_base\n"));
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF) && !defined(CONFIG_ARCH_AT91X40)
|
||||
#if defined(CONFIG_OF)
|
||||
static struct of_device_id ramc_ids[] = {
|
||||
{ .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
|
||||
{ .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
|
||||
|
|
|
|||
|
|
@ -1110,7 +1110,7 @@ config RTC_DRV_AT91RM9200
|
|||
|
||||
config RTC_DRV_AT91SAM9
|
||||
tristate "AT91SAM9x/AT91CAP9 RTT as RTC"
|
||||
depends on ARCH_AT91 && !(ARCH_AT91RM9200 || ARCH_AT91X40)
|
||||
depends on ARCH_AT91 && !ARCH_AT91RM9200
|
||||
help
|
||||
RTC driver for the Atmel AT91SAM9x and AT91CAP9 internal RTT
|
||||
(Real Time Timer). These timers are powered by the backup power
|
||||
|
|
|
|||
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