IOMMU Fixes for Linux v3.17-rc4
Including:
* Two fixes for issues found by Coverity
* Various fixes for the ARM SMMU driver
* A warning fix for the FSL PAMU driver
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Merge tag 'iommu-fixes-v3.17-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull iommu fixes from Joerg Roedel:
- two fixes for issues found by Coverity
- various fixes for the ARM SMMU driver
- a warning fix for the FSL PAMU driver
* tag 'iommu-fixes-v3.17-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu:
iommu/fsl: Fix warning resulting from adding PCI device twice
iommu/arm-smmu: fix corner cases in address size calculations
iommu/arm-smmu: fix decimal printf format specifiers prefixed with 0x
iommu/arm-smmu: Do not access non-existing S2CR registers
iommu/arm-smmu: fix s2cr and smr teardown on device detach from domain
iommu/arm-smmu: remove pgtable_page_{c,d}tor()
iommu/arm-smmu: fix programming of SMMU_CBn_TCR for stage 1
iommu/arm-smmu: avoid calling request_irq in atomic context
iommu/vt-d: Check return value of acpi_bus_get_device()
iommu/core: Make iommu_group_get_for_dev() more robust
This commit is contained in:
Linus Torvalds
Коммит
753a6cb7e4
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@ -146,6 +146,8 @@
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#define ID0_CTTW (1 << 14)
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#define ID0_NUMIRPT_SHIFT 16
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#define ID0_NUMIRPT_MASK 0xff
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#define ID0_NUMSIDB_SHIFT 9
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#define ID0_NUMSIDB_MASK 0xf
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#define ID0_NUMSMRG_SHIFT 0
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#define ID0_NUMSMRG_MASK 0xff
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@ -524,9 +526,18 @@ static int register_smmu_master(struct arm_smmu_device *smmu,
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master->of_node = masterspec->np;
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master->cfg.num_streamids = masterspec->args_count;
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for (i = 0; i < master->cfg.num_streamids; ++i)
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master->cfg.streamids[i] = masterspec->args[i];
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for (i = 0; i < master->cfg.num_streamids; ++i) {
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u16 streamid = masterspec->args[i];
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if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) &&
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(streamid >= smmu->num_mapping_groups)) {
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dev_err(dev,
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"stream ID for master device %s greater than maximum allowed (%d)\n",
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masterspec->np->name, smmu->num_mapping_groups);
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return -ERANGE;
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}
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master->cfg.streamids[i] = streamid;
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}
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return insert_smmu_master(smmu, master);
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}
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@ -623,7 +634,7 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
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if (fsr & FSR_IGN)
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dev_err_ratelimited(smmu->dev,
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"Unexpected context fault (fsr 0x%u)\n",
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"Unexpected context fault (fsr 0x%x)\n",
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fsr);
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fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
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@ -752,6 +763,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
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reg = (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT);
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break;
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case 39:
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case 40:
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reg = (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT);
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break;
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case 42:
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@ -773,6 +785,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
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reg |= (TTBCR2_ADDR_36 << TTBCR2_PASIZE_SHIFT);
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break;
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case 39:
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case 40:
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reg |= (TTBCR2_ADDR_40 << TTBCR2_PASIZE_SHIFT);
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break;
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case 42:
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@ -843,8 +856,11 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
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reg |= TTBCR_EAE |
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(TTBCR_SH_IS << TTBCR_SH0_SHIFT) |
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(TTBCR_RGN_WBWA << TTBCR_ORGN0_SHIFT) |
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(TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT) |
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(TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT);
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(TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT);
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if (!stage1)
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reg |= (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT);
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writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
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/* MAIR0 (stage-1 only) */
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@ -868,10 +884,15 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
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static int arm_smmu_init_domain_context(struct iommu_domain *domain,
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struct arm_smmu_device *smmu)
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{
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int irq, ret, start;
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int irq, start, ret = 0;
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unsigned long flags;
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struct arm_smmu_domain *smmu_domain = domain->priv;
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struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
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spin_lock_irqsave(&smmu_domain->lock, flags);
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if (smmu_domain->smmu)
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goto out_unlock;
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if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) {
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/*
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* We will likely want to change this if/when KVM gets
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@ -890,7 +911,7 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,
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ret = __arm_smmu_alloc_bitmap(smmu->context_map, start,
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smmu->num_context_banks);
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if (IS_ERR_VALUE(ret))
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return ret;
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goto out_unlock;
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cfg->cbndx = ret;
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if (smmu->version == 1) {
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@ -900,6 +921,10 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,
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cfg->irptndx = cfg->cbndx;
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}
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ACCESS_ONCE(smmu_domain->smmu) = smmu;
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arm_smmu_init_context_bank(smmu_domain);
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spin_unlock_irqrestore(&smmu_domain->lock, flags);
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irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
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ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED,
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"arm-smmu-context-fault", domain);
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@ -907,15 +932,12 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain,
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dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n",
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cfg->irptndx, irq);
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cfg->irptndx = INVALID_IRPTNDX;
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goto out_free_context;
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}
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smmu_domain->smmu = smmu;
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arm_smmu_init_context_bank(smmu_domain);
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return 0;
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out_free_context:
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__arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx);
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out_unlock:
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spin_unlock_irqrestore(&smmu_domain->lock, flags);
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return ret;
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}
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@ -975,7 +997,6 @@ static void arm_smmu_free_ptes(pmd_t *pmd)
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{
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pgtable_t table = pmd_pgtable(*pmd);
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pgtable_page_dtor(table);
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__free_page(table);
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}
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@ -1108,6 +1129,9 @@ static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu,
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void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
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struct arm_smmu_smr *smrs = cfg->smrs;
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if (!smrs)
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return;
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/* Invalidate the SMRs before freeing back to the allocator */
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for (i = 0; i < cfg->num_streamids; ++i) {
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u8 idx = smrs[i].idx;
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@ -1120,20 +1144,6 @@ static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu,
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kfree(smrs);
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}
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static void arm_smmu_bypass_stream_mapping(struct arm_smmu_device *smmu,
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struct arm_smmu_master_cfg *cfg)
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{
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int i;
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void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
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for (i = 0; i < cfg->num_streamids; ++i) {
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u16 sid = cfg->streamids[i];
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writel_relaxed(S2CR_TYPE_BYPASS,
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gr0_base + ARM_SMMU_GR0_S2CR(sid));
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}
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}
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static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
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struct arm_smmu_master_cfg *cfg)
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{
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@ -1160,23 +1170,30 @@ static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
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static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain,
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struct arm_smmu_master_cfg *cfg)
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{
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int i;
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struct arm_smmu_device *smmu = smmu_domain->smmu;
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void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
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/*
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* We *must* clear the S2CR first, because freeing the SMR means
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* that it can be re-allocated immediately.
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*/
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arm_smmu_bypass_stream_mapping(smmu, cfg);
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for (i = 0; i < cfg->num_streamids; ++i) {
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u32 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];
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writel_relaxed(S2CR_TYPE_BYPASS,
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gr0_base + ARM_SMMU_GR0_S2CR(idx));
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}
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arm_smmu_master_free_smrs(smmu, cfg);
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}
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static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
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{
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int ret = -EINVAL;
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int ret;
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struct arm_smmu_domain *smmu_domain = domain->priv;
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struct arm_smmu_device *smmu;
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struct arm_smmu_device *smmu, *dom_smmu;
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struct arm_smmu_master_cfg *cfg;
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unsigned long flags;
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smmu = dev_get_master_dev(dev)->archdata.iommu;
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if (!smmu) {
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@ -1188,20 +1205,22 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
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* Sanity check the domain. We don't support domains across
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* different SMMUs.
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*/
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spin_lock_irqsave(&smmu_domain->lock, flags);
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if (!smmu_domain->smmu) {
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dom_smmu = ACCESS_ONCE(smmu_domain->smmu);
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if (!dom_smmu) {
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/* Now that we have a master, we can finalise the domain */
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ret = arm_smmu_init_domain_context(domain, smmu);
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if (IS_ERR_VALUE(ret))
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goto err_unlock;
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} else if (smmu_domain->smmu != smmu) {
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return ret;
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dom_smmu = smmu_domain->smmu;
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}
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if (dom_smmu != smmu) {
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dev_err(dev,
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"cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n",
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dev_name(smmu_domain->smmu->dev),
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dev_name(smmu->dev));
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goto err_unlock;
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dev_name(smmu_domain->smmu->dev), dev_name(smmu->dev));
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return -EINVAL;
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}
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spin_unlock_irqrestore(&smmu_domain->lock, flags);
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/* Looks ok, so add the device to the domain */
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cfg = find_smmu_master_cfg(smmu_domain->smmu, dev);
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@ -1209,10 +1228,6 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
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return -ENODEV;
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return arm_smmu_domain_add_master(smmu_domain, cfg);
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err_unlock:
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spin_unlock_irqrestore(&smmu_domain->lock, flags);
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return ret;
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}
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static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev)
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@ -1247,10 +1262,6 @@ static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd,
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return -ENOMEM;
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arm_smmu_flush_pgtable(smmu, page_address(table), PAGE_SIZE);
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if (!pgtable_page_ctor(table)) {
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__free_page(table);
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return -ENOMEM;
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}
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pmd_populate(NULL, pmd, table);
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arm_smmu_flush_pgtable(smmu, pmd, sizeof(*pmd));
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}
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@ -1626,7 +1637,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
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/* Mark all SMRn as invalid and all S2CRn as bypass */
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for (i = 0; i < smmu->num_mapping_groups; ++i) {
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writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(i));
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writel_relaxed(0, gr0_base + ARM_SMMU_GR0_SMR(i));
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writel_relaxed(S2CR_TYPE_BYPASS,
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gr0_base + ARM_SMMU_GR0_S2CR(i));
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}
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@ -1761,6 +1772,9 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
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dev_notice(smmu->dev,
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"\tstream matching with %u register groups, mask 0x%x",
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smmu->num_mapping_groups, mask);
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} else {
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smmu->num_mapping_groups = (id >> ID0_NUMSIDB_SHIFT) &
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ID0_NUMSIDB_MASK;
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}
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/* ID1 */
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@ -1794,11 +1808,16 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
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* Stage-1 output limited by stage-2 input size due to pgd
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* allocation (PTRS_PER_PGD).
|
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*/
|
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if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) {
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#ifdef CONFIG_64BIT
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smmu->s1_output_size = min_t(unsigned long, VA_BITS, size);
|
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#else
|
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smmu->s1_output_size = min(32UL, size);
|
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#endif
|
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} else {
|
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smmu->s1_output_size = min_t(unsigned long, PHYS_MASK_SHIFT,
|
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size);
|
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}
|
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|
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/* The stage-2 output mask is also applied for bypass */
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size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);
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|
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@ -1889,6 +1908,10 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
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smmu->irqs[i] = irq;
|
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}
|
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|
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err = arm_smmu_device_cfg_probe(smmu);
|
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if (err)
|
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return err;
|
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|
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i = 0;
|
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smmu->masters = RB_ROOT;
|
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while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters",
|
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|
|
@ -1905,10 +1928,6 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
|
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}
|
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dev_notice(dev, "registered %d master devices\n", i);
|
||||
|
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err = arm_smmu_device_cfg_probe(smmu);
|
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if (err)
|
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goto out_put_masters;
|
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|
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parse_driver_options(smmu);
|
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|
||||
if (smmu->version > 1 &&
|
||||
|
|
|
|||
|
|
@ -678,8 +678,7 @@ static int __init dmar_acpi_dev_scope_init(void)
|
|||
andd->device_name);
|
||||
continue;
|
||||
}
|
||||
acpi_bus_get_device(h, &adev);
|
||||
if (!adev) {
|
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if (acpi_bus_get_device(h, &adev)) {
|
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pr_err("Failed to get device for ACPI object %s\n",
|
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andd->device_name);
|
||||
continue;
|
||||
|
|
|
|||
|
|
@ -984,7 +984,7 @@ static int fsl_pamu_add_device(struct device *dev)
|
|||
struct iommu_group *group = ERR_PTR(-ENODEV);
|
||||
struct pci_dev *pdev;
|
||||
const u32 *prop;
|
||||
int ret, len;
|
||||
int ret = 0, len;
|
||||
|
||||
/*
|
||||
* For platform devices we allocate a separate group for
|
||||
|
|
@ -1007,6 +1007,12 @@ static int fsl_pamu_add_device(struct device *dev)
|
|||
if (IS_ERR(group))
|
||||
return PTR_ERR(group);
|
||||
|
||||
/*
|
||||
* Check if device has already been added to an iommu group.
|
||||
* Group could have already been created for a PCI device in
|
||||
* the iommu_group_get_for_dev path.
|
||||
*/
|
||||
if (!dev->iommu_group)
|
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ret = iommu_group_add_device(group, dev);
|
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|
||||
iommu_group_put(group);
|
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|
|
|
|||
|
|
@ -678,14 +678,16 @@ static struct iommu_group *iommu_group_get_for_pci_dev(struct pci_dev *pdev)
|
|||
*/
|
||||
struct iommu_group *iommu_group_get_for_dev(struct device *dev)
|
||||
{
|
||||
struct iommu_group *group = ERR_PTR(-EIO);
|
||||
struct iommu_group *group;
|
||||
int ret;
|
||||
|
||||
group = iommu_group_get(dev);
|
||||
if (group)
|
||||
return group;
|
||||
|
||||
if (dev_is_pci(dev))
|
||||
if (!dev_is_pci(dev))
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
group = iommu_group_get_for_pci_dev(to_pci_dev(dev));
|
||||
|
||||
if (IS_ERR(group))
|
||||
|
|
|
|||
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