drm/i915/bdw: Broadwell has PIPEMISC
And it inherits some bits from the previous TRANS_CONF (aka PIPE_CONF on previous gens). v2: Rebase on to of the pipe config bpp handling rework. v3: Rebased on top of the pipe_config->dither refactoring. v4: Drop the read-modify-write cycle for PIPEMISC, similarly to how we now also build up PIPECONF completely ourselves - keeping around random stuff set by the BIOS just isn't a good idea. I've checked BDW BSpec and we already set all relevant bits. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -3237,6 +3237,18 @@
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#define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
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#define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
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#define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
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#define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
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#define _PIPE_MISC_A 0x70030
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#define _PIPE_MISC_B 0x71030
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#define PIPEMISC_DITHER_BPC_MASK (7<<5)
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#define PIPEMISC_DITHER_8_BPC (0<<5)
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#define PIPEMISC_DITHER_10_BPC (1<<5)
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#define PIPEMISC_DITHER_6_BPC (2<<5)
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#define PIPEMISC_DITHER_12_BPC (3<<5)
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#define PIPEMISC_DITHER_ENABLE (1<<4)
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#define PIPEMISC_DITHER_TYPE_MASK (3<<2)
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#define PIPEMISC_DITHER_TYPE_SP (0<<2)
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#define PIPEMISC(pipe) _PIPE(pipe, _PIPE_MISC_A, _PIPE_MISC_B)
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#define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028)
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#define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028)
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#define PIPEB_LINE_COMPARE_INT_EN (1<<29)
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#define PIPEB_LINE_COMPARE_INT_EN (1<<29)
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#define PIPEB_HLINE_INT_EN (1<<28)
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#define PIPEB_HLINE_INT_EN (1<<28)
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@ -5818,14 +5818,16 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc)
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static void haswell_set_pipeconf(struct drm_crtc *crtc)
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static void haswell_set_pipeconf(struct drm_crtc *crtc)
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{
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{
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struct drm_i915_private *dev_priv = crtc->dev->dev_private;
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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enum pipe pipe = intel_crtc->pipe;
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enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
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enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
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uint32_t val;
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uint32_t val;
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val = 0;
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val = 0;
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if (intel_crtc->config.dither)
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if (IS_HASWELL(dev) && intel_crtc->config.dither)
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val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
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val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
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if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
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if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
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@ -5838,6 +5840,33 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
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I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
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I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
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POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
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POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
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if (IS_BROADWELL(dev)) {
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val = 0;
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switch (intel_crtc->config.pipe_bpp) {
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case 18:
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val |= PIPEMISC_DITHER_6_BPC;
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break;
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case 24:
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val |= PIPEMISC_DITHER_8_BPC;
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break;
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case 30:
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val |= PIPEMISC_DITHER_10_BPC;
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break;
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case 36:
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val |= PIPEMISC_DITHER_12_BPC;
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break;
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default:
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/* Case prevented by pipe_config_set_bpp. */
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BUG();
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}
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if (intel_crtc->config.dither)
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val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
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I915_WRITE(PIPEMISC(pipe), val);
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}
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}
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}
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static bool ironlake_compute_clocks(struct drm_crtc *crtc,
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static bool ironlake_compute_clocks(struct drm_crtc *crtc,
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