ARM: OMAP: mux: add config for 16xx SPI pins
This patch adds pin mux info for the SPI master/slave interface on OMAP16xx. Data from OMAP 1611/1612 TRM and errata. Works for me on my 1611/H2 with current git kernel. Signed-off-by: Mark Howell <mhowell@northlink.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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Коммит
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@ -199,6 +199,17 @@ MUX_CFG("N14_1610_UWIRE_CS0", 8, 9, 1, 1, 21, 0, 1, 1, 1)
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MUX_CFG("P15_1610_UWIRE_CS3", 8, 12, 1, 1, 22, 0, 1, 1, 1)
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MUX_CFG("P15_1610_UWIRE_CS3", 8, 12, 1, 1, 22, 0, 1, 1, 1)
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MUX_CFG("N15_1610_UWIRE_CS1", 7, 18, 2, 1, 14, 0, NA, 0, 1)
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MUX_CFG("N15_1610_UWIRE_CS1", 7, 18, 2, 1, 14, 0, NA, 0, 1)
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/* OMAP-1610 SPI */
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MUX_CFG("U19_1610_SPIF_SCK", 7, 21, 6, 1, 15, 0, 1, 1, 1)
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MUX_CFG("U18_1610_SPIF_DIN", 8, 0, 6, 1, 18, 1, 1, 0, 1)
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MUX_CFG("P20_1610_SPIF_DIN", 6, 27, 4, 1, 7, 1, 1, 0, 1)
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MUX_CFG("W21_1610_SPIF_DOUT", 8, 3, 6, 1, 19, 0, 1, 0, 1)
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MUX_CFG("R18_1610_SPIF_DOUT", 7, 9, 3, 1, 11, 0, 1, 0, 1)
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MUX_CFG("N14_1610_SPIF_CS0", 8, 9, 6, 1, 21, 0, 1, 1, 1)
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MUX_CFG("N15_1610_SPIF_CS1", 7, 18, 6, 1, 14, 0, 1, 1, 1)
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MUX_CFG("T19_1610_SPIF_CS2", 7, 15, 4, 1, 13, 0, 1, 1, 1)
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MUX_CFG("P15_1610_SPIF_CS3", 8, 12, 3, 1, 22, 0, 1, 1, 1)
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/* OMAP-1610 Flash */
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/* OMAP-1610 Flash */
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MUX_CFG("L3_1610_FLASH_CS2B_OE",10, 6, 1, NA, 0, 0, NA, 0, 1)
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MUX_CFG("L3_1610_FLASH_CS2B_OE",10, 6, 1, NA, 0, 0, NA, 0, 1)
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MUX_CFG("M8_1610_FLASH_CS2B_WE",10, 3, 1, NA, 0, 0, NA, 0, 1)
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MUX_CFG("M8_1610_FLASH_CS2B_WE",10, 3, 1, NA, 0, 0, NA, 0, 1)
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@ -320,6 +320,17 @@ enum omap1xxx_index {
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P15_1610_UWIRE_CS3,
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P15_1610_UWIRE_CS3,
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N15_1610_UWIRE_CS1,
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N15_1610_UWIRE_CS1,
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/* OMAP-1610 SPI */
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U19_1610_SPIF_SCK,
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U18_1610_SPIF_DIN,
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P20_1610_SPIF_DIN,
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W21_1610_SPIF_DOUT,
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R18_1610_SPIF_DOUT,
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N14_1610_SPIF_CS0,
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N15_1610_SPIF_CS1,
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T19_1610_SPIF_CS2,
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P15_1610_SPIF_CS3,
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/* OMAP-1610 Flash */
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/* OMAP-1610 Flash */
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L3_1610_FLASH_CS2B_OE,
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L3_1610_FLASH_CS2B_OE,
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M8_1610_FLASH_CS2B_WE,
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M8_1610_FLASH_CS2B_WE,
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