OMAP: DSS2: DSI: Get number of DSI data lanes using DSI_GNQ register
On OMAP3, the DSI module has 2 data lanes. On OMAP4, DSI1 has 4 data lanes and DSI2 has 2 data lanes. Introduce function dsi_get_num_data_lanes() which returns the number of data lanes on the dsi interface, introduce function dsi_get_num_data_lanes_dssdev() which returns the number of data lanes used by the omap_dss_device connected to the lanes. Use the DSI_GNQ register on OMAP4 to get the number of data lanes, modify dsi.c to use the number of lanes and the extra data lanes on DSI1. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This commit is contained in:
Archit Taneja
Tomi Valkeinen
Родитель
49dbf5892f
Коммит
75d7247c07
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@ -59,6 +59,7 @@ struct dsi_reg { u16 idx; };
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#define DSI_IRQSTATUS DSI_REG(0x0018)
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#define DSI_IRQENABLE DSI_REG(0x001C)
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#define DSI_CTRL DSI_REG(0x0040)
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#define DSI_GNQ DSI_REG(0x0044)
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#define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
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#define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
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#define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
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@ -238,6 +239,10 @@ enum dsi_lane {
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DSI_DATA1_N = 1 << 3,
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DSI_DATA2_P = 1 << 4,
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DSI_DATA2_N = 1 << 5,
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DSI_DATA3_P = 1 << 6,
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DSI_DATA3_N = 1 << 7,
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DSI_DATA4_P = 1 << 8,
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DSI_DATA4_N = 1 << 9,
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};
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struct dsi_update_region {
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@ -326,6 +331,8 @@ struct dsi_data {
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unsigned long fint_min, fint_max;
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unsigned long lpdiv_max;
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int num_data_lanes;
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unsigned scp_clk_refcount;
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};
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@ -2001,10 +2008,39 @@ static int dsi_cio_power(struct platform_device *dsidev,
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return 0;
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}
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/* Number of data lanes present on DSI interface */
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static inline int dsi_get_num_data_lanes(struct platform_device *dsidev)
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{
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/* DSI on OMAP3 doesn't have register DSI_GNQ, set number
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* of data lanes as 2 by default */
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if (dss_has_feature(FEAT_DSI_GNQ))
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return REG_GET(dsidev, DSI_GNQ, 11, 9); /* NB_DATA_LANES */
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else
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return 2;
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}
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/* Number of data lanes used by the dss device */
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static inline int dsi_get_num_data_lanes_dssdev(struct omap_dss_device *dssdev)
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{
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int num_data_lanes = 0;
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if (dssdev->phy.dsi.data1_lane != 0)
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num_data_lanes++;
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if (dssdev->phy.dsi.data2_lane != 0)
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num_data_lanes++;
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if (dssdev->phy.dsi.data3_lane != 0)
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num_data_lanes++;
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if (dssdev->phy.dsi.data4_lane != 0)
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num_data_lanes++;
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return num_data_lanes;
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}
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static void dsi_set_lane_config(struct omap_dss_device *dssdev)
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{
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struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
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u32 r;
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int num_data_lanes_dssdev = dsi_get_num_data_lanes_dssdev(dssdev);
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int clk_lane = dssdev->phy.dsi.clk_lane;
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int data1_lane = dssdev->phy.dsi.data1_lane;
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@ -2020,6 +2056,20 @@ static void dsi_set_lane_config(struct omap_dss_device *dssdev)
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r = FLD_MOD(r, data1_pol, 7, 7);
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r = FLD_MOD(r, data2_lane, 10, 8);
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r = FLD_MOD(r, data2_pol, 11, 11);
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if (num_data_lanes_dssdev > 2) {
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int data3_lane = dssdev->phy.dsi.data3_lane;
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int data3_pol = dssdev->phy.dsi.data3_pol;
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r = FLD_MOD(r, data3_lane, 14, 12);
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r = FLD_MOD(r, data3_pol, 15, 15);
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}
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if (num_data_lanes_dssdev > 3) {
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int data4_lane = dssdev->phy.dsi.data4_lane;
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int data4_pol = dssdev->phy.dsi.data4_pol;
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r = FLD_MOD(r, data4_lane, 18, 16);
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r = FLD_MOD(r, data4_pol, 19, 19);
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}
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dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
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/* The configuration of the DSI complex I/O (number of data lanes,
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@ -2132,14 +2182,20 @@ static void dsi_cio_enable_lane_override(struct omap_dss_device *dssdev,
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enum dsi_lane lanes)
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{
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struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
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struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
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int clk_lane = dssdev->phy.dsi.clk_lane;
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int data1_lane = dssdev->phy.dsi.data1_lane;
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int data2_lane = dssdev->phy.dsi.data2_lane;
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int data3_lane = dssdev->phy.dsi.data3_lane;
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int data4_lane = dssdev->phy.dsi.data4_lane;
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int clk_pol = dssdev->phy.dsi.clk_pol;
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int data1_pol = dssdev->phy.dsi.data1_pol;
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int data2_pol = dssdev->phy.dsi.data2_pol;
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int data3_pol = dssdev->phy.dsi.data3_pol;
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int data4_pol = dssdev->phy.dsi.data4_pol;
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u32 l = 0;
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u8 lptxscp_start = dsi->num_data_lanes == 2 ? 22 : 26;
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if (lanes & DSI_CLK_P)
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l |= 1 << ((clk_lane - 1) * 2 + (clk_pol ? 0 : 1));
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@ -2156,17 +2212,28 @@ static void dsi_cio_enable_lane_override(struct omap_dss_device *dssdev,
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if (lanes & DSI_DATA2_N)
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l |= 1 << ((data2_lane - 1) * 2 + (data2_pol ? 1 : 0));
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if (lanes & DSI_DATA3_P)
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l |= 1 << ((data3_lane - 1) * 2 + (data3_pol ? 0 : 1));
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if (lanes & DSI_DATA3_N)
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l |= 1 << ((data3_lane - 1) * 2 + (data3_pol ? 1 : 0));
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if (lanes & DSI_DATA4_P)
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l |= 1 << ((data4_lane - 1) * 2 + (data4_pol ? 0 : 1));
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if (lanes & DSI_DATA4_N)
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l |= 1 << ((data4_lane - 1) * 2 + (data4_pol ? 1 : 0));
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/*
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* Bits in REGLPTXSCPDAT4TO0DXDY:
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* 17: DY0 18: DX0
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* 19: DY1 20: DX1
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* 21: DY2 22: DX2
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* 23: DY3 24: DX3
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* 25: DY4 26: DX4
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*/
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/* Set the lane override configuration */
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/* REGLPTXSCPDAT4TO0DXDY */
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REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, 22, 17);
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REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
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/* Enable lane override */
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@ -2248,6 +2315,7 @@ static int dsi_cio_init(struct omap_dss_device *dssdev)
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struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
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struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
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int r;
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int num_data_lanes_dssdev = dsi_get_num_data_lanes_dssdev(dssdev);
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u32 l;
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DSSDBGF();
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@ -2279,6 +2347,8 @@ static int dsi_cio_init(struct omap_dss_device *dssdev)
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dsi_write_reg(dsidev, DSI_TIMING1, l);
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if (dsi->ulps_enabled) {
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u32 lane_mask = DSI_CLK_P | DSI_DATA1_P | DSI_DATA2_P;
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DSSDBG("manual ulps exit\n");
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/* ULPS is exited by Mark-1 state for 1ms, followed by
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@ -2289,8 +2359,13 @@ static int dsi_cio_init(struct omap_dss_device *dssdev)
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* manually.
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*/
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dsi_cio_enable_lane_override(dssdev,
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DSI_CLK_P | DSI_DATA1_P | DSI_DATA2_P);
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if (num_data_lanes_dssdev > 2)
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lane_mask |= DSI_DATA3_P;
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if (num_data_lanes_dssdev > 3)
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lane_mask |= DSI_DATA4_P;
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dsi_cio_enable_lane_override(dssdev, lane_mask);
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}
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r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
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@ -3495,12 +3570,7 @@ static void dsi_proto_timings(struct omap_dss_device *dssdev)
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/* min 60ns + 52*UI */
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tclk_post = ns2ddr(dsidev, 60) + 26;
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/* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */
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if (dssdev->phy.dsi.data1_lane != 0 &&
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dssdev->phy.dsi.data2_lane != 0)
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ths_eot = 2;
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else
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ths_eot = 4;
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ths_eot = DIV_ROUND_UP(4, dsi_get_num_data_lanes_dssdev(dssdev));
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ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
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4);
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@ -4220,6 +4290,7 @@ int dsi_init_display(struct omap_dss_device *dssdev)
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{
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struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
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struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
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int dsi_module = dsi_get_dsidev_id(dsidev);
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DSSDBG("DSI init\n");
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@ -4240,6 +4311,12 @@ int dsi_init_display(struct omap_dss_device *dssdev)
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dsi->vdds_dsi_reg = vdds_dsi;
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}
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if (dsi_get_num_data_lanes_dssdev(dssdev) > dsi->num_data_lanes) {
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DSSERR("DSI%d can't support more than %d data lanes\n",
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dsi_module + 1, dsi->num_data_lanes);
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return -EINVAL;
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}
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return 0;
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}
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@ -4416,6 +4493,8 @@ static int dsi_init(struct platform_device *dsidev)
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dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
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FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
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dsi->num_data_lanes = dsi_get_num_data_lanes(dsidev);
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enable_clocks(0);
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return 0;
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@ -294,7 +294,8 @@ static const struct omap_dss_features omap4_dss_features = {
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FEAT_GLOBAL_ALPHA | FEAT_PRE_MULT_ALPHA |
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FEAT_MGR_LCD2 | FEAT_GLOBAL_ALPHA_VID1 |
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FEAT_CORE_CLK_DIV | FEAT_LCD_CLK_SRC |
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FEAT_DSI_DCS_CMD_CONFIG_VC | FEAT_DSI_VC_OCP_WIDTH,
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FEAT_DSI_DCS_CMD_CONFIG_VC | FEAT_DSI_VC_OCP_WIDTH |
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FEAT_DSI_GNQ,
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.num_mgrs = 3,
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.num_ovls = 3,
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@ -47,6 +47,7 @@ enum dss_feat_id {
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FEAT_DSI_DCS_CMD_CONFIG_VC = 1 << 15,
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FEAT_DSI_VC_OCP_WIDTH = 1 << 16,
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FEAT_DSI_REVERSE_TXCLKESC = 1 << 17,
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FEAT_DSI_GNQ = 1 << 18,
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};
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/* DSS register field id */
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@ -420,6 +420,10 @@ struct omap_dss_device {
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u8 data1_pol;
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u8 data2_lane;
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u8 data2_pol;
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u8 data3_lane;
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u8 data3_pol;
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u8 data4_lane;
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u8 data4_pol;
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int module;
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