rtw88: 8723d: initialize mac/bb/rf basic functions
Implement rtw_chip_ops::phy_set_param and ::mac_init to initialize mac/bb/rf, and they are used during interface up. The procedure contains power on sequence registers, download firmware, load predefined parameters, mac/bb/rf specific register and etc. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20200422034607.28747-9-yhchuang@realtek.com
This commit is contained in:
Ping-Ke Shih
Kalle Valo
Родитель
d91277de23
Коммит
75e69fb11b
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@ -1475,6 +1475,7 @@ struct rtw_efuse {
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u8 ant_div_cfg;
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u8 ant_div_type;
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u8 regd;
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u8 afe;
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u8 lna_type_2g;
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u8 lna_type_5g;
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@ -6,6 +6,7 @@
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#define __RTW_REG_DEF_H__
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#define REG_SYS_FUNC_EN 0x0002
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#define BIT_FEN_EN_25_1 BIT(13)
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#define BIT_FEN_ELDR BIT(12)
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#define BIT_FEN_CPUEN BIT(2)
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#define BIT_FEN_BB_GLB_RST BIT(1)
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@ -40,6 +41,11 @@
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#define BIT_MASK_EF_ADDR 0x3ff
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#define BIT_MASK_EF_DATA 0xff
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#define BITS_EF_ADDR (BIT_MASK_EF_ADDR << BIT_SHIFT_EF_ADDR)
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#define BITS_PLL 0xf0
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#define REG_AFE_CTRL3 0x2c
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#define BIT_MASK_XTAL 0x00FFF000
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#define BIT_XTAL_GMP_BIT4 BIT(28)
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#define REG_LDO_EFUSE_CTRL 0x0034
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#define BIT_MASK_EFUSE_BANK_SEL (BIT(8) | BIT(9))
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@ -61,6 +67,7 @@
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#define BIT_PAPE_SEL_EN BIT(25)
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#define BIT_DPDT_WL_SEL BIT(24)
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#define BIT_DPDT_SEL_EN BIT(23)
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#define REG_LEDCFG2 0x004E
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#define REG_PAD_CTRL1 0x0064
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#define BIT_PAPE_WLBT_SEL BIT(29)
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#define BIT_LNAON_WLBT_SEL BIT(28)
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@ -76,9 +83,15 @@
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#define BIT_LTE_MUX_CTRL_PATH BIT(26)
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#define REG_HCI_OPT_CTRL 0x0074
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#define REG_AFE_CTRL_4 0x0078
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#define BIT_CK320M_AFE_EN BIT(4)
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#define BIT_EN_SYN BIT(15)
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#define REG_LDO_SWR_CTRL 0x007C
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#define LDO_SEL 0xC3
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#define SPS_SEL 0x83
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#define BIT_XTA1 BIT(29)
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#define BIT_XTA0 BIT(28)
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#define REG_MCUFW_CTRL 0x0080
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#define BIT_ANA_PORT_EN BIT(22)
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@ -197,6 +210,7 @@
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#define BIT_FS_RXDONE BIT(16)
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#define REG_PKTBUF_DBG_CTRL 0x0140
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#define REG_C2HEVT 0x01A0
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#define REG_MCUTST_1 0x01C0
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#define REG_MCUTST_II 0x01C4
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#define REG_WOWLAN_WAKE_REASON 0x01C7
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#define REG_HMETFR 0x01CC
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@ -230,6 +244,7 @@
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#define REG_DWBCN0_CTRL 0x0208
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#define BIT_BCN_VALID BIT(16)
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#define REG_TXDMA_OFFSET_CHK 0x020C
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#define BIT_DROP_DATA_EN BIT(9)
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#define REG_TXDMA_STATUS 0x0210
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#define BTI_PAGE_OVF BIT(2)
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@ -291,6 +306,7 @@
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#define BIT_CHECK_CCK_EN BIT(7)
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#define REG_AMPDU_MAX_TIME_V1 0x0455
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#define REG_BCNQ1_BDNY_V1 0x0456
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#define REG_AMPDU_MAX_TIME 0x0456
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#define REG_WMAC_LBK_BF_HD 0x045D
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#define REG_TX_HANG_CTRL 0x045E
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#define BIT_EN_GNT_BT_AWAKE BIT(3)
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@ -306,7 +322,10 @@
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#define REG_QUEUE_CTRL 0x04C6
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#define BIT_PTA_WL_TX_EN BIT(4)
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#define BIT_PTA_EDCCA_EN BIT(5)
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#define REG_SINGLE_AMPDU_CTRL 0x04C7
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#define BIT_EN_SINGLE_APMDU BIT(7)
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#define REG_PROT_MODE_CTRL 0x04C8
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#define REG_MAX_AGGR_NUM 0x04CA
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#define REG_BAR_MODE_CTRL 0x04CC
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#define REG_PRECNT_CTRL 0x04E5
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#define BIT_BTCCA_CTRL (BIT(0) | BIT(1))
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@ -326,6 +345,7 @@
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#define BIT_SHIFT_SIFS_OFDM_CTX 8
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#define BIT_SHIFT_SIFS_CCK_TRX 16
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#define BIT_SHIFT_SIFS_OFDM_TRX 24
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#define REG_AGGR_BREAK_TIME 0x051A
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#define REG_SLOT 0x051B
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#define REG_TX_PTCL_CTRL 0x0520
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#define BIT_SIFS_BK_EN BIT(12)
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@ -337,18 +357,23 @@
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#define REG_TBTT_PROHIBIT 0x0540
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#define BIT_SHIFT_TBTT_HOLD_TIME_AP 8
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#define REG_RD_NAV_NXT 0x0544
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#define REG_NAV_PROT_LEN 0x0546
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#define REG_BCN_CTRL 0x0550
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#define BIT_DIS_TSF_UDT BIT(4)
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#define BIT_EN_BCN_FUNCTION BIT(3)
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#define BIT_EN_TXBCN_RPT BIT(2)
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#define REG_BCN_CTRL_CLINT0 0x0551
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#define REG_DRVERLYINT 0x0558
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#define REG_BCNDMATIM 0x0559
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#define REG_ATIMWND 0x055A
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#define REG_USTIME_TSF 0x055C
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#define REG_BCN_MAX_ERR 0x055D
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#define REG_RXTSF_OFFSET_CCK 0x055E
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#define REG_MISC_CTRL 0x0577
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#define BIT_EN_FREE_CNT BIT(3)
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#define BIT_DIS_SECOND_CCA (BIT(0) | BIT(1))
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#define REG_HIQ_NO_LMT_EN 0x5A7
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#define BIT_HIQ_NO_LMT_EN_ROOT BIT(0)
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#define REG_TIMER0_SRC_SEL 0x05B4
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#define BIT_TSFT_SEL_TIMER0 (BIT(4) | BIT(5) | BIT(6))
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@ -374,6 +399,7 @@
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#define BIT_HTC_LOC_CTRL BIT(14)
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#define BIT_RPFM_CAM_ENABLE BIT(12)
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#define BIT_TA_BCN BIT(11)
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#define BIT_RCR_ADF BIT(11)
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#define BIT_DISDECMYPKT BIT(10)
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#define BIT_AICV BIT(9)
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#define BIT_ACRC32 BIT(8)
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@ -391,6 +417,7 @@
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#define REG_MAR 0x0620
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#define REG_USTIME_EDCA 0x0638
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#define REG_ACKTO_CCK 0x0639
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#define REG_MAC_SPEC_SIFS 0x063A
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#define REG_RESP_SIFS_CCK 0x063C
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#define REG_RESP_SIFS_OFDM 0x063E
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#define REG_ACKTO 0x0640
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@ -433,12 +460,19 @@
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#define BIT_LTE_COEX_EN BIT(7)
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#define REG_BT_STAT_CTRL 0x0778
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#define REG_BT_TDMA_TIME 0x0790
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#define REG_LTR_IDLE_LATENCY 0x0798
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#define REG_LTR_ACTIVE_LATENCY 0x079C
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#define REG_LTR_CTRL_BASIC 0x07A4
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#define REG_WMAC_OPTION_FUNCTION 0x07D0
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#define REG_WMAC_OPTION_FUNCTION_1 0x07D4
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#define REG_FPGA0_RFMOD 0x0800
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#define BIT_CCKEN BIT(24)
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#define BIT_OFDMEN BIT(25)
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#define REG_RX_GAIN_EN 0x081c
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#define REG_RFE_CTRL_E 0x0974
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#define REG_2ND_CCA_CTRL 0x0976
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#define REG_DIS_DPD 0x0a70
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#define DIS_DPD_MASK GENMASK(9, 0)
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@ -37,6 +37,98 @@ static const struct rtw_hw_reg rtw8723d_txagc[] = {
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[DESC_RATEMCS7] = { .addr = 0xe14, .mask = 0xff000000 },
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};
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#define WLAN_TXQ_RPT_EN 0x1F
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#define WLAN_SLOT_TIME 0x09
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#define WLAN_RL_VAL 0x3030
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#define WLAN_BAR_VAL 0x0201ffff
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#define BIT_MASK_TBTT_HOLD 0x00000fff
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#define BIT_SHIFT_TBTT_HOLD 8
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#define BIT_MASK_TBTT_SETUP 0x000000ff
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#define BIT_SHIFT_TBTT_SETUP 0
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#define BIT_MASK_TBTT_MASK ((BIT_MASK_TBTT_HOLD << BIT_SHIFT_TBTT_HOLD) | \
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(BIT_MASK_TBTT_SETUP << BIT_SHIFT_TBTT_SETUP))
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#define TBTT_TIME(s, h)((((s) & BIT_MASK_TBTT_SETUP) << BIT_SHIFT_TBTT_SETUP) |\
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(((h) & BIT_MASK_TBTT_HOLD) << BIT_SHIFT_TBTT_HOLD))
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#define WLAN_TBTT_TIME_NORMAL TBTT_TIME(0x04, 0x80)
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#define WLAN_TBTT_TIME_STOP_BCN TBTT_TIME(0x04, 0x64)
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#define WLAN_PIFS_VAL 0
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#define WLAN_AGG_BRK_TIME 0x16
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#define WLAN_NAV_PROT_LEN 0x0040
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#define WLAN_SPEC_SIFS 0x100a
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#define WLAN_RX_PKT_LIMIT 0x17
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#define WLAN_MAX_AGG_NR 0x0A
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#define WLAN_AMPDU_MAX_TIME 0x1C
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#define WLAN_ANT_SEL 0x82
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#define WLAN_LTR_IDLE_LAT 0x883C883C
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#define WLAN_LTR_ACT_LAT 0x880B880B
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#define WLAN_LTR_CTRL1 0xCB004010
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#define WLAN_LTR_CTRL2 0x01233425
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static void rtw8723d_phy_set_param(struct rtw_dev *rtwdev)
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{
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u8 xtal_cap;
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u32 val32;
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/* power on BB/RF domain */
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rtw_write16_set(rtwdev, REG_SYS_FUNC_EN,
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BIT_FEN_EN_25_1 | BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB);
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rtw_write8_set(rtwdev, REG_RF_CTRL,
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BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
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rtw_write8(rtwdev, REG_AFE_CTRL1 + 1, 0x80);
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rtw_phy_load_tables(rtwdev);
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/* post init after header files config */
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rtw_write32_clr(rtwdev, REG_RCR, BIT_RCR_ADF);
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rtw_write8_set(rtwdev, REG_HIQ_NO_LMT_EN, BIT_HIQ_NO_LMT_EN_ROOT);
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rtw_write16_set(rtwdev, REG_AFE_CTRL_4, BIT_CK320M_AFE_EN | BIT_EN_SYN);
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xtal_cap = rtwdev->efuse.crystal_cap & 0x3F;
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rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL,
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xtal_cap | (xtal_cap << 6));
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rtw_write32_set(rtwdev, REG_FPGA0_RFMOD, BIT_CCKEN | BIT_OFDMEN);
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if ((rtwdev->efuse.afe >> 4) == 14) {
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rtw_write32_set(rtwdev, REG_AFE_CTRL3, BIT_XTAL_GMP_BIT4);
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rtw_write32_clr(rtwdev, REG_AFE_CTRL1, BITS_PLL);
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rtw_write32_set(rtwdev, REG_LDO_SWR_CTRL, BIT_XTA1);
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rtw_write32_clr(rtwdev, REG_LDO_SWR_CTRL, BIT_XTA0);
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}
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rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME);
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rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN);
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rtw_write16(rtwdev, REG_RETRY_LIMIT, WLAN_RL_VAL);
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rtw_write32(rtwdev, REG_BAR_MODE_CTRL, WLAN_BAR_VAL);
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rtw_write8(rtwdev, REG_ATIMWND, 0x2);
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rtw_write8(rtwdev, REG_BCN_CTRL,
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BIT_DIS_TSF_UDT | BIT_EN_BCN_FUNCTION | BIT_EN_TXBCN_RPT);
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val32 = rtw_read32(rtwdev, REG_TBTT_PROHIBIT);
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val32 &= ~BIT_MASK_TBTT_MASK;
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val32 |= WLAN_TBTT_TIME_STOP_BCN;
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rtw_write8(rtwdev, REG_TBTT_PROHIBIT, val32);
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rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_VAL);
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rtw_write8(rtwdev, REG_AGGR_BREAK_TIME, WLAN_AGG_BRK_TIME);
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rtw_write16(rtwdev, REG_NAV_PROT_LEN, WLAN_NAV_PROT_LEN);
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rtw_write16(rtwdev, REG_MAC_SPEC_SIFS, WLAN_SPEC_SIFS);
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rtw_write16(rtwdev, REG_SIFS, WLAN_SPEC_SIFS);
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rtw_write16(rtwdev, REG_SIFS + 2, WLAN_SPEC_SIFS);
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rtw_write8(rtwdev, REG_SINGLE_AMPDU_CTRL, BIT_EN_SINGLE_APMDU);
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rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RX_PKT_LIMIT);
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rtw_write8(rtwdev, REG_MAX_AGGR_NUM, WLAN_MAX_AGG_NR);
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rtw_write8(rtwdev, REG_AMPDU_MAX_TIME, WLAN_AMPDU_MAX_TIME);
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rtw_write8(rtwdev, REG_LEDCFG2, WLAN_ANT_SEL);
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rtw_write32(rtwdev, REG_LTR_IDLE_LATENCY, WLAN_LTR_IDLE_LAT);
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rtw_write32(rtwdev, REG_LTR_ACTIVE_LATENCY, WLAN_LTR_ACT_LAT);
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rtw_write32(rtwdev, REG_LTR_CTRL_BASIC, WLAN_LTR_CTRL1);
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rtw_write32(rtwdev, REG_LTR_CTRL_BASIC + 4, WLAN_LTR_CTRL2);
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rtw_phy_init(rtwdev);
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rtw_write16_set(rtwdev, REG_TXDMA_OFFSET_CHK, BIT_DROP_DATA_EN);
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rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50);
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rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20);
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}
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static void rtw8723de_efuse_parsing(struct rtw_efuse *efuse,
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struct rtw8723d_efuse *map)
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{
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@ -63,6 +155,7 @@ static int rtw8723d_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
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efuse->regd = map->rf_board_option & 0x7;
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efuse->thermal_meter[0] = map->thermal_meter;
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efuse->thermal_meter_k = map->thermal_meter;
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efuse->afe = map->afe;
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for (i = 0; i < 4; i++)
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efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
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@ -79,6 +172,35 @@ static int rtw8723d_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
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return 0;
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}
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#define BIT_CFENDFORM BIT(9)
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#define BIT_WMAC_TCR_ERR0 BIT(12)
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#define BIT_WMAC_TCR_ERR1 BIT(13)
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#define BIT_TCR_CFG (BIT_CFENDFORM | BIT_WMAC_TCR_ERR0 | \
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BIT_WMAC_TCR_ERR1)
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#define WLAN_RX_FILTER0 0xFFFF
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#define WLAN_RX_FILTER1 0x400
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#define WLAN_RX_FILTER2 0xFFFF
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#define WLAN_RCR_CFG 0x700060CE
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static int rtw8723d_mac_init(struct rtw_dev *rtwdev)
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{
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rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN);
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rtw_write32(rtwdev, REG_TCR, BIT_TCR_CFG);
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rtw_write16(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0);
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rtw_write16(rtwdev, REG_RXFLTMAP1, WLAN_RX_FILTER1);
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rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2);
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rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG);
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rtw_write32(rtwdev, REG_INT_MIG, 0);
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rtw_write32(rtwdev, REG_MCUTST_1, 0x0);
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rtw_write8(rtwdev, REG_MISC_CTRL, BIT_DIS_SECOND_CCA);
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rtw_write8(rtwdev, REG_2ND_CCA_CTRL, 0);
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return 0;
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}
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static void rtw8723d_cfg_ldo25(struct rtw_dev *rtwdev, bool enable)
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{
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u8 ldo_pwr;
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@ -143,7 +265,9 @@ static void rtw8723d_efuse_grant(struct rtw_dev *rtwdev, bool on)
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}
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static struct rtw_chip_ops rtw8723d_ops = {
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.phy_set_param = rtw8723d_phy_set_param,
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.read_efuse = rtw8723d_read_efuse,
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.mac_init = rtw8723d_mac_init,
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.read_rf = rtw_phy_read_rf_sipi,
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.write_rf = rtw_phy_write_rf_reg_sipi,
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.set_tx_power_index = rtw8723d_set_tx_power_index,
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@ -44,4 +44,7 @@ struct rtw8723d_efuse {
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struct rtw8723de_efuse e;
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};
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#define REG_OFDM0_XAAGC1 0x0c50
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#define REG_OFDM0_XBAGC1 0x0c58
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#endif
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