octeontx2-af: cn10k: DWRR MTU configuration
On OcteonTx2 DWRR quantum is directly configured into each of the transmit scheduler queues. And PF/VF drivers were free to config any value upto 2^24. On CN10K, HW is modified, the quantum configuration at scheduler queues is in terms of weight. And SW needs to setup a base DWRR MTU at NIX_AF_DWRR_RPM_MTU / NIX_AF_DWRR_SDP_MTU. HW will do 'DWRR MTU * weight' to get the quantum. For LBK traffic, value programmed into NIX_AF_DWRR_RPM_MTU register is considered as DWRR MTU. This patch programs a default DWRR MTU of 8192 into HW and also provides a way to change this via devlink params. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Родитель
cfba3fb689
Коммит
76660df2b4
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@ -150,6 +150,7 @@ enum nix_scheduler {
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#define DFLT_RR_WEIGHT 71
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#define DFLT_RR_QTM ((DFLT_RR_WEIGHT * TXSCH_RR_QTM_MAX) \
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/ MAX_SCHED_WEIGHT)
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#define CN10K_MAX_DWRR_WEIGHT 16384 /* Weight is 14bit on CN10K */
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/* Min/Max packet sizes, excluding FCS */
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#define NIC_HW_MIN_FRS 40
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@ -329,6 +329,7 @@ struct hw_cap {
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bool nix_shaping; /* Is shaping and coloring supported */
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bool nix_tx_link_bp; /* Can link backpressure TL queues ? */
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bool nix_rx_multicast; /* Rx packet replication support */
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bool nix_common_dwrr_mtu; /* Common DWRR MTU for quantum config */
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bool per_pf_mbox_regs; /* PF mbox specified in per PF registers ? */
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bool programmable_chans; /* Channels programmable ? */
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bool ipolicer;
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@ -706,6 +707,8 @@ int nix_aq_context_read(struct rvu *rvu, struct nix_hw *nix_hw,
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struct nix_cn10k_aq_enq_rsp *aq_rsp,
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u16 pcifunc, u8 ctype, u32 qidx);
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int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc);
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u32 convert_dwrr_mtu_to_bytes(u8 dwrr_mtu);
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u32 convert_bytes_to_dwrr_mtu(u32 bytes);
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/* NPC APIs */
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int rvu_npc_init(struct rvu *rvu);
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@ -1364,6 +1364,89 @@ static void rvu_health_reporters_destroy(struct rvu *rvu)
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rvu_nix_health_reporters_destroy(rvu_dl);
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}
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/* Devlink Params APIs */
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static int rvu_af_dl_dwrr_mtu_validate(struct devlink *devlink, u32 id,
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union devlink_param_value val,
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struct netlink_ext_ack *extack)
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{
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struct rvu_devlink *rvu_dl = devlink_priv(devlink);
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struct rvu *rvu = rvu_dl->rvu;
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int dwrr_mtu = val.vu32;
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struct nix_txsch *txsch;
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struct nix_hw *nix_hw;
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if (!rvu->hw->cap.nix_common_dwrr_mtu) {
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NL_SET_ERR_MSG_MOD(extack,
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"Setting DWRR_MTU is not supported on this silicon");
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return -EOPNOTSUPP;
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}
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if ((dwrr_mtu > 65536 || !is_power_of_2(dwrr_mtu)) &&
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(dwrr_mtu != 9728 && dwrr_mtu != 10240)) {
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NL_SET_ERR_MSG_MOD(extack,
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"Invalid, supported MTUs are 0,2,4,8.16,32,64....4K,8K,32K,64K and 9728, 10240");
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return -EINVAL;
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}
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nix_hw = get_nix_hw(rvu->hw, BLKADDR_NIX0);
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if (!nix_hw)
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return -ENODEV;
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txsch = &nix_hw->txsch[NIX_TXSCH_LVL_SMQ];
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if (rvu_rsrc_free_count(&txsch->schq) != txsch->schq.max) {
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NL_SET_ERR_MSG_MOD(extack,
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"Changing DWRR MTU is not supported when there are active NIXLFs");
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NL_SET_ERR_MSG_MOD(extack,
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"Makesure none of the PF/VF interfaces are initialized and retry");
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return -EOPNOTSUPP;
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}
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return 0;
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}
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static int rvu_af_dl_dwrr_mtu_set(struct devlink *devlink, u32 id,
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struct devlink_param_gset_ctx *ctx)
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{
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struct rvu_devlink *rvu_dl = devlink_priv(devlink);
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struct rvu *rvu = rvu_dl->rvu;
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u64 dwrr_mtu;
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dwrr_mtu = convert_bytes_to_dwrr_mtu(ctx->val.vu32);
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rvu_write64(rvu, BLKADDR_NIX0, NIX_AF_DWRR_RPM_MTU, dwrr_mtu);
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return 0;
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}
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static int rvu_af_dl_dwrr_mtu_get(struct devlink *devlink, u32 id,
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struct devlink_param_gset_ctx *ctx)
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{
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struct rvu_devlink *rvu_dl = devlink_priv(devlink);
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struct rvu *rvu = rvu_dl->rvu;
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u64 dwrr_mtu;
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if (!rvu->hw->cap.nix_common_dwrr_mtu)
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return -EOPNOTSUPP;
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dwrr_mtu = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_DWRR_RPM_MTU);
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ctx->val.vu32 = convert_dwrr_mtu_to_bytes(dwrr_mtu);
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return 0;
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}
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enum rvu_af_dl_param_id {
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RVU_AF_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX,
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RVU_AF_DEVLINK_PARAM_ID_DWRR_MTU,
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};
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static const struct devlink_param rvu_af_dl_params[] = {
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DEVLINK_PARAM_DRIVER(RVU_AF_DEVLINK_PARAM_ID_DWRR_MTU,
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"dwrr_mtu", DEVLINK_PARAM_TYPE_U32,
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BIT(DEVLINK_PARAM_CMODE_RUNTIME),
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rvu_af_dl_dwrr_mtu_get, rvu_af_dl_dwrr_mtu_set,
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rvu_af_dl_dwrr_mtu_validate),
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};
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/* Devlink switch mode */
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static int rvu_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode)
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{
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struct rvu_devlink *rvu_dl = devlink_priv(devlink);
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@ -1438,7 +1521,30 @@ int rvu_register_dl(struct rvu *rvu)
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rvu_dl->rvu = rvu;
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rvu->rvu_dl = rvu_dl;
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return rvu_health_reporters_create(rvu);
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err = rvu_health_reporters_create(rvu);
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if (err) {
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dev_err(rvu->dev,
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"devlink health reporter creation failed with error %d\n", err);
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goto err_dl_health;
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}
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err = devlink_params_register(dl, rvu_af_dl_params,
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ARRAY_SIZE(rvu_af_dl_params));
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if (err) {
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dev_err(rvu->dev,
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"devlink params register failed with error %d", err);
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goto err_dl_health;
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}
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devlink_params_publish(dl);
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return 0;
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err_dl_health:
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rvu_health_reporters_destroy(rvu);
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devlink_unregister(dl);
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devlink_free(dl);
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return err;
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}
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void rvu_unregister_dl(struct rvu *rvu)
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@ -1449,6 +1555,8 @@ void rvu_unregister_dl(struct rvu *rvu)
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if (!dl)
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return;
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devlink_params_unregister(dl, rvu_af_dl_params,
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ARRAY_SIZE(rvu_af_dl_params));
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rvu_health_reporters_destroy(rvu);
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devlink_unregister(dl);
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devlink_free(dl);
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@ -192,6 +192,47 @@ struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr)
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return NULL;
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}
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u32 convert_dwrr_mtu_to_bytes(u8 dwrr_mtu)
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{
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dwrr_mtu &= 0x1FULL;
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/* MTU used for DWRR calculation is in power of 2 up until 64K bytes.
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* Value of 4 is reserved for MTU value of 9728 bytes.
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* Value of 5 is reserved for MTU value of 10240 bytes.
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*/
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switch (dwrr_mtu) {
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case 4:
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return 9728;
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case 5:
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return 10240;
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default:
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return BIT_ULL(dwrr_mtu);
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}
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return 0;
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}
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u32 convert_bytes_to_dwrr_mtu(u32 bytes)
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{
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/* MTU used for DWRR calculation is in power of 2 up until 64K bytes.
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* Value of 4 is reserved for MTU value of 9728 bytes.
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* Value of 5 is reserved for MTU value of 10240 bytes.
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*/
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if (bytes > BIT_ULL(16))
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return 0;
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switch (bytes) {
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case 9728:
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return 4;
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case 10240:
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return 5;
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default:
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return ilog2(bytes);
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}
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return 0;
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}
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static void nix_rx_sync(struct rvu *rvu, int blkaddr)
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{
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int err;
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@ -1958,8 +1999,17 @@ static void nix_tl1_default_cfg(struct rvu *rvu, struct nix_hw *nix_hw,
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return;
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rvu_write64(rvu, blkaddr, NIX_AF_TL1X_TOPOLOGY(schq),
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(TXSCH_TL1_DFLT_RR_PRIO << 1));
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rvu_write64(rvu, blkaddr, NIX_AF_TL1X_SCHEDULE(schq),
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TXSCH_TL1_DFLT_RR_QTM);
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/* On OcteonTx2 the config was in bytes and newer silcons
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* it's changed to weight.
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*/
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if (!rvu->hw->cap.nix_common_dwrr_mtu)
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rvu_write64(rvu, blkaddr, NIX_AF_TL1X_SCHEDULE(schq),
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TXSCH_TL1_DFLT_RR_QTM);
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else
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rvu_write64(rvu, blkaddr, NIX_AF_TL1X_SCHEDULE(schq),
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CN10K_MAX_DWRR_WEIGHT);
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rvu_write64(rvu, blkaddr, NIX_AF_TL1X_CIR(schq), 0x00);
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pfvf_map[schq] = TXSCH_SET_FLAG(pfvf_map[schq], NIX_TXSCHQ_CFG_DONE);
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}
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@ -2667,6 +2717,15 @@ static int nix_setup_txschq(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr)
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for (schq = 0; schq < txsch->schq.max; schq++)
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txsch->pfvf_map[schq] = TXSCH_MAP(0, NIX_TXSCHQ_FREE);
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}
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/* Setup a default value of 8192 as DWRR MTU */
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if (rvu->hw->cap.nix_common_dwrr_mtu) {
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rvu_write64(rvu, blkaddr, NIX_AF_DWRR_RPM_MTU,
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convert_bytes_to_dwrr_mtu(8192));
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rvu_write64(rvu, blkaddr, NIX_AF_DWRR_SDP_MTU,
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convert_bytes_to_dwrr_mtu(8192));
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}
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return 0;
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}
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@ -3647,6 +3706,28 @@ static int nix_aq_init(struct rvu *rvu, struct rvu_block *block)
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return 0;
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}
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static void rvu_nix_setup_capabilities(struct rvu *rvu, int blkaddr)
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{
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struct rvu_hwinfo *hw = rvu->hw;
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u64 hw_const;
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hw_const = rvu_read64(rvu, blkaddr, NIX_AF_CONST1);
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/* On OcteonTx2 DWRR quantum is directly configured into each of
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* the transmit scheduler queues. And PF/VF drivers were free to
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* config any value upto 2^24.
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* On CN10K, HW is modified, the quantum configuration at scheduler
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* queues is in terms of weight. And SW needs to setup a base DWRR MTU
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* at NIX_AF_DWRR_RPM_MTU / NIX_AF_DWRR_SDP_MTU. HW will do
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* 'DWRR MTU * weight' to get the quantum.
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*
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* Check if HW uses a common MTU for all DWRR quantum configs.
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* On OcteonTx2 this register field is '0'.
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*/
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if (((hw_const >> 56) & 0x10) == 0x10)
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hw->cap.nix_common_dwrr_mtu = true;
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}
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static int rvu_nix_block_init(struct rvu *rvu, struct nix_hw *nix_hw)
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{
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const struct npc_lt_def_cfg *ltdefs;
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@ -3684,6 +3765,9 @@ static int rvu_nix_block_init(struct rvu *rvu, struct nix_hw *nix_hw)
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if (err)
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return err;
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/* Setup capabilities of the NIX block */
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rvu_nix_setup_capabilities(rvu, blkaddr);
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/* Initialize admin queue */
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err = nix_aq_init(rvu, block);
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if (err)
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@ -269,6 +269,8 @@
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#define NIX_AF_DEBUG_NPC_RESP_DATAX(a) (0x680 | (a) << 3)
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#define NIX_AF_SMQX_CFG(a) (0x700 | (a) << 16)
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#define NIX_AF_SQM_DBG_CTL_STATUS (0x750)
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#define NIX_AF_DWRR_SDP_MTU (0x790)
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#define NIX_AF_DWRR_RPM_MTU (0x7A0)
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#define NIX_AF_PSE_CHANNEL_LEVEL (0x800)
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#define NIX_AF_PSE_SHAPER_CFG (0x810)
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#define NIX_AF_TX_EXPR_CREDIT (0x830)
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