Merge branch 'upstream-net26' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/netdev-2.6
Conflicts: drivers/s390/net/qeth_main.c
This commit is contained in:
Коммит
76fef2b6bf
|
@ -213,14 +213,6 @@ Who: linuxppc-dev@ozlabs.org
|
|||
|
||||
---------------------------
|
||||
|
||||
What: sk98lin network driver
|
||||
When: Feburary 2008
|
||||
Why: In kernel tree version of driver is unmaintained. Sk98lin driver
|
||||
replaced by the skge driver.
|
||||
Who: Stephen Hemminger <shemminger@linux-foundation.org>
|
||||
|
||||
---------------------------
|
||||
|
||||
What: i386/x86_64 bzImage symlinks
|
||||
When: April 2008
|
||||
|
||||
|
@ -231,8 +223,6 @@ Who: Thomas Gleixner <tglx@linutronix.de>
|
|||
|
||||
---------------------------
|
||||
|
||||
---------------------------
|
||||
|
||||
What: i2c-i810, i2c-prosavage and i2c-savage4
|
||||
When: May 2008
|
||||
Why: These drivers are superseded by i810fb, intelfb and savagefb.
|
||||
|
|
|
@ -537,11 +537,9 @@ CONFIG_CTC=m
|
|||
# CONFIG_SMSGIUCV is not set
|
||||
# CONFIG_CLAW is not set
|
||||
CONFIG_QETH=y
|
||||
|
||||
#
|
||||
# Gigabit Ethernet default settings
|
||||
#
|
||||
# CONFIG_QETH_IPV6 is not set
|
||||
CONFIG_QETH_L2=y
|
||||
CONFIG_QETH_L3=y
|
||||
CONFIG_QETH_IPV6=y
|
||||
CONFIG_CCWGROUP=y
|
||||
# CONFIG_PPP is not set
|
||||
# CONFIG_SLIP is not set
|
||||
|
|
|
@ -48,14 +48,16 @@ EXPORT_SYMBOL(__alloc_ei_netdev);
|
|||
|
||||
#if defined(MODULE)
|
||||
|
||||
int init_module(void)
|
||||
static int __init ns8390_module_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
void cleanup_module(void)
|
||||
static void __exit ns8390_module_exit(void)
|
||||
{
|
||||
}
|
||||
|
||||
module_init(ns8390_init_module);
|
||||
module_exit(ns8390_module_exit);
|
||||
#endif /* MODULE */
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
|
@ -2220,93 +2220,6 @@ config SKY2_DEBUG
|
|||
|
||||
If unsure, say N.
|
||||
|
||||
config SK98LIN
|
||||
tristate "Marvell Yukon Chipset / SysKonnect SK-98xx Support (DEPRECATED)"
|
||||
depends on PCI
|
||||
---help---
|
||||
Say Y here if you have a Marvell Yukon or SysKonnect SK-98xx/SK-95xx
|
||||
compliant Gigabit Ethernet Adapter.
|
||||
|
||||
This driver supports the original Yukon chipset. This driver is
|
||||
deprecated and will be removed from the kernel in the near future,
|
||||
it has been replaced by the skge driver. skge is cleaner and
|
||||
seems to work better.
|
||||
|
||||
This driver does not support the newer Yukon2 chipset. A separate
|
||||
driver, sky2, is provided to support Yukon2-based adapters.
|
||||
|
||||
The following adapters are supported by this driver:
|
||||
- 3Com 3C940 Gigabit LOM Ethernet Adapter
|
||||
- 3Com 3C941 Gigabit LOM Ethernet Adapter
|
||||
- Allied Telesyn AT-2970LX Gigabit Ethernet Adapter
|
||||
- Allied Telesyn AT-2970LX/2SC Gigabit Ethernet Adapter
|
||||
- Allied Telesyn AT-2970SX Gigabit Ethernet Adapter
|
||||
- Allied Telesyn AT-2970SX/2SC Gigabit Ethernet Adapter
|
||||
- Allied Telesyn AT-2970TX Gigabit Ethernet Adapter
|
||||
- Allied Telesyn AT-2970TX/2TX Gigabit Ethernet Adapter
|
||||
- Allied Telesyn AT-2971SX Gigabit Ethernet Adapter
|
||||
- Allied Telesyn AT-2971T Gigabit Ethernet Adapter
|
||||
- Belkin Gigabit Desktop Card 10/100/1000Base-T Adapter, Copper RJ-45
|
||||
- EG1032 v2 Instant Gigabit Network Adapter
|
||||
- EG1064 v2 Instant Gigabit Network Adapter
|
||||
- Marvell 88E8001 Gigabit LOM Ethernet Adapter (Abit)
|
||||
- Marvell 88E8001 Gigabit LOM Ethernet Adapter (Albatron)
|
||||
- Marvell 88E8001 Gigabit LOM Ethernet Adapter (Asus)
|
||||
- Marvell 88E8001 Gigabit LOM Ethernet Adapter (ECS)
|
||||
- Marvell 88E8001 Gigabit LOM Ethernet Adapter (Epox)
|
||||
- Marvell 88E8001 Gigabit LOM Ethernet Adapter (Foxconn)
|
||||
- Marvell 88E8001 Gigabit LOM Ethernet Adapter (Gigabyte)
|
||||
- Marvell 88E8001 Gigabit LOM Ethernet Adapter (Iwill)
|
||||
- Marvell 88E8050 Gigabit LOM Ethernet Adapter (Intel)
|
||||
- Marvell RDK-8001 Adapter
|
||||
- Marvell RDK-8002 Adapter
|
||||
- Marvell RDK-8003 Adapter
|
||||
- Marvell RDK-8004 Adapter
|
||||
- Marvell RDK-8006 Adapter
|
||||
- Marvell RDK-8007 Adapter
|
||||
- Marvell RDK-8008 Adapter
|
||||
- Marvell RDK-8009 Adapter
|
||||
- Marvell RDK-8010 Adapter
|
||||
- Marvell RDK-8011 Adapter
|
||||
- Marvell RDK-8012 Adapter
|
||||
- Marvell RDK-8052 Adapter
|
||||
- Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Adapter (32 bit)
|
||||
- Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Adapter (64 bit)
|
||||
- N-Way PCI-Bus Giga-Card 1000/100/10Mbps(L)
|
||||
- SK-9521 10/100/1000Base-T Adapter
|
||||
- SK-9521 V2.0 10/100/1000Base-T Adapter
|
||||
- SK-9821 Gigabit Ethernet Server Adapter (SK-NET GE-T)
|
||||
- SK-9821 V2.0 Gigabit Ethernet 10/100/1000Base-T Adapter
|
||||
- SK-9822 Gigabit Ethernet Server Adapter (SK-NET GE-T dual link)
|
||||
- SK-9841 Gigabit Ethernet Server Adapter (SK-NET GE-LX)
|
||||
- SK-9841 V2.0 Gigabit Ethernet 1000Base-LX Adapter
|
||||
- SK-9842 Gigabit Ethernet Server Adapter (SK-NET GE-LX dual link)
|
||||
- SK-9843 Gigabit Ethernet Server Adapter (SK-NET GE-SX)
|
||||
- SK-9843 V2.0 Gigabit Ethernet 1000Base-SX Adapter
|
||||
- SK-9844 Gigabit Ethernet Server Adapter (SK-NET GE-SX dual link)
|
||||
- SK-9851 V2.0 Gigabit Ethernet 1000Base-SX Adapter
|
||||
- SK-9861 Gigabit Ethernet Server Adapter (SK-NET GE-SX Volition)
|
||||
- SK-9861 V2.0 Gigabit Ethernet 1000Base-SX Adapter
|
||||
- SK-9862 Gigabit Ethernet Server Adapter (SK-NET GE-SX Volition dual link)
|
||||
- SK-9871 Gigabit Ethernet Server Adapter (SK-NET GE-ZX)
|
||||
- SK-9871 V2.0 Gigabit Ethernet 1000Base-ZX Adapter
|
||||
- SK-9872 Gigabit Ethernet Server Adapter (SK-NET GE-ZX dual link)
|
||||
- SMC EZ Card 1000 (SMC9452TXV.2)
|
||||
|
||||
The adapters support Jumbo Frames.
|
||||
The dual link adapters support link-failover and dual port features.
|
||||
Both Marvell Yukon and SysKonnect SK-98xx/SK-95xx adapters support
|
||||
the scatter-gather functionality with sendfile(). Please refer to
|
||||
<file:Documentation/networking/sk98lin.txt> for more information about
|
||||
optional driver parameters.
|
||||
Questions concerning this driver may be addressed to:
|
||||
<linux@syskonnect.de>
|
||||
|
||||
If you want to compile this driver as a module ( = code which can be
|
||||
inserted in and removed from the running kernel whenever you want),
|
||||
say M here and read <file:Documentation/kbuild/modules.txt>. The module will
|
||||
be called sk98lin. This is recommended.
|
||||
|
||||
config VIA_VELOCITY
|
||||
tristate "VIA Velocity support"
|
||||
depends on PCI
|
||||
|
|
|
@ -15,7 +15,7 @@ obj-$(CONFIG_CHELSIO_T3) += cxgb3/
|
|||
obj-$(CONFIG_EHEA) += ehea/
|
||||
obj-$(CONFIG_CAN) += can/
|
||||
obj-$(CONFIG_BONDING) += bonding/
|
||||
obj-$(CONFIG_ATL1) += atl1/
|
||||
obj-$(CONFIG_ATL1) += atlx/
|
||||
obj-$(CONFIG_GIANFAR) += gianfar_driver.o
|
||||
obj-$(CONFIG_TEHUTI) += tehuti.o
|
||||
|
||||
|
@ -75,7 +75,6 @@ ps3_gelic-objs += ps3_gelic_net.o $(gelic_wireless-y)
|
|||
obj-$(CONFIG_TC35815) += tc35815.o
|
||||
obj-$(CONFIG_SKGE) += skge.o
|
||||
obj-$(CONFIG_SKY2) += sky2.o
|
||||
obj-$(CONFIG_SK98LIN) += sk98lin/
|
||||
obj-$(CONFIG_SKFP) += skfp/
|
||||
obj-$(CONFIG_VIA_RHINE) += via-rhine.o
|
||||
obj-$(CONFIG_VIA_VELOCITY) += via-velocity.o
|
||||
|
|
|
@ -1010,7 +1010,7 @@ module_param(io, int, 0);
|
|||
module_param(irq, int, 0);
|
||||
module_param(board_type, int, 0);
|
||||
|
||||
int __init init_module(void)
|
||||
static int __init cops_module_init(void)
|
||||
{
|
||||
if (io == 0)
|
||||
printk(KERN_WARNING "%s: You shouldn't autoprobe with insmod\n",
|
||||
|
@ -1021,12 +1021,14 @@ int __init init_module(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
void __exit cleanup_module(void)
|
||||
static void __exit cops_module_exit(void)
|
||||
{
|
||||
unregister_netdev(cops_dev);
|
||||
cleanup_card(cops_dev);
|
||||
free_netdev(cops_dev);
|
||||
}
|
||||
module_init(cops_module_init);
|
||||
module_exit(cops_module_exit);
|
||||
#endif /* MODULE */
|
||||
|
||||
/*
|
||||
|
|
|
@ -348,14 +348,15 @@ MODULE_LICENSE("GPL");
|
|||
|
||||
#ifdef MODULE
|
||||
|
||||
int init_module(void)
|
||||
static int __init com20020_module_init(void)
|
||||
{
|
||||
BUGLVL(D_NORMAL) printk(VERSION);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void cleanup_module(void)
|
||||
static void __exit com20020_module_exit(void)
|
||||
{
|
||||
}
|
||||
|
||||
module_init(com20020_module_init);
|
||||
module_exit(com20020_module_exit);
|
||||
#endif /* MODULE */
|
||||
|
|
|
@ -881,7 +881,7 @@ MODULE_PARM_DESC(io, "AT1700/FMV18X I/O base address");
|
|||
MODULE_PARM_DESC(irq, "AT1700/FMV18X IRQ number");
|
||||
MODULE_PARM_DESC(net_debug, "AT1700/FMV18X debug level (0-6)");
|
||||
|
||||
int __init init_module(void)
|
||||
static int __init at1700_module_init(void)
|
||||
{
|
||||
if (io == 0)
|
||||
printk("at1700: You should not use auto-probing with insmod!\n");
|
||||
|
@ -891,13 +891,14 @@ int __init init_module(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
void __exit
|
||||
cleanup_module(void)
|
||||
static void __exit at1700_module_exit(void)
|
||||
{
|
||||
unregister_netdev(dev_at1700);
|
||||
cleanup_card(dev_at1700);
|
||||
free_netdev(dev_at1700);
|
||||
}
|
||||
module_init(at1700_module_init);
|
||||
module_exit(at1700_module_exit);
|
||||
#endif /* MODULE */
|
||||
MODULE_LICENSE("GPL");
|
||||
|
||||
|
|
|
@ -1155,7 +1155,7 @@ static int lance_set_mac_address( struct net_device *dev, void *addr )
|
|||
#ifdef MODULE
|
||||
static struct net_device *atarilance_dev;
|
||||
|
||||
int __init init_module(void)
|
||||
static int __init atarilance_module_init(void)
|
||||
{
|
||||
atarilance_dev = atarilance_probe(-1);
|
||||
if (IS_ERR(atarilance_dev))
|
||||
|
@ -1163,13 +1163,14 @@ int __init init_module(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
void __exit cleanup_module(void)
|
||||
static void __exit atarilance_module_exit(void)
|
||||
{
|
||||
unregister_netdev(atarilance_dev);
|
||||
free_irq(atarilance_dev->irq, atarilance_dev);
|
||||
free_netdev(atarilance_dev);
|
||||
}
|
||||
|
||||
module_init(atarilance_module_init);
|
||||
module_exit(atarilance_module_exit);
|
||||
#endif /* MODULE */
|
||||
|
||||
|
||||
|
|
|
@ -1,2 +0,0 @@
|
|||
obj-$(CONFIG_ATL1) += atl1.o
|
||||
atl1-y += atl1_main.o atl1_hw.o atl1_ethtool.o atl1_param.o
|
|
@ -1,286 +0,0 @@
|
|||
/*
|
||||
* Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
|
||||
* Copyright(c) 2006 Chris Snook <csnook@redhat.com>
|
||||
* Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
|
||||
*
|
||||
* Derived from Intel e1000 driver
|
||||
* Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59
|
||||
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef _ATL1_H_
|
||||
#define _ATL1_H_
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/if_vlan.h>
|
||||
|
||||
#include "atl1_hw.h"
|
||||
|
||||
/* function prototypes needed by multiple files */
|
||||
s32 atl1_up(struct atl1_adapter *adapter);
|
||||
void atl1_down(struct atl1_adapter *adapter);
|
||||
int atl1_reset(struct atl1_adapter *adapter);
|
||||
s32 atl1_setup_ring_resources(struct atl1_adapter *adapter);
|
||||
void atl1_free_ring_resources(struct atl1_adapter *adapter);
|
||||
|
||||
extern char atl1_driver_name[];
|
||||
extern char atl1_driver_version[];
|
||||
extern const struct ethtool_ops atl1_ethtool_ops;
|
||||
|
||||
struct atl1_adapter;
|
||||
|
||||
#define ATL1_MAX_INTR 3
|
||||
#define ATL1_MAX_TX_BUF_LEN 0x3000 /* 12288 bytes */
|
||||
|
||||
#define ATL1_DEFAULT_TPD 256
|
||||
#define ATL1_MAX_TPD 1024
|
||||
#define ATL1_MIN_TPD 64
|
||||
#define ATL1_DEFAULT_RFD 512
|
||||
#define ATL1_MIN_RFD 128
|
||||
#define ATL1_MAX_RFD 2048
|
||||
|
||||
#define ATL1_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i]))
|
||||
#define ATL1_RFD_DESC(R, i) ATL1_GET_DESC(R, i, struct rx_free_desc)
|
||||
#define ATL1_TPD_DESC(R, i) ATL1_GET_DESC(R, i, struct tx_packet_desc)
|
||||
#define ATL1_RRD_DESC(R, i) ATL1_GET_DESC(R, i, struct rx_return_desc)
|
||||
|
||||
/*
|
||||
* This detached comment is preserved for documentation purposes only.
|
||||
* It was originally attached to some code that got deleted, but seems
|
||||
* important enough to keep around...
|
||||
*
|
||||
* <begin detached comment>
|
||||
* Some workarounds require millisecond delays and are run during interrupt
|
||||
* context. Most notably, when establishing link, the phy may need tweaking
|
||||
* but cannot process phy register reads/writes faster than millisecond
|
||||
* intervals...and we establish link due to a "link status change" interrupt.
|
||||
* <end detached comment>
|
||||
*/
|
||||
|
||||
/*
|
||||
* atl1_ring_header represents a single, contiguous block of DMA space
|
||||
* mapped for the three descriptor rings (tpd, rfd, rrd) and the two
|
||||
* message blocks (cmb, smb) described below
|
||||
*/
|
||||
struct atl1_ring_header {
|
||||
void *desc; /* virtual address */
|
||||
dma_addr_t dma; /* physical address*/
|
||||
unsigned int size; /* length in bytes */
|
||||
};
|
||||
|
||||
/*
|
||||
* atl1_buffer is wrapper around a pointer to a socket buffer
|
||||
* so a DMA handle can be stored along with the skb
|
||||
*/
|
||||
struct atl1_buffer {
|
||||
struct sk_buff *skb; /* socket buffer */
|
||||
u16 length; /* rx buffer length */
|
||||
u16 alloced; /* 1 if skb allocated */
|
||||
dma_addr_t dma;
|
||||
};
|
||||
|
||||
/* transmit packet descriptor (tpd) ring */
|
||||
struct atl1_tpd_ring {
|
||||
void *desc; /* descriptor ring virtual address */
|
||||
dma_addr_t dma; /* descriptor ring physical address */
|
||||
u16 size; /* descriptor ring length in bytes */
|
||||
u16 count; /* number of descriptors in the ring */
|
||||
u16 hw_idx; /* hardware index */
|
||||
atomic_t next_to_clean;
|
||||
atomic_t next_to_use;
|
||||
struct atl1_buffer *buffer_info;
|
||||
};
|
||||
|
||||
/* receive free descriptor (rfd) ring */
|
||||
struct atl1_rfd_ring {
|
||||
void *desc; /* descriptor ring virtual address */
|
||||
dma_addr_t dma; /* descriptor ring physical address */
|
||||
u16 size; /* descriptor ring length in bytes */
|
||||
u16 count; /* number of descriptors in the ring */
|
||||
atomic_t next_to_use;
|
||||
u16 next_to_clean;
|
||||
struct atl1_buffer *buffer_info;
|
||||
};
|
||||
|
||||
/* receive return descriptor (rrd) ring */
|
||||
struct atl1_rrd_ring {
|
||||
void *desc; /* descriptor ring virtual address */
|
||||
dma_addr_t dma; /* descriptor ring physical address */
|
||||
unsigned int size; /* descriptor ring length in bytes */
|
||||
u16 count; /* number of descriptors in the ring */
|
||||
u16 next_to_use;
|
||||
atomic_t next_to_clean;
|
||||
};
|
||||
|
||||
/* coalescing message block (cmb) */
|
||||
struct atl1_cmb {
|
||||
struct coals_msg_block *cmb;
|
||||
dma_addr_t dma;
|
||||
};
|
||||
|
||||
/* statistics message block (smb) */
|
||||
struct atl1_smb {
|
||||
struct stats_msg_block *smb;
|
||||
dma_addr_t dma;
|
||||
};
|
||||
|
||||
/* Statistics counters */
|
||||
struct atl1_sft_stats {
|
||||
u64 rx_packets;
|
||||
u64 tx_packets;
|
||||
u64 rx_bytes;
|
||||
u64 tx_bytes;
|
||||
u64 multicast;
|
||||
u64 collisions;
|
||||
u64 rx_errors;
|
||||
u64 rx_length_errors;
|
||||
u64 rx_crc_errors;
|
||||
u64 rx_frame_errors;
|
||||
u64 rx_fifo_errors;
|
||||
u64 rx_missed_errors;
|
||||
u64 tx_errors;
|
||||
u64 tx_fifo_errors;
|
||||
u64 tx_aborted_errors;
|
||||
u64 tx_window_errors;
|
||||
u64 tx_carrier_errors;
|
||||
u64 tx_pause; /* num pause packets transmitted. */
|
||||
u64 excecol; /* num tx packets w/ excessive collisions. */
|
||||
u64 deffer; /* num tx packets deferred */
|
||||
u64 scc; /* num packets subsequently transmitted
|
||||
* successfully w/ single prior collision. */
|
||||
u64 mcc; /* num packets subsequently transmitted
|
||||
* successfully w/ multiple prior collisions. */
|
||||
u64 latecol; /* num tx packets w/ late collisions. */
|
||||
u64 tx_underun; /* num tx packets aborted due to transmit
|
||||
* FIFO underrun, or TRD FIFO underrun */
|
||||
u64 tx_trunc; /* num tx packets truncated due to size
|
||||
* exceeding MTU, regardless whether truncated
|
||||
* by the chip or not. (The name doesn't really
|
||||
* reflect the meaning in this case.) */
|
||||
u64 rx_pause; /* num Pause packets received. */
|
||||
u64 rx_rrd_ov;
|
||||
u64 rx_trunc;
|
||||
};
|
||||
|
||||
/* hardware structure */
|
||||
struct atl1_hw {
|
||||
u8 __iomem *hw_addr;
|
||||
struct atl1_adapter *back;
|
||||
enum atl1_dma_order dma_ord;
|
||||
enum atl1_dma_rcb rcb_value;
|
||||
enum atl1_dma_req_block dmar_block;
|
||||
enum atl1_dma_req_block dmaw_block;
|
||||
u8 preamble_len;
|
||||
u8 max_retry; /* Retransmission maximum, after which the
|
||||
* packet will be discarded */
|
||||
u8 jam_ipg; /* IPG to start JAM for collision based flow
|
||||
* control in half-duplex mode. In units of
|
||||
* 8-bit time */
|
||||
u8 ipgt; /* Desired back to back inter-packet gap.
|
||||
* The default is 96-bit time */
|
||||
u8 min_ifg; /* Minimum number of IFG to enforce in between
|
||||
* receive frames. Frame gap below such IFP
|
||||
* is dropped */
|
||||
u8 ipgr1; /* 64bit Carrier-Sense window */
|
||||
u8 ipgr2; /* 96-bit IPG window */
|
||||
u8 tpd_burst; /* Number of TPD to prefetch in cache-aligned
|
||||
* burst. Each TPD is 16 bytes long */
|
||||
u8 rfd_burst; /* Number of RFD to prefetch in cache-aligned
|
||||
* burst. Each RFD is 12 bytes long */
|
||||
u8 rfd_fetch_gap;
|
||||
u8 rrd_burst; /* Threshold number of RRDs that can be retired
|
||||
* in a burst. Each RRD is 16 bytes long */
|
||||
u8 tpd_fetch_th;
|
||||
u8 tpd_fetch_gap;
|
||||
u16 tx_jumbo_task_th;
|
||||
u16 txf_burst; /* Number of data bytes to read in a cache-
|
||||
* aligned burst. Each SRAM entry is 8 bytes */
|
||||
u16 rx_jumbo_th; /* Jumbo packet size for non-VLAN packet. VLAN
|
||||
* packets should add 4 bytes */
|
||||
u16 rx_jumbo_lkah;
|
||||
u16 rrd_ret_timer; /* RRD retirement timer. Decrement by 1 after
|
||||
* every 512ns passes. */
|
||||
u16 lcol; /* Collision Window */
|
||||
|
||||
u16 cmb_tpd;
|
||||
u16 cmb_rrd;
|
||||
u16 cmb_rx_timer;
|
||||
u16 cmb_tx_timer;
|
||||
u32 smb_timer;
|
||||
u16 media_type;
|
||||
u16 autoneg_advertised;
|
||||
|
||||
u16 mii_autoneg_adv_reg;
|
||||
u16 mii_1000t_ctrl_reg;
|
||||
|
||||
u32 max_frame_size;
|
||||
u32 min_frame_size;
|
||||
|
||||
u16 dev_rev;
|
||||
|
||||
/* spi flash */
|
||||
u8 flash_vendor;
|
||||
|
||||
u8 mac_addr[ETH_ALEN];
|
||||
u8 perm_mac_addr[ETH_ALEN];
|
||||
|
||||
bool phy_configured;
|
||||
};
|
||||
|
||||
struct atl1_adapter {
|
||||
struct net_device *netdev;
|
||||
struct pci_dev *pdev;
|
||||
struct net_device_stats net_stats;
|
||||
struct atl1_sft_stats soft_stats;
|
||||
struct vlan_group *vlgrp;
|
||||
u32 rx_buffer_len;
|
||||
u32 wol;
|
||||
u16 link_speed;
|
||||
u16 link_duplex;
|
||||
spinlock_t lock;
|
||||
struct work_struct tx_timeout_task;
|
||||
struct work_struct link_chg_task;
|
||||
struct work_struct pcie_dma_to_rst_task;
|
||||
struct timer_list watchdog_timer;
|
||||
struct timer_list phy_config_timer;
|
||||
bool phy_timer_pending;
|
||||
|
||||
/* all descriptor rings' memory */
|
||||
struct atl1_ring_header ring_header;
|
||||
|
||||
/* TX */
|
||||
struct atl1_tpd_ring tpd_ring;
|
||||
spinlock_t mb_lock;
|
||||
|
||||
/* RX */
|
||||
struct atl1_rfd_ring rfd_ring;
|
||||
struct atl1_rrd_ring rrd_ring;
|
||||
u64 hw_csum_err;
|
||||
u64 hw_csum_good;
|
||||
|
||||
u16 imt; /* interrupt moderator timer (2us resolution */
|
||||
u16 ict; /* interrupt clear timer (2us resolution */
|
||||
struct mii_if_info mii; /* MII interface info */
|
||||
|
||||
/* structs defined in atl1_hw.h */
|
||||
u32 bd_number; /* board number */
|
||||
bool pci_using_64;
|
||||
struct atl1_hw hw;
|
||||
struct atl1_smb smb;
|
||||
struct atl1_cmb cmb;
|
||||
};
|
||||
|
||||
#endif /* _ATL1_H_ */
|
|
@ -1,505 +0,0 @@
|
|||
/*
|
||||
* Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
|
||||
* Copyright(c) 2006 Chris Snook <csnook@redhat.com>
|
||||
* Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
|
||||
*
|
||||
* Derived from Intel e1000 driver
|
||||
* Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59
|
||||
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/ethtool.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/mii.h>
|
||||
#include <asm/uaccess.h>
|
||||
|
||||
#include "atl1.h"
|
||||
|
||||
struct atl1_stats {
|
||||
char stat_string[ETH_GSTRING_LEN];
|
||||
int sizeof_stat;
|
||||
int stat_offset;
|
||||
};
|
||||
|
||||
#define ATL1_STAT(m) sizeof(((struct atl1_adapter *)0)->m), \
|
||||
offsetof(struct atl1_adapter, m)
|
||||
|
||||
static struct atl1_stats atl1_gstrings_stats[] = {
|
||||
{"rx_packets", ATL1_STAT(soft_stats.rx_packets)},
|
||||
{"tx_packets", ATL1_STAT(soft_stats.tx_packets)},
|
||||
{"rx_bytes", ATL1_STAT(soft_stats.rx_bytes)},
|
||||
{"tx_bytes", ATL1_STAT(soft_stats.tx_bytes)},
|
||||
{"rx_errors", ATL1_STAT(soft_stats.rx_errors)},
|
||||
{"tx_errors", ATL1_STAT(soft_stats.tx_errors)},
|
||||
{"rx_dropped", ATL1_STAT(net_stats.rx_dropped)},
|
||||
{"tx_dropped", ATL1_STAT(net_stats.tx_dropped)},
|
||||
{"multicast", ATL1_STAT(soft_stats.multicast)},
|
||||
{"collisions", ATL1_STAT(soft_stats.collisions)},
|
||||
{"rx_length_errors", ATL1_STAT(soft_stats.rx_length_errors)},
|
||||
{"rx_over_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
|
||||
{"rx_crc_errors", ATL1_STAT(soft_stats.rx_crc_errors)},
|
||||
{"rx_frame_errors", ATL1_STAT(soft_stats.rx_frame_errors)},
|
||||
{"rx_fifo_errors", ATL1_STAT(soft_stats.rx_fifo_errors)},
|
||||
{"rx_missed_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
|
||||
{"tx_aborted_errors", ATL1_STAT(soft_stats.tx_aborted_errors)},
|
||||
{"tx_carrier_errors", ATL1_STAT(soft_stats.tx_carrier_errors)},
|
||||
{"tx_fifo_errors", ATL1_STAT(soft_stats.tx_fifo_errors)},
|
||||
{"tx_window_errors", ATL1_STAT(soft_stats.tx_window_errors)},
|
||||
{"tx_abort_exce_coll", ATL1_STAT(soft_stats.excecol)},
|
||||
{"tx_abort_late_coll", ATL1_STAT(soft_stats.latecol)},
|
||||
{"tx_deferred_ok", ATL1_STAT(soft_stats.deffer)},
|
||||
{"tx_single_coll_ok", ATL1_STAT(soft_stats.scc)},
|
||||
{"tx_multi_coll_ok", ATL1_STAT(soft_stats.mcc)},
|
||||
{"tx_underun", ATL1_STAT(soft_stats.tx_underun)},
|
||||
{"tx_trunc", ATL1_STAT(soft_stats.tx_trunc)},
|
||||
{"tx_pause", ATL1_STAT(soft_stats.tx_pause)},
|
||||
{"rx_pause", ATL1_STAT(soft_stats.rx_pause)},
|
||||
{"rx_rrd_ov", ATL1_STAT(soft_stats.rx_rrd_ov)},
|
||||
{"rx_trunc", ATL1_STAT(soft_stats.rx_trunc)}
|
||||
};
|
||||
|
||||
static void atl1_get_ethtool_stats(struct net_device *netdev,
|
||||
struct ethtool_stats *stats, u64 *data)
|
||||
{
|
||||
struct atl1_adapter *adapter = netdev_priv(netdev);
|
||||
int i;
|
||||
char *p;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
|
||||
p = (char *)adapter+atl1_gstrings_stats[i].stat_offset;
|
||||
data[i] = (atl1_gstrings_stats[i].sizeof_stat ==
|
||||
sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static int atl1_get_sset_count(struct net_device *netdev, int sset)
|
||||
{
|
||||
switch (sset) {
|
||||
case ETH_SS_STATS:
|
||||
return ARRAY_SIZE(atl1_gstrings_stats);
|
||||
default:
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
}
|
||||
|
||||
static int atl1_get_settings(struct net_device *netdev,
|
||||
struct ethtool_cmd *ecmd)
|
||||
{
|
||||
struct atl1_adapter *adapter = netdev_priv(netdev);
|
||||
struct atl1_hw *hw = &adapter->hw;
|
||||
|
||||
ecmd->supported = (SUPPORTED_10baseT_Half |
|
||||
SUPPORTED_10baseT_Full |
|
||||
SUPPORTED_100baseT_Half |
|
||||
SUPPORTED_100baseT_Full |
|
||||
SUPPORTED_1000baseT_Full |
|
||||
SUPPORTED_Autoneg | SUPPORTED_TP);
|
||||
ecmd->advertising = ADVERTISED_TP;
|
||||
if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
|
||||
hw->media_type == MEDIA_TYPE_1000M_FULL) {
|
||||
ecmd->advertising |= ADVERTISED_Autoneg;
|
||||
if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR) {
|
||||
ecmd->advertising |= ADVERTISED_Autoneg;
|
||||
ecmd->advertising |=
|
||||
(ADVERTISED_10baseT_Half |
|
||||
ADVERTISED_10baseT_Full |
|
||||
ADVERTISED_100baseT_Half |
|
||||
ADVERTISED_100baseT_Full |
|
||||
ADVERTISED_1000baseT_Full);
|
||||
}
|
||||
else
|
||||
ecmd->advertising |= (ADVERTISED_1000baseT_Full);
|
||||
}
|
||||
ecmd->port = PORT_TP;
|
||||
ecmd->phy_address = 0;
|
||||
ecmd->transceiver = XCVR_INTERNAL;
|
||||
|
||||
if (netif_carrier_ok(adapter->netdev)) {
|
||||
u16 link_speed, link_duplex;
|
||||
atl1_get_speed_and_duplex(hw, &link_speed, &link_duplex);
|
||||
ecmd->speed = link_speed;
|
||||
if (link_duplex == FULL_DUPLEX)
|
||||
ecmd->duplex = DUPLEX_FULL;
|
||||
else
|
||||
ecmd->duplex = DUPLEX_HALF;
|
||||
} else {
|
||||
ecmd->speed = -1;
|
||||
ecmd->duplex = -1;
|
||||
}
|
||||
if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
|
||||
hw->media_type == MEDIA_TYPE_1000M_FULL)
|
||||
ecmd->autoneg = AUTONEG_ENABLE;
|
||||
else
|
||||
ecmd->autoneg = AUTONEG_DISABLE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int atl1_set_settings(struct net_device *netdev,
|
||||
struct ethtool_cmd *ecmd)
|
||||
{
|
||||
struct atl1_adapter *adapter = netdev_priv(netdev);
|
||||
struct atl1_hw *hw = &adapter->hw;
|
||||
u16 phy_data;
|
||||
int ret_val = 0;
|
||||
u16 old_media_type = hw->media_type;
|
||||
|
||||
if (netif_running(adapter->netdev)) {
|
||||
dev_dbg(&adapter->pdev->dev, "ethtool shutting down adapter\n");
|
||||
atl1_down(adapter);
|
||||
}
|
||||
|
||||
if (ecmd->autoneg == AUTONEG_ENABLE)
|
||||
hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
|
||||
else {
|
||||
if (ecmd->speed == SPEED_1000) {
|
||||
if (ecmd->duplex != DUPLEX_FULL) {
|
||||
dev_warn(&adapter->pdev->dev,
|
||||
"can't force to 1000M half duplex\n");
|
||||
ret_val = -EINVAL;
|
||||
goto exit_sset;
|
||||
}
|
||||
hw->media_type = MEDIA_TYPE_1000M_FULL;
|
||||
} else if (ecmd->speed == SPEED_100) {
|
||||
if (ecmd->duplex == DUPLEX_FULL) {
|
||||
hw->media_type = MEDIA_TYPE_100M_FULL;
|
||||
} else
|
||||
hw->media_type = MEDIA_TYPE_100M_HALF;
|
||||
} else {
|
||||
if (ecmd->duplex == DUPLEX_FULL)
|
||||
hw->media_type = MEDIA_TYPE_10M_FULL;
|
||||
else
|
||||
hw->media_type = MEDIA_TYPE_10M_HALF;
|
||||
}
|
||||
}
|
||||
switch (hw->media_type) {
|
||||
case MEDIA_TYPE_AUTO_SENSOR:
|
||||
ecmd->advertising =
|
||||
ADVERTISED_10baseT_Half |
|
||||
ADVERTISED_10baseT_Full |
|
||||
ADVERTISED_100baseT_Half |
|
||||
ADVERTISED_100baseT_Full |
|
||||
ADVERTISED_1000baseT_Full |
|
||||
ADVERTISED_Autoneg | ADVERTISED_TP;
|
||||
break;
|
||||
case MEDIA_TYPE_1000M_FULL:
|
||||
ecmd->advertising =
|
||||
ADVERTISED_1000baseT_Full |
|
||||
ADVERTISED_Autoneg | ADVERTISED_TP;
|
||||
break;
|
||||
default:
|
||||
ecmd->advertising = 0;
|
||||
break;
|
||||
}
|
||||
if (atl1_phy_setup_autoneg_adv(hw)) {
|
||||
ret_val = -EINVAL;
|
||||
dev_warn(&adapter->pdev->dev,
|
||||
"invalid ethtool speed/duplex setting\n");
|
||||
goto exit_sset;
|
||||
}
|
||||
if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
|
||||
hw->media_type == MEDIA_TYPE_1000M_FULL)
|
||||
phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
|
||||
else {
|
||||
switch (hw->media_type) {
|
||||
case MEDIA_TYPE_100M_FULL:
|
||||
phy_data =
|
||||
MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
|
||||
MII_CR_RESET;
|
||||
break;
|
||||
case MEDIA_TYPE_100M_HALF:
|
||||
phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
|
||||
break;
|
||||
case MEDIA_TYPE_10M_FULL:
|
||||
phy_data =
|
||||
MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
|
||||
break;
|
||||
default: /* MEDIA_TYPE_10M_HALF: */
|
||||
phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
|
||||
break;
|
||||
}
|
||||
}
|
||||
atl1_write_phy_reg(hw, MII_BMCR, phy_data);
|
||||
exit_sset:
|
||||
if (ret_val)
|
||||
hw->media_type = old_media_type;
|
||||
|
||||
if (netif_running(adapter->netdev)) {
|
||||
dev_dbg(&adapter->pdev->dev, "ethtool starting adapter\n");
|
||||
atl1_up(adapter);
|
||||
} else if (!ret_val) {
|
||||
dev_dbg(&adapter->pdev->dev, "ethtool resetting adapter\n");
|
||||
atl1_reset(adapter);
|
||||
}
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
static void atl1_get_drvinfo(struct net_device *netdev,
|
||||
struct ethtool_drvinfo *drvinfo)
|
||||
{
|
||||
struct atl1_adapter *adapter = netdev_priv(netdev);
|
||||
|
||||
strncpy(drvinfo->driver, atl1_driver_name, sizeof(drvinfo->driver));
|
||||
strncpy(drvinfo->version, atl1_driver_version,
|
||||
sizeof(drvinfo->version));
|
||||
strncpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
|
||||
strncpy(drvinfo->bus_info, pci_name(adapter->pdev),
|
||||
sizeof(drvinfo->bus_info));
|
||||
drvinfo->eedump_len = ATL1_EEDUMP_LEN;
|
||||
}
|
||||
|
||||
static void atl1_get_wol(struct net_device *netdev,
|
||||
struct ethtool_wolinfo *wol)
|
||||
{
|
||||
struct atl1_adapter *adapter = netdev_priv(netdev);
|
||||
|
||||
wol->supported = WAKE_UCAST | WAKE_MCAST | WAKE_BCAST | WAKE_MAGIC;
|
||||
wol->wolopts = 0;
|
||||
if (adapter->wol & ATL1_WUFC_EX)
|
||||
wol->wolopts |= WAKE_UCAST;
|
||||
if (adapter->wol & ATL1_WUFC_MC)
|
||||
wol->wolopts |= WAKE_MCAST;
|
||||
if (adapter->wol & ATL1_WUFC_BC)
|
||||
wol->wolopts |= WAKE_BCAST;
|
||||
if (adapter->wol & ATL1_WUFC_MAG)
|
||||
wol->wolopts |= WAKE_MAGIC;
|
||||
return;
|
||||
}
|
||||
|
||||
static int atl1_set_wol(struct net_device *netdev,
|
||||
struct ethtool_wolinfo *wol)
|
||||
{
|
||||
struct atl1_adapter *adapter = netdev_priv(netdev);
|
||||
|
||||
if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
|
||||
return -EOPNOTSUPP;
|
||||
adapter->wol = 0;
|
||||
if (wol->wolopts & WAKE_UCAST)
|
||||
adapter->wol |= ATL1_WUFC_EX;
|
||||
if (wol->wolopts & WAKE_MCAST)
|
||||
adapter->wol |= ATL1_WUFC_MC;
|
||||
if (wol->wolopts & WAKE_BCAST)
|
||||
adapter->wol |= ATL1_WUFC_BC;
|
||||
if (wol->wolopts & WAKE_MAGIC)
|
||||
adapter->wol |= ATL1_WUFC_MAG;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void atl1_get_ringparam(struct net_device *netdev,
|
||||
struct ethtool_ringparam *ring)
|
||||
{
|
||||
struct atl1_adapter *adapter = netdev_priv(netdev);
|
||||
struct atl1_tpd_ring *txdr = &adapter->tpd_ring;
|
||||
struct atl1_rfd_ring *rxdr = &adapter->rfd_ring;
|
||||
|
||||
ring->rx_max_pending = ATL1_MAX_RFD;
|
||||
ring->tx_max_pending = ATL1_MAX_TPD;
|
||||
ring->rx_mini_max_pending = 0;
|
||||
ring->rx_jumbo_max_pending = 0;
|
||||
ring->rx_pending = rxdr->count;
|
||||
ring->tx_pending = txdr->count;
|
||||
ring->rx_mini_pending = 0;
|
||||
ring->rx_jumbo_pending = 0;
|
||||
}
|
||||
|
||||
static int atl1_set_ringparam(struct net_device *netdev,
|
||||
struct ethtool_ringparam *ring)
|
||||
{
|
||||
struct atl1_adapter *adapter = netdev_priv(netdev);
|
||||
struct atl1_tpd_ring *tpdr = &adapter->tpd_ring;
|
||||
struct atl1_rrd_ring *rrdr = &adapter->rrd_ring;
|
||||
struct atl1_rfd_ring *rfdr = &adapter->rfd_ring;
|
||||
|
||||
struct atl1_tpd_ring tpd_old, tpd_new;
|
||||
struct atl1_rfd_ring rfd_old, rfd_new;
|
||||
struct atl1_rrd_ring rrd_old, rrd_new;
|
||||
struct atl1_ring_header rhdr_old, rhdr_new;
|
||||
int err;
|
||||
|
||||
tpd_old = adapter->tpd_ring;
|
||||
rfd_old = adapter->rfd_ring;
|
||||
rrd_old = adapter->rrd_ring;
|
||||
rhdr_old = adapter->ring_header;
|
||||
|
||||
if (netif_running(adapter->netdev))
|
||||
atl1_down(adapter);
|
||||
|
||||
rfdr->count = (u16) max(ring->rx_pending, (u32) ATL1_MIN_RFD);
|
||||
rfdr->count = rfdr->count > ATL1_MAX_RFD ? ATL1_MAX_RFD :
|
||||
rfdr->count;
|
||||
rfdr->count = (rfdr->count + 3) & ~3;
|
||||
rrdr->count = rfdr->count;
|
||||
|
||||
tpdr->count = (u16) max(ring->tx_pending, (u32) ATL1_MIN_TPD);
|
||||
tpdr->count = tpdr->count > ATL1_MAX_TPD ? ATL1_MAX_TPD :
|
||||
tpdr->count;
|
||||
tpdr->count = (tpdr->count + 3) & ~3;
|
||||
|
||||
if (netif_running(adapter->netdev)) {
|
||||
/* try to get new resources before deleting old */
|
||||
err = atl1_setup_ring_resources(adapter);
|
||||
if (err)
|
||||
goto err_setup_ring;
|
||||
|
||||
/*
|
||||
* save the new, restore the old in order to free it,
|
||||
* then restore the new back again
|
||||
*/
|
||||
|
||||
rfd_new = adapter->rfd_ring;
|
||||
rrd_new = adapter->rrd_ring;
|
||||
tpd_new = adapter->tpd_ring;
|
||||
rhdr_new = adapter->ring_header;
|
||||
adapter->rfd_ring = rfd_old;
|
||||
adapter->rrd_ring = rrd_old;
|
||||
adapter->tpd_ring = tpd_old;
|
||||
adapter->ring_header = rhdr_old;
|
||||
atl1_free_ring_resources(adapter);
|
||||
adapter->rfd_ring = rfd_new;
|
||||
adapter->rrd_ring = rrd_new;
|
||||
adapter->tpd_ring = tpd_new;
|
||||
adapter->ring_header = rhdr_new;
|
||||
|
||||
err = atl1_up(adapter);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
return 0;
|
||||
|
||||
err_setup_ring:
|
||||
adapter->rfd_ring = rfd_old;
|
||||
adapter->rrd_ring = rrd_old;
|
||||
adapter->tpd_ring = tpd_old;
|
||||
adapter->ring_header = rhdr_old;
|
||||
atl1_up(adapter);
|
||||
return err;
|
||||
}
|
||||
|
||||
static void atl1_get_pauseparam(struct net_device *netdev,
|
||||
struct ethtool_pauseparam *epause)
|
||||
{
|
||||
struct atl1_adapter *adapter = netdev_priv(netdev);
|
||||
struct atl1_hw *hw = &adapter->hw;
|
||||
|
||||
if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
|
||||
hw->media_type == MEDIA_TYPE_1000M_FULL) {
|
||||
epause->autoneg = AUTONEG_ENABLE;
|
||||
} else {
|
||||
epause->autoneg = AUTONEG_DISABLE;
|
||||
}
|
||||
epause->rx_pause = 1;
|
||||
epause->tx_pause = 1;
|
||||
}
|
||||
|
||||
static int atl1_set_pauseparam(struct net_device *netdev,
|
||||
struct ethtool_pauseparam *epause)
|
||||
{
|
||||
struct atl1_adapter *adapter = netdev_priv(netdev);
|
||||
struct atl1_hw *hw = &adapter->hw;
|
||||
|
||||
if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
|
||||
hw->media_type == MEDIA_TYPE_1000M_FULL) {
|
||||
epause->autoneg = AUTONEG_ENABLE;
|
||||
} else {
|
||||
epause->autoneg = AUTONEG_DISABLE;
|
||||
}
|
||||
|
||||
epause->rx_pause = 1;
|
||||
epause->tx_pause = 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u32 atl1_get_rx_csum(struct net_device *netdev)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void atl1_get_strings(struct net_device *netdev, u32 stringset,
|
||||
u8 *data)
|
||||
{
|
||||
u8 *p = data;
|
||||
int i;
|
||||
|
||||
switch (stringset) {
|
||||
case ETH_SS_STATS:
|
||||
for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
|
||||
memcpy(p, atl1_gstrings_stats[i].stat_string,
|
||||
ETH_GSTRING_LEN);
|
||||
p += ETH_GSTRING_LEN;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static int atl1_nway_reset(struct net_device *netdev)
|
||||
{
|
||||
struct atl1_adapter *adapter = netdev_priv(netdev);
|
||||
struct atl1_hw *hw = &adapter->hw;
|
||||
|
||||
if (netif_running(netdev)) {
|
||||
u16 phy_data;
|
||||
atl1_down(adapter);
|
||||
|
||||
if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
|
||||
hw->media_type == MEDIA_TYPE_1000M_FULL) {
|
||||
phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
|
||||
} else {
|
||||
switch (hw->media_type) {
|
||||
case MEDIA_TYPE_100M_FULL:
|
||||
phy_data = MII_CR_FULL_DUPLEX |
|
||||
MII_CR_SPEED_100 | MII_CR_RESET;
|
||||
break;
|
||||
case MEDIA_TYPE_100M_HALF:
|
||||
phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
|
||||
break;
|
||||
case MEDIA_TYPE_10M_FULL:
|
||||
phy_data = MII_CR_FULL_DUPLEX |
|
||||
MII_CR_SPEED_10 | MII_CR_RESET;
|
||||
break;
|
||||
default: /* MEDIA_TYPE_10M_HALF */
|
||||
phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
|
||||
}
|
||||
}
|
||||
atl1_write_phy_reg(hw, MII_BMCR, phy_data);
|
||||
atl1_up(adapter);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct ethtool_ops atl1_ethtool_ops = {
|
||||
.get_settings = atl1_get_settings,
|
||||
.set_settings = atl1_set_settings,
|
||||
.get_drvinfo = atl1_get_drvinfo,
|
||||
.get_wol = atl1_get_wol,
|
||||
.set_wol = atl1_set_wol,
|
||||
.get_ringparam = atl1_get_ringparam,
|
||||
.set_ringparam = atl1_set_ringparam,
|
||||
.get_pauseparam = atl1_get_pauseparam,
|
||||
.set_pauseparam = atl1_set_pauseparam,
|
||||
.get_rx_csum = atl1_get_rx_csum,
|
||||
.set_tx_csum = ethtool_op_set_tx_hw_csum,
|
||||
.get_link = ethtool_op_get_link,
|
||||
.set_sg = ethtool_op_set_sg,
|
||||
.get_strings = atl1_get_strings,
|
||||
.nway_reset = atl1_nway_reset,
|
||||
.get_ethtool_stats = atl1_get_ethtool_stats,
|
||||
.get_sset_count = atl1_get_sset_count,
|
||||
.set_tso = ethtool_op_set_tso,
|
||||
};
|
|
@ -1,720 +0,0 @@
|
|||
/*
|
||||
* Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
|
||||
* Copyright(c) 2006 Chris Snook <csnook@redhat.com>
|
||||
* Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
|
||||
*
|
||||
* Derived from Intel e1000 driver
|
||||
* Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59
|
||||
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/if_vlan.h>
|
||||
#include <linux/etherdevice.h>
|
||||
#include <linux/crc32.h>
|
||||
#include <asm/byteorder.h>
|
||||
|
||||
#include "atl1.h"
|
||||
|
||||
/*
|
||||
* Reset the transmit and receive units; mask and clear all interrupts.
|
||||
* hw - Struct containing variables accessed by shared code
|
||||
* return : ATL1_SUCCESS or idle status (if error)
|
||||
*/
|
||||
s32 atl1_reset_hw(struct atl1_hw *hw)
|
||||
{
|
||||
struct pci_dev *pdev = hw->back->pdev;
|
||||
u32 icr;
|
||||
int i;
|
||||
|
||||
/*
|
||||
* Clear Interrupt mask to stop board from generating
|
||||
* interrupts & Clear any pending interrupt events
|
||||
*/
|
||||
/*
|
||||
* iowrite32(0, hw->hw_addr + REG_IMR);
|
||||
* iowrite32(0xffffffff, hw->hw_addr + REG_ISR);
|
||||
*/
|
||||
|
||||
/*
|
||||
* Issue Soft Reset to the MAC. This will reset the chip's
|
||||
* transmit, receive, DMA. It will not effect
|
||||
* the current PCI configuration. The global reset bit is self-
|
||||
* clearing, and should clear within a microsecond.
|
||||
*/
|
||||
iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
|
||||
ioread32(hw->hw_addr + REG_MASTER_CTRL);
|
||||
|
||||
iowrite16(1, hw->hw_addr + REG_GPHY_ENABLE);
|
||||
ioread16(hw->hw_addr + REG_GPHY_ENABLE);
|
||||
|
||||
msleep(1); /* delay about 1ms */
|
||||
|
||||
/* Wait at least 10ms for All module to be Idle */
|
||||
for (i = 0; i < 10; i++) {
|
||||
icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
|
||||
if (!icr)
|
||||
break;
|
||||
msleep(1); /* delay 1 ms */
|
||||
cpu_relax(); /* FIXME: is this still the right way to do this? */
|
||||
}
|
||||
|
||||
if (icr) {
|
||||
dev_dbg(&pdev->dev, "ICR = 0x%x\n", icr);
|
||||
return icr;
|
||||
}
|
||||
|
||||
return ATL1_SUCCESS;
|
||||
}
|
||||
|
||||
/* function about EEPROM
|
||||
*
|
||||
* check_eeprom_exist
|
||||
* return 0 if eeprom exist
|
||||
*/
|
||||
static int atl1_check_eeprom_exist(struct atl1_hw *hw)
|
||||
{
|
||||
u32 value;
|
||||
value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
|
||||
if (value & SPI_FLASH_CTRL_EN_VPD) {
|
||||
value &= ~SPI_FLASH_CTRL_EN_VPD;
|
||||
iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
|
||||
}
|
||||
|
||||
value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST);
|
||||
return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
|
||||
}
|
||||
|
||||
static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
|
||||
{
|
||||
int i;
|
||||
u32 control;
|
||||
|
||||
if (offset & 3)
|
||||
return false; /* address do not align */
|
||||
|
||||
iowrite32(0, hw->hw_addr + REG_VPD_DATA);
|
||||
control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
|
||||
iowrite32(control, hw->hw_addr + REG_VPD_CAP);
|
||||
ioread32(hw->hw_addr + REG_VPD_CAP);
|
||||
|
||||
for (i = 0; i < 10; i++) {
|
||||
msleep(2);
|
||||
control = ioread32(hw->hw_addr + REG_VPD_CAP);
|
||||
if (control & VPD_CAP_VPD_FLAG)
|
||||
break;
|
||||
}
|
||||
if (control & VPD_CAP_VPD_FLAG) {
|
||||
*p_value = ioread32(hw->hw_addr + REG_VPD_DATA);
|
||||
return true;
|
||||
}
|
||||
return false; /* timeout */
|
||||
}
|
||||
|
||||
/*
|
||||
* Reads the value from a PHY register
|
||||
* hw - Struct containing variables accessed by shared code
|
||||
* reg_addr - address of the PHY register to read
|
||||
*/
|
||||
s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
|
||||
{
|
||||
u32 val;
|
||||
int i;
|
||||
|
||||
val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
|
||||
MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 <<
|
||||
MDIO_CLK_SEL_SHIFT;
|
||||
iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
|
||||
ioread32(hw->hw_addr + REG_MDIO_CTRL);
|
||||
|
||||
for (i = 0; i < MDIO_WAIT_TIMES; i++) {
|
||||
udelay(2);
|
||||
val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
|
||||
if (!(val & (MDIO_START | MDIO_BUSY)))
|
||||
break;
|
||||
}
|
||||
if (!(val & (MDIO_START | MDIO_BUSY))) {
|
||||
*phy_data = (u16) val;
|
||||
return ATL1_SUCCESS;
|
||||
}
|
||||
return ATL1_ERR_PHY;
|
||||
}
|
||||
|
||||
#define CUSTOM_SPI_CS_SETUP 2
|
||||
#define CUSTOM_SPI_CLK_HI 2
|
||||
#define CUSTOM_SPI_CLK_LO 2
|
||||
#define CUSTOM_SPI_CS_HOLD 2
|
||||
#define CUSTOM_SPI_CS_HI 3
|
||||
|
||||
static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
|
||||
{
|
||||
int i;
|
||||
u32 value;
|
||||
|
||||
iowrite32(0, hw->hw_addr + REG_SPI_DATA);
|
||||
iowrite32(addr, hw->hw_addr + REG_SPI_ADDR);
|
||||
|
||||
value = SPI_FLASH_CTRL_WAIT_READY |
|
||||
(CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
|
||||
SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI &
|
||||
SPI_FLASH_CTRL_CLK_HI_MASK) <<
|
||||
SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO &
|
||||
SPI_FLASH_CTRL_CLK_LO_MASK) <<
|
||||
SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD &
|
||||
SPI_FLASH_CTRL_CS_HOLD_MASK) <<
|
||||
SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI &
|
||||
SPI_FLASH_CTRL_CS_HI_MASK) <<
|
||||
SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) <<
|
||||
SPI_FLASH_CTRL_INS_SHIFT;
|
||||
|
||||
iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
|
||||
|
||||
value |= SPI_FLASH_CTRL_START;
|
||||
iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
|
||||
ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
|
||||
|
||||
for (i = 0; i < 10; i++) {
|
||||
msleep(1); /* 1ms */
|
||||
value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
|
||||
if (!(value & SPI_FLASH_CTRL_START))
|
||||
break;
|
||||
}
|
||||
|
||||
if (value & SPI_FLASH_CTRL_START)
|
||||
return false;
|
||||
|
||||
*buf = ioread32(hw->hw_addr + REG_SPI_DATA);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/*
|
||||
* get_permanent_address
|
||||
* return 0 if get valid mac address,
|
||||
*/
|
||||
static int atl1_get_permanent_address(struct atl1_hw *hw)
|
||||
{
|
||||
u32 addr[2];
|
||||
u32 i, control;
|
||||
u16 reg;
|
||||
u8 eth_addr[ETH_ALEN];
|
||||
bool key_valid;
|
||||
|
||||
if (is_valid_ether_addr(hw->perm_mac_addr))
|
||||
return 0;
|
||||
|
||||
/* init */
|
||||
addr[0] = addr[1] = 0;
|
||||
|
||||
if (!atl1_check_eeprom_exist(hw)) { /* eeprom exist */
|
||||
reg = 0;
|
||||
key_valid = false;
|
||||
/* Read out all EEPROM content */
|
||||
i = 0;
|
||||
while (1) {
|
||||
if (atl1_read_eeprom(hw, i + 0x100, &control)) {
|
||||
if (key_valid) {
|
||||
if (reg == REG_MAC_STA_ADDR)
|
||||
addr[0] = control;
|
||||
else if (reg == (REG_MAC_STA_ADDR + 4))
|
||||
addr[1] = control;
|
||||
key_valid = false;
|
||||
} else if ((control & 0xff) == 0x5A) {
|
||||
key_valid = true;
|
||||
reg = (u16) (control >> 16);
|
||||
} else
|
||||
break; /* assume data end while encount an invalid KEYWORD */
|
||||
} else
|
||||
break; /* read error */
|
||||
i += 4;
|
||||
}
|
||||
|
||||
*(u32 *) ð_addr[2] = swab32(addr[0]);
|
||||
*(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]);
|
||||
if (is_valid_ether_addr(eth_addr)) {
|
||||
memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
|
||||
return 0;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* see if SPI FLAGS exist ? */
|
||||
addr[0] = addr[1] = 0;
|
||||
reg = 0;
|
||||
key_valid = false;
|
||||
i = 0;
|
||||
while (1) {
|
||||
if (atl1_spi_read(hw, i + 0x1f000, &control)) {
|
||||
if (key_valid) {
|
||||
if (reg == REG_MAC_STA_ADDR)
|
||||
addr[0] = control;
|
||||
else if (reg == (REG_MAC_STA_ADDR + 4))
|
||||
addr[1] = control;
|
||||
key_valid = false;
|
||||
} else if ((control & 0xff) == 0x5A) {
|
||||
key_valid = true;
|
||||
reg = (u16) (control >> 16);
|
||||
} else
|
||||
break; /* data end */
|
||||
} else
|
||||
break; /* read error */
|
||||
i += 4;
|
||||
}
|
||||
|
||||
*(u32 *) ð_addr[2] = swab32(addr[0]);
|
||||
*(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]);
|
||||
if (is_valid_ether_addr(eth_addr)) {
|
||||
memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* On some motherboards, the MAC address is written by the
|
||||
* BIOS directly to the MAC register during POST, and is
|
||||
* not stored in eeprom. If all else thus far has failed
|
||||
* to fetch the permanent MAC address, try reading it directly.
|
||||
*/
|
||||
addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR);
|
||||
addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4));
|
||||
*(u32 *) ð_addr[2] = swab32(addr[0]);
|
||||
*(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]);
|
||||
if (is_valid_ether_addr(eth_addr)) {
|
||||
memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Reads the adapter's MAC address from the EEPROM
|
||||
* hw - Struct containing variables accessed by shared code
|
||||
*/
|
||||
s32 atl1_read_mac_addr(struct atl1_hw *hw)
|
||||
{
|
||||
u16 i;
|
||||
|
||||
if (atl1_get_permanent_address(hw))
|
||||
random_ether_addr(hw->perm_mac_addr);
|
||||
|
||||
for (i = 0; i < ETH_ALEN; i++)
|
||||
hw->mac_addr[i] = hw->perm_mac_addr[i];
|
||||
return ATL1_SUCCESS;
|
||||
}
|
||||
|
||||
/*
|
||||
* Hashes an address to determine its location in the multicast table
|
||||
* hw - Struct containing variables accessed by shared code
|
||||
* mc_addr - the multicast address to hash
|
||||
*
|
||||
* atl1_hash_mc_addr
|
||||
* purpose
|
||||
* set hash value for a multicast address
|
||||
* hash calcu processing :
|
||||
* 1. calcu 32bit CRC for multicast address
|
||||
* 2. reverse crc with MSB to LSB
|
||||
*/
|
||||
u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr)
|
||||
{
|
||||
u32 crc32, value = 0;
|
||||
int i;
|
||||
|
||||
crc32 = ether_crc_le(6, mc_addr);
|
||||
for (i = 0; i < 32; i++)
|
||||
value |= (((crc32 >> i) & 1) << (31 - i));
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
/*
|
||||
* Sets the bit in the multicast table corresponding to the hash value.
|
||||
* hw - Struct containing variables accessed by shared code
|
||||
* hash_value - Multicast address hash value
|
||||
*/
|
||||
void atl1_hash_set(struct atl1_hw *hw, u32 hash_value)
|
||||
{
|
||||
u32 hash_bit, hash_reg;
|
||||
u32 mta;
|
||||
|
||||
/*
|
||||
* The HASH Table is a register array of 2 32-bit registers.
|
||||
* It is treated like an array of 64 bits. We want to set
|
||||
* bit BitArray[hash_value]. So we figure out what register
|
||||
* the bit is in, read it, OR in the new bit, then write
|
||||
* back the new value. The register is determined by the
|
||||
* upper 7 bits of the hash value and the bit within that
|
||||
* register are determined by the lower 5 bits of the value.
|
||||
*/
|
||||
hash_reg = (hash_value >> 31) & 0x1;
|
||||
hash_bit = (hash_value >> 26) & 0x1F;
|
||||
mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
|
||||
mta |= (1 << hash_bit);
|
||||
iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
|
||||
}
|
||||
|
||||
/*
|
||||
* Writes a value to a PHY register
|
||||
* hw - Struct containing variables accessed by shared code
|
||||
* reg_addr - address of the PHY register to write
|
||||
* data - data to write to the PHY
|
||||
*/
|
||||
s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
|
||||
{
|
||||
int i;
|
||||
u32 val;
|
||||
|
||||
val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
|
||||
(reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
|
||||
MDIO_SUP_PREAMBLE |
|
||||
MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
|
||||
iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
|
||||
ioread32(hw->hw_addr + REG_MDIO_CTRL);
|
||||
|
||||
for (i = 0; i < MDIO_WAIT_TIMES; i++) {
|
||||
udelay(2);
|
||||
val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
|
||||
if (!(val & (MDIO_START | MDIO_BUSY)))
|
||||
break;
|
||||
}
|
||||
|
||||
if (!(val & (MDIO_START | MDIO_BUSY)))
|
||||
return ATL1_SUCCESS;
|
||||
|
||||
return ATL1_ERR_PHY;
|
||||
}
|
||||
|
||||
/*
|
||||
* Make L001's PHY out of Power Saving State (bug)
|
||||
* hw - Struct containing variables accessed by shared code
|
||||
* when power on, L001's PHY always on Power saving State
|
||||
* (Gigabit Link forbidden)
|
||||
*/
|
||||
static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw)
|
||||
{
|
||||
s32 ret;
|
||||
ret = atl1_write_phy_reg(hw, 29, 0x0029);
|
||||
if (ret)
|
||||
return ret;
|
||||
return atl1_write_phy_reg(hw, 30, 0);
|
||||
}
|
||||
|
||||
/*
|
||||
*TODO: do something or get rid of this
|
||||
*/
|
||||
s32 atl1_phy_enter_power_saving(struct atl1_hw *hw)
|
||||
{
|
||||
/* s32 ret_val;
|
||||
* u16 phy_data;
|
||||
*/
|
||||
|
||||
/*
|
||||
ret_val = atl1_write_phy_reg(hw, ...);
|
||||
ret_val = atl1_write_phy_reg(hw, ...);
|
||||
....
|
||||
*/
|
||||
return ATL1_SUCCESS;
|
||||
}
|
||||
|
||||
/*
|
||||
* Resets the PHY and make all config validate
|
||||
* hw - Struct containing variables accessed by shared code
|
||||
*
|
||||
* Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
|
||||
*/
|
||||
static s32 atl1_phy_reset(struct atl1_hw *hw)
|
||||
{
|
||||
struct pci_dev *pdev = hw->back->pdev;
|
||||
s32 ret_val;
|
||||
u16 phy_data;
|
||||
|
||||
if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
|
||||
hw->media_type == MEDIA_TYPE_1000M_FULL)
|
||||
phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
|
||||
else {
|
||||
switch (hw->media_type) {
|
||||
case MEDIA_TYPE_100M_FULL:
|
||||
phy_data =
|
||||
MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
|
||||
MII_CR_RESET;
|
||||
break;
|
||||
case MEDIA_TYPE_100M_HALF:
|
||||
phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
|
||||
break;
|
||||
case MEDIA_TYPE_10M_FULL:
|
||||
phy_data =
|
||||
MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
|
||||
break;
|
||||
default: /* MEDIA_TYPE_10M_HALF: */
|
||||
phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
|
||||
if (ret_val) {
|
||||
u32 val;
|
||||
int i;
|
||||
/* pcie serdes link may be down! */
|
||||
dev_dbg(&pdev->dev, "pcie phy link down\n");
|
||||
|
||||
for (i = 0; i < 25; i++) {
|
||||
msleep(1);
|
||||
val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
|
||||
if (!(val & (MDIO_START | MDIO_BUSY)))
|
||||
break;
|
||||
}
|
||||
|
||||
if ((val & (MDIO_START | MDIO_BUSY)) != 0) {
|
||||
dev_warn(&pdev->dev, "pcie link down at least 25ms\n");
|
||||
return ret_val;
|
||||
}
|
||||
}
|
||||
return ATL1_SUCCESS;
|
||||
}
|
||||
|
||||
/*
|
||||
* Configures PHY autoneg and flow control advertisement settings
|
||||
* hw - Struct containing variables accessed by shared code
|
||||
*/
|
||||
s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw)
|
||||
{
|
||||
s32 ret_val;
|
||||
s16 mii_autoneg_adv_reg;
|
||||
s16 mii_1000t_ctrl_reg;
|
||||
|
||||
/* Read the MII Auto-Neg Advertisement Register (Address 4). */
|
||||
mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
|
||||
|
||||
/* Read the MII 1000Base-T Control Register (Address 9). */
|
||||
mii_1000t_ctrl_reg = MII_AT001_CR_1000T_DEFAULT_CAP_MASK;
|
||||
|
||||
/*
|
||||
* First we clear all the 10/100 mb speed bits in the Auto-Neg
|
||||
* Advertisement Register (Address 4) and the 1000 mb speed bits in
|
||||
* the 1000Base-T Control Register (Address 9).
|
||||
*/
|
||||
mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
|
||||
mii_1000t_ctrl_reg &= ~MII_AT001_CR_1000T_SPEED_MASK;
|
||||
|
||||
/*
|
||||
* Need to parse media_type and set up
|
||||
* the appropriate PHY registers.
|
||||
*/
|
||||
switch (hw->media_type) {
|
||||
case MEDIA_TYPE_AUTO_SENSOR:
|
||||
mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS |
|
||||
MII_AR_10T_FD_CAPS |
|
||||
MII_AR_100TX_HD_CAPS |
|
||||
MII_AR_100TX_FD_CAPS);
|
||||
mii_1000t_ctrl_reg |= MII_AT001_CR_1000T_FD_CAPS;
|
||||
break;
|
||||
|
||||
case MEDIA_TYPE_1000M_FULL:
|
||||
mii_1000t_ctrl_reg |= MII_AT001_CR_1000T_FD_CAPS;
|
||||
break;
|
||||
|
||||
case MEDIA_TYPE_100M_FULL:
|
||||
mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
|
||||
break;
|
||||
|
||||
case MEDIA_TYPE_100M_HALF:
|
||||
mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
|
||||
break;
|
||||
|
||||
case MEDIA_TYPE_10M_FULL:
|
||||
mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
|
||||
break;
|
||||
|
||||
default:
|
||||
mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
|
||||
break;
|
||||
}
|
||||
|
||||
/* flow control fixed to enable all */
|
||||
mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
|
||||
|
||||
hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
|
||||
hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
|
||||
|
||||
ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
|
||||
ret_val = atl1_write_phy_reg(hw, MII_AT001_CR, mii_1000t_ctrl_reg);
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
|
||||
return ATL1_SUCCESS;
|
||||
}
|
||||
|
||||
/*
|
||||
* Configures link settings.
|
||||
* hw - Struct containing variables accessed by shared code
|
||||
* Assumes the hardware has previously been reset and the
|
||||
* transmitter and receiver are not enabled.
|
||||
*/
|
||||
static s32 atl1_setup_link(struct atl1_hw *hw)
|
||||
{
|
||||
struct pci_dev *pdev = hw->back->pdev;
|
||||
s32 ret_val;
|
||||
|
||||
/*
|
||||
* Options:
|
||||
* PHY will advertise value(s) parsed from
|
||||
* autoneg_advertised and fc
|
||||
* no matter what autoneg is , We will not wait link result.
|
||||
*/
|
||||
ret_val = atl1_phy_setup_autoneg_adv(hw);
|
||||
if (ret_val) {
|
||||
dev_dbg(&pdev->dev, "error setting up autonegotiation\n");
|
||||
return ret_val;
|
||||
}
|
||||
/* SW.Reset , En-Auto-Neg if needed */
|
||||
ret_val = atl1_phy_reset(hw);
|
||||
if (ret_val) {
|
||||
dev_dbg(&pdev->dev, "error resetting phy\n");
|
||||
return ret_val;
|
||||
}
|
||||
hw->phy_configured = true;
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
static struct atl1_spi_flash_dev flash_table[] = {
|
||||
/* MFR_NAME WRSR READ PRGM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */
|
||||
{"Atmel", 0x00, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62},
|
||||
{"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60},
|
||||
{"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7},
|
||||
};
|
||||
|
||||
static void atl1_init_flash_opcode(struct atl1_hw *hw)
|
||||
{
|
||||
if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
|
||||
hw->flash_vendor = 0; /* ATMEL */
|
||||
|
||||
/* Init OP table */
|
||||
iowrite8(flash_table[hw->flash_vendor].cmd_program,
|
||||
hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM);
|
||||
iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase,
|
||||
hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE);
|
||||
iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase,
|
||||
hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE);
|
||||
iowrite8(flash_table[hw->flash_vendor].cmd_rdid,
|
||||
hw->hw_addr + REG_SPI_FLASH_OP_RDID);
|
||||
iowrite8(flash_table[hw->flash_vendor].cmd_wren,
|
||||
hw->hw_addr + REG_SPI_FLASH_OP_WREN);
|
||||
iowrite8(flash_table[hw->flash_vendor].cmd_rdsr,
|
||||
hw->hw_addr + REG_SPI_FLASH_OP_RDSR);
|
||||
iowrite8(flash_table[hw->flash_vendor].cmd_wrsr,
|
||||
hw->hw_addr + REG_SPI_FLASH_OP_WRSR);
|
||||
iowrite8(flash_table[hw->flash_vendor].cmd_read,
|
||||
hw->hw_addr + REG_SPI_FLASH_OP_READ);
|
||||
}
|
||||
|
||||
/*
|
||||
* Performs basic configuration of the adapter.
|
||||
* hw - Struct containing variables accessed by shared code
|
||||
* Assumes that the controller has previously been reset and is in a
|
||||
* post-reset uninitialized state. Initializes multicast table,
|
||||
* and Calls routines to setup link
|
||||
* Leaves the transmit and receive units disabled and uninitialized.
|
||||
*/
|
||||
s32 atl1_init_hw(struct atl1_hw *hw)
|
||||
{
|
||||
u32 ret_val = 0;
|
||||
|
||||
/* Zero out the Multicast HASH table */
|
||||
iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
|
||||
/* clear the old settings from the multicast hash table */
|
||||
iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
|
||||
|
||||
atl1_init_flash_opcode(hw);
|
||||
|
||||
if (!hw->phy_configured) {
|
||||
/* enable GPHY LinkChange Interrrupt */
|
||||
ret_val = atl1_write_phy_reg(hw, 18, 0xC00);
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
/* make PHY out of power-saving state */
|
||||
ret_val = atl1_phy_leave_power_saving(hw);
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
/* Call a subroutine to configure the link */
|
||||
ret_val = atl1_setup_link(hw);
|
||||
}
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/*
|
||||
* Detects the current speed and duplex settings of the hardware.
|
||||
* hw - Struct containing variables accessed by shared code
|
||||
* speed - Speed of the connection
|
||||
* duplex - Duplex setting of the connection
|
||||
*/
|
||||
s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex)
|
||||
{
|
||||
struct pci_dev *pdev = hw->back->pdev;
|
||||
s32 ret_val;
|
||||
u16 phy_data;
|
||||
|
||||
/* ; --- Read PHY Specific Status Register (17) */
|
||||
ret_val = atl1_read_phy_reg(hw, MII_AT001_PSSR, &phy_data);
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
|
||||
if (!(phy_data & MII_AT001_PSSR_SPD_DPLX_RESOLVED))
|
||||
return ATL1_ERR_PHY_RES;
|
||||
|
||||
switch (phy_data & MII_AT001_PSSR_SPEED) {
|
||||
case MII_AT001_PSSR_1000MBS:
|
||||
*speed = SPEED_1000;
|
||||
break;
|
||||
case MII_AT001_PSSR_100MBS:
|
||||
*speed = SPEED_100;
|
||||
break;
|
||||
case MII_AT001_PSSR_10MBS:
|
||||
*speed = SPEED_10;
|
||||
break;
|
||||
default:
|
||||
dev_dbg(&pdev->dev, "error getting speed\n");
|
||||
return ATL1_ERR_PHY_SPEED;
|
||||
break;
|
||||
}
|
||||
if (phy_data & MII_AT001_PSSR_DPLX)
|
||||
*duplex = FULL_DUPLEX;
|
||||
else
|
||||
*duplex = HALF_DUPLEX;
|
||||
|
||||
return ATL1_SUCCESS;
|
||||
}
|
||||
|
||||
void atl1_set_mac_addr(struct atl1_hw *hw)
|
||||
{
|
||||
u32 value;
|
||||
/*
|
||||
* 00-0B-6A-F6-00-DC
|
||||
* 0: 6AF600DC 1: 000B
|
||||
* low dword
|
||||
*/
|
||||
value = (((u32) hw->mac_addr[2]) << 24) |
|
||||
(((u32) hw->mac_addr[3]) << 16) |
|
||||
(((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5]));
|
||||
iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
|
||||
/* high dword */
|
||||
value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
|
||||
iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2));
|
||||
}
|
|
@ -1,946 +0,0 @@
|
|||
/*
|
||||
* Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
|
||||
* Copyright(c) 2006 Chris Snook <csnook@redhat.com>
|
||||
* Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
|
||||
*
|
||||
* Derived from Intel e1000 driver
|
||||
* Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59
|
||||
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*
|
||||
* There are a lot of defines in here that are unused and/or have cryptic
|
||||
* names. Please leave them alone, as they're the closest thing we have
|
||||
* to a spec from Attansic at present. *ahem* -- CHS
|
||||
*/
|
||||
|
||||
#ifndef _ATL1_HW_H_
|
||||
#define _ATL1_HW_H_
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/mii.h>
|
||||
|
||||
struct atl1_adapter;
|
||||
struct atl1_hw;
|
||||
|
||||
/* function prototypes needed by multiple files */
|
||||
s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw);
|
||||
s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data);
|
||||
s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex);
|
||||
s32 atl1_read_mac_addr(struct atl1_hw *hw);
|
||||
s32 atl1_init_hw(struct atl1_hw *hw);
|
||||
s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex);
|
||||
s32 atl1_set_speed_and_duplex(struct atl1_hw *hw, u16 speed, u16 duplex);
|
||||
u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr);
|
||||
void atl1_hash_set(struct atl1_hw *hw, u32 hash_value);
|
||||
s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data);
|
||||
void atl1_set_mac_addr(struct atl1_hw *hw);
|
||||
s32 atl1_phy_enter_power_saving(struct atl1_hw *hw);
|
||||
s32 atl1_reset_hw(struct atl1_hw *hw);
|
||||
void atl1_check_options(struct atl1_adapter *adapter);
|
||||
|
||||
/* register definitions */
|
||||
#define REG_PCIE_CAP_LIST 0x58
|
||||
|
||||
#define REG_VPD_CAP 0x6C
|
||||
#define VPD_CAP_ID_MASK 0xff
|
||||
#define VPD_CAP_ID_SHIFT 0
|
||||
#define VPD_CAP_NEXT_PTR_MASK 0xFF
|
||||
#define VPD_CAP_NEXT_PTR_SHIFT 8
|
||||
#define VPD_CAP_VPD_ADDR_MASK 0x7FFF
|
||||
#define VPD_CAP_VPD_ADDR_SHIFT 16
|
||||
#define VPD_CAP_VPD_FLAG 0x80000000
|
||||
|
||||
#define REG_VPD_DATA 0x70
|
||||
|
||||
#define REG_SPI_FLASH_CTRL 0x200
|
||||
#define SPI_FLASH_CTRL_STS_NON_RDY 0x1
|
||||
#define SPI_FLASH_CTRL_STS_WEN 0x2
|
||||
#define SPI_FLASH_CTRL_STS_WPEN 0x80
|
||||
#define SPI_FLASH_CTRL_DEV_STS_MASK 0xFF
|
||||
#define SPI_FLASH_CTRL_DEV_STS_SHIFT 0
|
||||
#define SPI_FLASH_CTRL_INS_MASK 0x7
|
||||
#define SPI_FLASH_CTRL_INS_SHIFT 8
|
||||
#define SPI_FLASH_CTRL_START 0x800
|
||||
#define SPI_FLASH_CTRL_EN_VPD 0x2000
|
||||
#define SPI_FLASH_CTRL_LDSTART 0x8000
|
||||
#define SPI_FLASH_CTRL_CS_HI_MASK 0x3
|
||||
#define SPI_FLASH_CTRL_CS_HI_SHIFT 16
|
||||
#define SPI_FLASH_CTRL_CS_HOLD_MASK 0x3
|
||||
#define SPI_FLASH_CTRL_CS_HOLD_SHIFT 18
|
||||
#define SPI_FLASH_CTRL_CLK_LO_MASK 0x3
|
||||
#define SPI_FLASH_CTRL_CLK_LO_SHIFT 20
|
||||
#define SPI_FLASH_CTRL_CLK_HI_MASK 0x3
|
||||
#define SPI_FLASH_CTRL_CLK_HI_SHIFT 22
|
||||
#define SPI_FLASH_CTRL_CS_SETUP_MASK 0x3
|
||||
#define SPI_FLASH_CTRL_CS_SETUP_SHIFT 24
|
||||
#define SPI_FLASH_CTRL_EROM_PGSZ_MASK 0x3
|
||||
#define SPI_FLASH_CTRL_EROM_PGSZ_SHIFT 26
|
||||
#define SPI_FLASH_CTRL_WAIT_READY 0x10000000
|
||||
|
||||
#define REG_SPI_ADDR 0x204
|
||||
|
||||
#define REG_SPI_DATA 0x208
|
||||
|
||||
#define REG_SPI_FLASH_CONFIG 0x20C
|
||||
#define SPI_FLASH_CONFIG_LD_ADDR_MASK 0xFFFFFF
|
||||
#define SPI_FLASH_CONFIG_LD_ADDR_SHIFT 0
|
||||
#define SPI_FLASH_CONFIG_VPD_ADDR_MASK 0x3
|
||||
#define SPI_FLASH_CONFIG_VPD_ADDR_SHIFT 24
|
||||
#define SPI_FLASH_CONFIG_LD_EXIST 0x4000000
|
||||
|
||||
#define REG_SPI_FLASH_OP_PROGRAM 0x210
|
||||
#define REG_SPI_FLASH_OP_SC_ERASE 0x211
|
||||
#define REG_SPI_FLASH_OP_CHIP_ERASE 0x212
|
||||
#define REG_SPI_FLASH_OP_RDID 0x213
|
||||
#define REG_SPI_FLASH_OP_WREN 0x214
|
||||
#define REG_SPI_FLASH_OP_RDSR 0x215
|
||||
#define REG_SPI_FLASH_OP_WRSR 0x216
|
||||
#define REG_SPI_FLASH_OP_READ 0x217
|
||||
|
||||
#define REG_TWSI_CTRL 0x218
|
||||
#define TWSI_CTRL_LD_OFFSET_MASK 0xFF
|
||||
#define TWSI_CTRL_LD_OFFSET_SHIFT 0
|
||||
#define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7
|
||||
#define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8
|
||||
#define TWSI_CTRL_SW_LDSTART 0x800
|
||||
#define TWSI_CTRL_HW_LDSTART 0x1000
|
||||
#define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x7F
|
||||
#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15
|
||||
#define TWSI_CTRL_LD_EXIST 0x400000
|
||||
#define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3
|
||||
#define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23
|
||||
#define TWSI_CTRL_FREQ_SEL_100K 0
|
||||
#define TWSI_CTRL_FREQ_SEL_200K 1
|
||||
#define TWSI_CTRL_FREQ_SEL_300K 2
|
||||
#define TWSI_CTRL_FREQ_SEL_400K 3
|
||||
#define TWSI_CTRL_SMB_SLV_ADDR
|
||||
#define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3
|
||||
#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24
|
||||
|
||||
#define REG_PCIE_DEV_MISC_CTRL 0x21C
|
||||
#define PCIE_DEV_MISC_CTRL_EXT_PIPE 0x2
|
||||
#define PCIE_DEV_MISC_CTRL_RETRY_BUFDIS 0x1
|
||||
#define PCIE_DEV_MISC_CTRL_SPIROM_EXIST 0x4
|
||||
#define PCIE_DEV_MISC_CTRL_SERDES_ENDIAN 0x8
|
||||
#define PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN 0x10
|
||||
|
||||
/* Selene Master Control Register */
|
||||
#define REG_MASTER_CTRL 0x1400
|
||||
#define MASTER_CTRL_SOFT_RST 0x1
|
||||
#define MASTER_CTRL_MTIMER_EN 0x2
|
||||
#define MASTER_CTRL_ITIMER_EN 0x4
|
||||
#define MASTER_CTRL_MANUAL_INT 0x8
|
||||
#define MASTER_CTRL_REV_NUM_SHIFT 16
|
||||
#define MASTER_CTRL_REV_NUM_MASK 0xff
|
||||
#define MASTER_CTRL_DEV_ID_SHIFT 24
|
||||
#define MASTER_CTRL_DEV_ID_MASK 0xff
|
||||
|
||||
/* Timer Initial Value Register */
|
||||
#define REG_MANUAL_TIMER_INIT 0x1404
|
||||
|
||||
/* IRQ ModeratorTimer Initial Value Register */
|
||||
#define REG_IRQ_MODU_TIMER_INIT 0x1408
|
||||
|
||||
#define REG_GPHY_ENABLE 0x140C
|
||||
|
||||
/* IRQ Anti-Lost Timer Initial Value Register */
|
||||
#define REG_CMBDISDMA_TIMER 0x140E
|
||||
|
||||
/* Block IDLE Status Register */
|
||||
#define REG_IDLE_STATUS 0x1410
|
||||
#define IDLE_STATUS_RXMAC 1
|
||||
#define IDLE_STATUS_TXMAC 2
|
||||
#define IDLE_STATUS_RXQ 4
|
||||
#define IDLE_STATUS_TXQ 8
|
||||
#define IDLE_STATUS_DMAR 0x10
|
||||
#define IDLE_STATUS_DMAW 0x20
|
||||
#define IDLE_STATUS_SMB 0x40
|
||||
#define IDLE_STATUS_CMB 0x80
|
||||
|
||||
/* MDIO Control Register */
|
||||
#define REG_MDIO_CTRL 0x1414
|
||||
#define MDIO_DATA_MASK 0xffff
|
||||
#define MDIO_DATA_SHIFT 0
|
||||
#define MDIO_REG_ADDR_MASK 0x1f
|
||||
#define MDIO_REG_ADDR_SHIFT 16
|
||||
#define MDIO_RW 0x200000
|
||||
#define MDIO_SUP_PREAMBLE 0x400000
|
||||
#define MDIO_START 0x800000
|
||||
#define MDIO_CLK_SEL_SHIFT 24
|
||||
#define MDIO_CLK_25_4 0
|
||||
#define MDIO_CLK_25_6 2
|
||||
#define MDIO_CLK_25_8 3
|
||||
#define MDIO_CLK_25_10 4
|
||||
#define MDIO_CLK_25_14 5
|
||||
#define MDIO_CLK_25_20 6
|
||||
#define MDIO_CLK_25_28 7
|
||||
#define MDIO_BUSY 0x8000000
|
||||
#define MDIO_WAIT_TIMES 30
|
||||
|
||||
/* MII PHY Status Register */
|
||||
#define REG_PHY_STATUS 0x1418
|
||||
|
||||
/* BIST Control and Status Register0 (for the Packet Memory) */
|
||||
#define REG_BIST0_CTRL 0x141c
|
||||
#define BIST0_NOW 0x1
|
||||
#define BIST0_SRAM_FAIL 0x2
|
||||
#define BIST0_FUSE_FLAG 0x4
|
||||
#define REG_BIST1_CTRL 0x1420
|
||||
#define BIST1_NOW 0x1
|
||||
#define BIST1_SRAM_FAIL 0x2
|
||||
#define BIST1_FUSE_FLAG 0x4
|
||||
|
||||
/* MAC Control Register */
|
||||
#define REG_MAC_CTRL 0x1480
|
||||
#define MAC_CTRL_TX_EN 1
|
||||
#define MAC_CTRL_RX_EN 2
|
||||
#define MAC_CTRL_TX_FLOW 4
|
||||
#define MAC_CTRL_RX_FLOW 8
|
||||
#define MAC_CTRL_LOOPBACK 0x10
|
||||
#define MAC_CTRL_DUPLX 0x20
|
||||
#define MAC_CTRL_ADD_CRC 0x40
|
||||
#define MAC_CTRL_PAD 0x80
|
||||
#define MAC_CTRL_LENCHK 0x100
|
||||
#define MAC_CTRL_HUGE_EN 0x200
|
||||
#define MAC_CTRL_PRMLEN_SHIFT 10
|
||||
#define MAC_CTRL_PRMLEN_MASK 0xf
|
||||
#define MAC_CTRL_RMV_VLAN 0x4000
|
||||
#define MAC_CTRL_PROMIS_EN 0x8000
|
||||
#define MAC_CTRL_TX_PAUSE 0x10000
|
||||
#define MAC_CTRL_SCNT 0x20000
|
||||
#define MAC_CTRL_SRST_TX 0x40000
|
||||
#define MAC_CTRL_TX_SIMURST 0x80000
|
||||
#define MAC_CTRL_SPEED_SHIFT 20
|
||||
#define MAC_CTRL_SPEED_MASK 0x300000
|
||||
#define MAC_CTRL_SPEED_1000 2
|
||||
#define MAC_CTRL_SPEED_10_100 1
|
||||
#define MAC_CTRL_DBG_TX_BKPRESURE 0x400000
|
||||
#define MAC_CTRL_TX_HUGE 0x800000
|
||||
#define MAC_CTRL_RX_CHKSUM_EN 0x1000000
|
||||
#define MAC_CTRL_MC_ALL_EN 0x2000000
|
||||
#define MAC_CTRL_BC_EN 0x4000000
|
||||
#define MAC_CTRL_DBG 0x8000000
|
||||
|
||||
/* MAC IPG/IFG Control Register */
|
||||
#define REG_MAC_IPG_IFG 0x1484
|
||||
#define MAC_IPG_IFG_IPGT_SHIFT 0
|
||||
#define MAC_IPG_IFG_IPGT_MASK 0x7f
|
||||
#define MAC_IPG_IFG_MIFG_SHIFT 8
|
||||
#define MAC_IPG_IFG_MIFG_MASK 0xff
|
||||
#define MAC_IPG_IFG_IPGR1_SHIFT 16
|
||||
#define MAC_IPG_IFG_IPGR1_MASK 0x7f
|
||||
#define MAC_IPG_IFG_IPGR2_SHIFT 24
|
||||
#define MAC_IPG_IFG_IPGR2_MASK 0x7f
|
||||
|
||||
/* MAC STATION ADDRESS */
|
||||
#define REG_MAC_STA_ADDR 0x1488
|
||||
|
||||
/* Hash table for multicast address */
|
||||
#define REG_RX_HASH_TABLE 0x1490
|
||||
|
||||
/* MAC Half-Duplex Control Register */
|
||||
#define REG_MAC_HALF_DUPLX_CTRL 0x1498
|
||||
#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0
|
||||
#define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff
|
||||
#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12
|
||||
#define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf
|
||||
#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000
|
||||
#define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000
|
||||
#define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000
|
||||
#define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000
|
||||
#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20
|
||||
#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf
|
||||
#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24
|
||||
#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf
|
||||
|
||||
/* Maximum Frame Length Control Register */
|
||||
#define REG_MTU 0x149c
|
||||
|
||||
/* Wake-On-Lan control register */
|
||||
#define REG_WOL_CTRL 0x14a0
|
||||
#define WOL_PATTERN_EN 0x00000001
|
||||
#define WOL_PATTERN_PME_EN 0x00000002
|
||||
#define WOL_MAGIC_EN 0x00000004
|
||||
#define WOL_MAGIC_PME_EN 0x00000008
|
||||
#define WOL_LINK_CHG_EN 0x00000010
|
||||
#define WOL_LINK_CHG_PME_EN 0x00000020
|
||||
#define WOL_PATTERN_ST 0x00000100
|
||||
#define WOL_MAGIC_ST 0x00000200
|
||||
#define WOL_LINKCHG_ST 0x00000400
|
||||
#define WOL_CLK_SWITCH_EN 0x00008000
|
||||
#define WOL_PT0_EN 0x00010000
|
||||
#define WOL_PT1_EN 0x00020000
|
||||
#define WOL_PT2_EN 0x00040000
|
||||
#define WOL_PT3_EN 0x00080000
|
||||
#define WOL_PT4_EN 0x00100000
|
||||
#define WOL_PT5_EN 0x00200000
|
||||
#define WOL_PT6_EN 0x00400000
|
||||
|
||||
/* WOL Length ( 2 DWORD ) */
|
||||
#define REG_WOL_PATTERN_LEN 0x14a4
|
||||
#define WOL_PT_LEN_MASK 0x7f
|
||||
#define WOL_PT0_LEN_SHIFT 0
|
||||
#define WOL_PT1_LEN_SHIFT 8
|
||||
#define WOL_PT2_LEN_SHIFT 16
|
||||
#define WOL_PT3_LEN_SHIFT 24
|
||||
#define WOL_PT4_LEN_SHIFT 0
|
||||
#define WOL_PT5_LEN_SHIFT 8
|
||||
#define WOL_PT6_LEN_SHIFT 16
|
||||
|
||||
/* Internal SRAM Partition Register */
|
||||
#define REG_SRAM_RFD_ADDR 0x1500
|
||||
#define REG_SRAM_RFD_LEN (REG_SRAM_RFD_ADDR+ 4)
|
||||
#define REG_SRAM_RRD_ADDR (REG_SRAM_RFD_ADDR+ 8)
|
||||
#define REG_SRAM_RRD_LEN (REG_SRAM_RFD_ADDR+12)
|
||||
#define REG_SRAM_TPD_ADDR (REG_SRAM_RFD_ADDR+16)
|
||||
#define REG_SRAM_TPD_LEN (REG_SRAM_RFD_ADDR+20)
|
||||
#define REG_SRAM_TRD_ADDR (REG_SRAM_RFD_ADDR+24)
|
||||
#define REG_SRAM_TRD_LEN (REG_SRAM_RFD_ADDR+28)
|
||||
#define REG_SRAM_RXF_ADDR (REG_SRAM_RFD_ADDR+32)
|
||||
#define REG_SRAM_RXF_LEN (REG_SRAM_RFD_ADDR+36)
|
||||
#define REG_SRAM_TXF_ADDR (REG_SRAM_RFD_ADDR+40)
|
||||
#define REG_SRAM_TXF_LEN (REG_SRAM_RFD_ADDR+44)
|
||||
#define REG_SRAM_TCPH_PATH_ADDR (REG_SRAM_RFD_ADDR+48)
|
||||
#define SRAM_TCPH_ADDR_MASK 0x0fff
|
||||
#define SRAM_TCPH_ADDR_SHIFT 0
|
||||
#define SRAM_PATH_ADDR_MASK 0x0fff
|
||||
#define SRAM_PATH_ADDR_SHIFT 16
|
||||
|
||||
/* Load Ptr Register */
|
||||
#define REG_LOAD_PTR (REG_SRAM_RFD_ADDR+52)
|
||||
|
||||
/* Descriptor Control register */
|
||||
#define REG_DESC_BASE_ADDR_HI 0x1540
|
||||
#define REG_DESC_RFD_ADDR_LO (REG_DESC_BASE_ADDR_HI+4)
|
||||
#define REG_DESC_RRD_ADDR_LO (REG_DESC_BASE_ADDR_HI+8)
|
||||
#define REG_DESC_TPD_ADDR_LO (REG_DESC_BASE_ADDR_HI+12)
|
||||
#define REG_DESC_CMB_ADDR_LO (REG_DESC_BASE_ADDR_HI+16)
|
||||
#define REG_DESC_SMB_ADDR_LO (REG_DESC_BASE_ADDR_HI+20)
|
||||
#define REG_DESC_RFD_RRD_RING_SIZE (REG_DESC_BASE_ADDR_HI+24)
|
||||
#define DESC_RFD_RING_SIZE_MASK 0x7ff
|
||||
#define DESC_RFD_RING_SIZE_SHIFT 0
|
||||
#define DESC_RRD_RING_SIZE_MASK 0x7ff
|
||||
#define DESC_RRD_RING_SIZE_SHIFT 16
|
||||
#define REG_DESC_TPD_RING_SIZE (REG_DESC_BASE_ADDR_HI+28)
|
||||
#define DESC_TPD_RING_SIZE_MASK 0x3ff
|
||||
#define DESC_TPD_RING_SIZE_SHIFT 0
|
||||
|
||||
/* TXQ Control Register */
|
||||
#define REG_TXQ_CTRL 0x1580
|
||||
#define TXQ_CTRL_TPD_BURST_NUM_SHIFT 0
|
||||
#define TXQ_CTRL_TPD_BURST_NUM_MASK 0x1f
|
||||
#define TXQ_CTRL_EN 0x20
|
||||
#define TXQ_CTRL_ENH_MODE 0x40
|
||||
#define TXQ_CTRL_TPD_FETCH_TH_SHIFT 8
|
||||
#define TXQ_CTRL_TPD_FETCH_TH_MASK 0x3f
|
||||
#define TXQ_CTRL_TXF_BURST_NUM_SHIFT 16
|
||||
#define TXQ_CTRL_TXF_BURST_NUM_MASK 0xffff
|
||||
|
||||
/* Jumbo packet Threshold for task offload */
|
||||
#define REG_TX_JUMBO_TASK_TH_TPD_IPG 0x1584
|
||||
#define TX_JUMBO_TASK_TH_MASK 0x7ff
|
||||
#define TX_JUMBO_TASK_TH_SHIFT 0
|
||||
#define TX_TPD_MIN_IPG_MASK 0x1f
|
||||
#define TX_TPD_MIN_IPG_SHIFT 16
|
||||
|
||||
/* RXQ Control Register */
|
||||
#define REG_RXQ_CTRL 0x15a0
|
||||
#define RXQ_CTRL_RFD_BURST_NUM_SHIFT 0
|
||||
#define RXQ_CTRL_RFD_BURST_NUM_MASK 0xff
|
||||
#define RXQ_CTRL_RRD_BURST_THRESH_SHIFT 8
|
||||
#define RXQ_CTRL_RRD_BURST_THRESH_MASK 0xff
|
||||
#define RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT 16
|
||||
#define RXQ_CTRL_RFD_PREF_MIN_IPG_MASK 0x1f
|
||||
#define RXQ_CTRL_CUT_THRU_EN 0x40000000
|
||||
#define RXQ_CTRL_EN 0x80000000
|
||||
|
||||
/* Rx jumbo packet threshold and rrd retirement timer */
|
||||
#define REG_RXQ_JMBOSZ_RRDTIM (REG_RXQ_CTRL+ 4)
|
||||
#define RXQ_JMBOSZ_TH_MASK 0x7ff
|
||||
#define RXQ_JMBOSZ_TH_SHIFT 0
|
||||
#define RXQ_JMBO_LKAH_MASK 0xf
|
||||
#define RXQ_JMBO_LKAH_SHIFT 11
|
||||
#define RXQ_RRD_TIMER_MASK 0xffff
|
||||
#define RXQ_RRD_TIMER_SHIFT 16
|
||||
|
||||
/* RFD flow control register */
|
||||
#define REG_RXQ_RXF_PAUSE_THRESH (REG_RXQ_CTRL+ 8)
|
||||
#define RXQ_RXF_PAUSE_TH_HI_SHIFT 16
|
||||
#define RXQ_RXF_PAUSE_TH_HI_MASK 0xfff
|
||||
#define RXQ_RXF_PAUSE_TH_LO_SHIFT 0
|
||||
#define RXQ_RXF_PAUSE_TH_LO_MASK 0xfff
|
||||
|
||||
/* RRD flow control register */
|
||||
#define REG_RXQ_RRD_PAUSE_THRESH (REG_RXQ_CTRL+12)
|
||||
#define RXQ_RRD_PAUSE_TH_HI_SHIFT 0
|
||||
#define RXQ_RRD_PAUSE_TH_HI_MASK 0xfff
|
||||
#define RXQ_RRD_PAUSE_TH_LO_SHIFT 16
|
||||
#define RXQ_RRD_PAUSE_TH_LO_MASK 0xfff
|
||||
|
||||
/* DMA Engine Control Register */
|
||||
#define REG_DMA_CTRL 0x15c0
|
||||
#define DMA_CTRL_DMAR_IN_ORDER 0x1
|
||||
#define DMA_CTRL_DMAR_ENH_ORDER 0x2
|
||||
#define DMA_CTRL_DMAR_OUT_ORDER 0x4
|
||||
#define DMA_CTRL_RCB_VALUE 0x8
|
||||
#define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4
|
||||
#define DMA_CTRL_DMAR_BURST_LEN_MASK 7
|
||||
#define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7
|
||||
#define DMA_CTRL_DMAW_BURST_LEN_MASK 7
|
||||
#define DMA_CTRL_DMAR_EN 0x400
|
||||
#define DMA_CTRL_DMAW_EN 0x800
|
||||
|
||||
/* CMB/SMB Control Register */
|
||||
#define REG_CSMB_CTRL 0x15d0
|
||||
#define CSMB_CTRL_CMB_NOW 1
|
||||
#define CSMB_CTRL_SMB_NOW 2
|
||||
#define CSMB_CTRL_CMB_EN 4
|
||||
#define CSMB_CTRL_SMB_EN 8
|
||||
|
||||
/* CMB DMA Write Threshold Register */
|
||||
#define REG_CMB_WRITE_TH (REG_CSMB_CTRL+ 4)
|
||||
#define CMB_RRD_TH_SHIFT 0
|
||||
#define CMB_RRD_TH_MASK 0x7ff
|
||||
#define CMB_TPD_TH_SHIFT 16
|
||||
#define CMB_TPD_TH_MASK 0x7ff
|
||||
|
||||
/* RX/TX count-down timer to trigger CMB-write. 2us resolution. */
|
||||
#define REG_CMB_WRITE_TIMER (REG_CSMB_CTRL+ 8)
|
||||
#define CMB_RX_TM_SHIFT 0
|
||||
#define CMB_RX_TM_MASK 0xffff
|
||||
#define CMB_TX_TM_SHIFT 16
|
||||
#define CMB_TX_TM_MASK 0xffff
|
||||
|
||||
/* Number of packet received since last CMB write */
|
||||
#define REG_CMB_RX_PKT_CNT (REG_CSMB_CTRL+12)
|
||||
|
||||
/* Number of packet transmitted since last CMB write */
|
||||
#define REG_CMB_TX_PKT_CNT (REG_CSMB_CTRL+16)
|
||||
|
||||
/* SMB auto DMA timer register */
|
||||
#define REG_SMB_TIMER (REG_CSMB_CTRL+20)
|
||||
|
||||
/* Mailbox Register */
|
||||
#define REG_MAILBOX 0x15f0
|
||||
#define MB_RFD_PROD_INDX_SHIFT 0
|
||||
#define MB_RFD_PROD_INDX_MASK 0x7ff
|
||||
#define MB_RRD_CONS_INDX_SHIFT 11
|
||||
#define MB_RRD_CONS_INDX_MASK 0x7ff
|
||||
#define MB_TPD_PROD_INDX_SHIFT 22
|
||||
#define MB_TPD_PROD_INDX_MASK 0x3ff
|
||||
|
||||
/* Interrupt Status Register */
|
||||
#define REG_ISR 0x1600
|
||||
#define ISR_SMB 1
|
||||
#define ISR_TIMER 2
|
||||
#define ISR_MANUAL 4
|
||||
#define ISR_RXF_OV 8
|
||||
#define ISR_RFD_UNRUN 0x10
|
||||
#define ISR_RRD_OV 0x20
|
||||
#define ISR_TXF_UNRUN 0x40
|
||||
#define ISR_LINK 0x80
|
||||
#define ISR_HOST_RFD_UNRUN 0x100
|
||||
#define ISR_HOST_RRD_OV 0x200
|
||||
#define ISR_DMAR_TO_RST 0x400
|
||||
#define ISR_DMAW_TO_RST 0x800
|
||||
#define ISR_GPHY 0x1000
|
||||
#define ISR_RX_PKT 0x10000
|
||||
#define ISR_TX_PKT 0x20000
|
||||
#define ISR_TX_DMA 0x40000
|
||||
#define ISR_RX_DMA 0x80000
|
||||
#define ISR_CMB_RX 0x100000
|
||||
#define ISR_CMB_TX 0x200000
|
||||
#define ISR_MAC_RX 0x400000
|
||||
#define ISR_MAC_TX 0x800000
|
||||
#define ISR_UR_DETECTED 0x1000000
|
||||
#define ISR_FERR_DETECTED 0x2000000
|
||||
#define ISR_NFERR_DETECTED 0x4000000
|
||||
#define ISR_CERR_DETECTED 0x8000000
|
||||
#define ISR_PHY_LINKDOWN 0x10000000
|
||||
#define ISR_DIS_SMB 0x20000000
|
||||
#define ISR_DIS_DMA 0x40000000
|
||||
#define ISR_DIS_INT 0x80000000
|
||||
|
||||
/* Interrupt Mask Register */
|
||||
#define REG_IMR 0x1604
|
||||
|
||||
/* Normal Interrupt mask */
|
||||
#define IMR_NORMAL_MASK (\
|
||||
ISR_SMB |\
|
||||
ISR_GPHY |\
|
||||
ISR_PHY_LINKDOWN|\
|
||||
ISR_DMAR_TO_RST |\
|
||||
ISR_DMAW_TO_RST |\
|
||||
ISR_CMB_TX |\
|
||||
ISR_CMB_RX )
|
||||
|
||||
/* Debug Interrupt Mask (enable all interrupt) */
|
||||
#define IMR_DEBUG_MASK (\
|
||||
ISR_SMB |\
|
||||
ISR_TIMER |\
|
||||
ISR_MANUAL |\
|
||||
ISR_RXF_OV |\
|
||||
ISR_RFD_UNRUN |\
|
||||
ISR_RRD_OV |\
|
||||
ISR_TXF_UNRUN |\
|
||||
ISR_LINK |\
|
||||
ISR_CMB_TX |\
|
||||
ISR_CMB_RX |\
|
||||
ISR_RX_PKT |\
|
||||
ISR_TX_PKT |\
|
||||
ISR_MAC_RX |\
|
||||
ISR_MAC_TX )
|
||||
|
||||
/* Interrupt Status Register */
|
||||
#define REG_RFD_RRD_IDX 0x1800
|
||||
#define REG_TPD_IDX 0x1804
|
||||
|
||||
/* MII definition */
|
||||
/* PHY Common Register */
|
||||
#define MII_AT001_CR 0x09
|
||||
#define MII_AT001_SR 0x0A
|
||||
#define MII_AT001_ESR 0x0F
|
||||
#define MII_AT001_PSCR 0x10
|
||||
#define MII_AT001_PSSR 0x11
|
||||
|
||||
/* PHY Control Register */
|
||||
#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
|
||||
#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
|
||||
#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
|
||||
#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
|
||||
#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
|
||||
#define MII_CR_POWER_DOWN 0x0800 /* Power down */
|
||||
#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
|
||||
#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
|
||||
#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
|
||||
#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
|
||||
#define MII_CR_SPEED_MASK 0x2040
|
||||
#define MII_CR_SPEED_1000 0x0040
|
||||
#define MII_CR_SPEED_100 0x2000
|
||||
#define MII_CR_SPEED_10 0x0000
|
||||
|
||||
/* PHY Status Register */
|
||||
#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
|
||||
#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
|
||||
#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
|
||||
#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
|
||||
#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
|
||||
#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
|
||||
#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
|
||||
#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
|
||||
#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
|
||||
#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
|
||||
#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
|
||||
#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
|
||||
#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
|
||||
#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
|
||||
#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
|
||||
|
||||
/* Link partner ability register. */
|
||||
#define MII_LPA_SLCT 0x001f /* Same as advertise selector */
|
||||
#define MII_LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
|
||||
#define MII_LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
|
||||
#define MII_LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
|
||||
#define MII_LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
|
||||
#define MII_LPA_100BASE4 0x0200 /* 100BASE-T4 */
|
||||
#define MII_LPA_PAUSE 0x0400 /* PAUSE */
|
||||
#define MII_LPA_ASYPAUSE 0x0800 /* Asymmetrical PAUSE */
|
||||
#define MII_LPA_RFAULT 0x2000 /* Link partner faulted */
|
||||
#define MII_LPA_LPACK 0x4000 /* Link partner acked us */
|
||||
#define MII_LPA_NPAGE 0x8000 /* Next page bit */
|
||||
|
||||
/* Autoneg Advertisement Register */
|
||||
#define MII_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
|
||||
#define MII_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
|
||||
#define MII_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
|
||||
#define MII_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
|
||||
#define MII_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
|
||||
#define MII_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
|
||||
#define MII_AR_PAUSE 0x0400 /* Pause operation desired */
|
||||
#define MII_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
|
||||
#define MII_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
|
||||
#define MII_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
|
||||
#define MII_AR_SPEED_MASK 0x01E0
|
||||
#define MII_AR_DEFAULT_CAP_MASK 0x0DE0
|
||||
|
||||
/* 1000BASE-T Control Register */
|
||||
#define MII_AT001_CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
|
||||
#define MII_AT001_CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
|
||||
#define MII_AT001_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port, 0=DTE device */
|
||||
#define MII_AT001_CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master, 0=Configure PHY as Slave */
|
||||
#define MII_AT001_CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value, 0=Automatic Master/Slave config */
|
||||
#define MII_AT001_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
|
||||
#define MII_AT001_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
|
||||
#define MII_AT001_CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
|
||||
#define MII_AT001_CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
|
||||
#define MII_AT001_CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
|
||||
#define MII_AT001_CR_1000T_SPEED_MASK 0x0300
|
||||
#define MII_AT001_CR_1000T_DEFAULT_CAP_MASK 0x0300
|
||||
|
||||
/* 1000BASE-T Status Register */
|
||||
#define MII_AT001_SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
|
||||
#define MII_AT001_SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
|
||||
#define MII_AT001_SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
|
||||
#define MII_AT001_SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
|
||||
#define MII_AT001_SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
|
||||
#define MII_AT001_SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
|
||||
#define MII_AT001_SR_1000T_REMOTE_RX_STATUS_SHIFT 12
|
||||
#define MII_AT001_SR_1000T_LOCAL_RX_STATUS_SHIFT 13
|
||||
|
||||
/* Extended Status Register */
|
||||
#define MII_AT001_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
|
||||
#define MII_AT001_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
|
||||
#define MII_AT001_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
|
||||
#define MII_AT001_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
|
||||
|
||||
/* AT001 PHY Specific Control Register */
|
||||
#define MII_AT001_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
|
||||
#define MII_AT001_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
|
||||
#define MII_AT001_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
|
||||
#define MII_AT001_PSCR_MAC_POWERDOWN 0x0008
|
||||
#define MII_AT001_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, 0=CLK125 toggling */
|
||||
#define MII_AT001_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5, Manual MDI configuration */
|
||||
#define MII_AT001_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
|
||||
#define MII_AT001_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
|
||||
#define MII_AT001_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled all speeds. */
|
||||
#define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE 0x0080 /* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T RX Threshold), 0=Normal 10BASE-T RX Threshold */
|
||||
#define MII_AT001_PSCR_MII_5BIT_ENABLE 0x0100 /* 1=5-Bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
|
||||
#define MII_AT001_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
|
||||
#define MII_AT001_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
|
||||
#define MII_AT001_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
|
||||
#define MII_AT001_PSCR_POLARITY_REVERSAL_SHIFT 1
|
||||
#define MII_AT001_PSCR_AUTO_X_MODE_SHIFT 5
|
||||
#define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
|
||||
|
||||
/* AT001 PHY Specific Status Register */
|
||||
#define MII_AT001_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
|
||||
#define MII_AT001_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
|
||||
#define MII_AT001_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
|
||||
#define MII_AT001_PSSR_10MBS 0x0000 /* 00=10Mbs */
|
||||
#define MII_AT001_PSSR_100MBS 0x4000 /* 01=100Mbs */
|
||||
#define MII_AT001_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
|
||||
|
||||
/* PCI Command Register Bit Definitions */
|
||||
#define PCI_REG_COMMAND 0x04 /* PCI Command Register */
|
||||
#define CMD_IO_SPACE 0x0001
|
||||
#define CMD_MEMORY_SPACE 0x0002
|
||||
#define CMD_BUS_MASTER 0x0004
|
||||
|
||||
/* Wake Up Filter Control */
|
||||
#define ATL1_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
|
||||
#define ATL1_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
|
||||
#define ATL1_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
|
||||
#define ATL1_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */
|
||||
#define ATL1_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
|
||||
|
||||
/* Error Codes */
|
||||
#define ATL1_SUCCESS 0
|
||||
#define ATL1_ERR_EEPROM 1
|
||||
#define ATL1_ERR_PHY 2
|
||||
#define ATL1_ERR_CONFIG 3
|
||||
#define ATL1_ERR_PARAM 4
|
||||
#define ATL1_ERR_MAC_TYPE 5
|
||||
#define ATL1_ERR_PHY_TYPE 6
|
||||
#define ATL1_ERR_PHY_SPEED 7
|
||||
#define ATL1_ERR_PHY_RES 8
|
||||
|
||||
#define SPEED_0 0xffff
|
||||
#define SPEED_10 10
|
||||
#define SPEED_100 100
|
||||
#define SPEED_1000 1000
|
||||
#define HALF_DUPLEX 1
|
||||
#define FULL_DUPLEX 2
|
||||
|
||||
#define MEDIA_TYPE_AUTO_SENSOR 0
|
||||
#define MEDIA_TYPE_1000M_FULL 1
|
||||
#define MEDIA_TYPE_100M_FULL 2
|
||||
#define MEDIA_TYPE_100M_HALF 3
|
||||
#define MEDIA_TYPE_10M_FULL 4
|
||||
#define MEDIA_TYPE_10M_HALF 5
|
||||
|
||||
#define ADVERTISE_10_HALF 0x0001
|
||||
#define ADVERTISE_10_FULL 0x0002
|
||||
#define ADVERTISE_100_HALF 0x0004
|
||||
#define ADVERTISE_100_FULL 0x0008
|
||||
#define ADVERTISE_1000_HALF 0x0010
|
||||
#define ADVERTISE_1000_FULL 0x0020
|
||||
#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
|
||||
#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds */
|
||||
#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds */
|
||||
|
||||
#define MAX_JUMBO_FRAME_SIZE 0x2800
|
||||
|
||||
#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
|
||||
#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
|
||||
|
||||
/* For checksumming , the sum of all words in the EEPROM should equal 0xBABA */
|
||||
#define EEPROM_SUM 0xBABA
|
||||
|
||||
#define ATL1_EEDUMP_LEN 48
|
||||
|
||||
/* Statistics counters collected by the MAC */
|
||||
struct stats_msg_block {
|
||||
/* rx */
|
||||
u32 rx_ok; /* The number of good packet received. */
|
||||
u32 rx_bcast; /* The number of good broadcast packet received. */
|
||||
u32 rx_mcast; /* The number of good multicast packet received. */
|
||||
u32 rx_pause; /* The number of Pause packet received. */
|
||||
u32 rx_ctrl; /* The number of Control packet received other than Pause frame. */
|
||||
u32 rx_fcs_err; /* The number of packets with bad FCS. */
|
||||
u32 rx_len_err; /* The number of packets with mismatch of length field and actual size. */
|
||||
u32 rx_byte_cnt; /* The number of bytes of good packet received. FCS is NOT included. */
|
||||
u32 rx_runt; /* The number of packets received that are less than 64 byte long and with good FCS. */
|
||||
u32 rx_frag; /* The number of packets received that are less than 64 byte long and with bad FCS. */
|
||||
u32 rx_sz_64; /* The number of good and bad packets received that are 64 byte long. */
|
||||
u32 rx_sz_65_127; /* The number of good and bad packets received that are between 65 and 127-byte long. */
|
||||
u32 rx_sz_128_255; /* The number of good and bad packets received that are between 128 and 255-byte long. */
|
||||
u32 rx_sz_256_511; /* The number of good and bad packets received that are between 256 and 511-byte long. */
|
||||
u32 rx_sz_512_1023; /* The number of good and bad packets received that are between 512 and 1023-byte long. */
|
||||
u32 rx_sz_1024_1518; /* The number of good and bad packets received that are between 1024 and 1518-byte long. */
|
||||
u32 rx_sz_1519_max; /* The number of good and bad packets received that are between 1519-byte and MTU. */
|
||||
u32 rx_sz_ov; /* The number of good and bad packets received that are more than MTU size šC truncated by Selene. */
|
||||
u32 rx_rxf_ov; /* The number of frame dropped due to occurrence of RX FIFO overflow. */
|
||||
u32 rx_rrd_ov; /* The number of frame dropped due to occurrence of RRD overflow. */
|
||||
u32 rx_align_err; /* Alignment Error */
|
||||
u32 rx_bcast_byte_cnt; /* The byte count of broadcast packet received, excluding FCS. */
|
||||
u32 rx_mcast_byte_cnt; /* The byte count of multicast packet received, excluding FCS. */
|
||||
u32 rx_err_addr; /* The number of packets dropped due to address filtering. */
|
||||
|
||||
/* tx */
|
||||
u32 tx_ok; /* The number of good packet transmitted. */
|
||||
u32 tx_bcast; /* The number of good broadcast packet transmitted. */
|
||||
u32 tx_mcast; /* The number of good multicast packet transmitted. */
|
||||
u32 tx_pause; /* The number of Pause packet transmitted. */
|
||||
u32 tx_exc_defer; /* The number of packets transmitted with excessive deferral. */
|
||||
u32 tx_ctrl; /* The number of packets transmitted is a control frame, excluding Pause frame. */
|
||||
u32 tx_defer; /* The number of packets transmitted that is deferred. */
|
||||
u32 tx_byte_cnt; /* The number of bytes of data transmitted. FCS is NOT included. */
|
||||
u32 tx_sz_64; /* The number of good and bad packets transmitted that are 64 byte long. */
|
||||
u32 tx_sz_65_127; /* The number of good and bad packets transmitted that are between 65 and 127-byte long. */
|
||||
u32 tx_sz_128_255; /* The number of good and bad packets transmitted that are between 128 and 255-byte long. */
|
||||
u32 tx_sz_256_511; /* The number of good and bad packets transmitted that are between 256 and 511-byte long. */
|
||||
u32 tx_sz_512_1023; /* The number of good and bad packets transmitted that are between 512 and 1023-byte long. */
|
||||
u32 tx_sz_1024_1518; /* The number of good and bad packets transmitted that are between 1024 and 1518-byte long. */
|
||||
u32 tx_sz_1519_max; /* The number of good and bad packets transmitted that are between 1519-byte and MTU. */
|
||||
u32 tx_1_col; /* The number of packets subsequently transmitted successfully with a single prior collision. */
|
||||
u32 tx_2_col; /* The number of packets subsequently transmitted successfully with multiple prior collisions. */
|
||||
u32 tx_late_col; /* The number of packets transmitted with late collisions. */
|
||||
u32 tx_abort_col; /* The number of transmit packets aborted due to excessive collisions. */
|
||||
u32 tx_underrun; /* The number of transmit packets aborted due to transmit FIFO underrun, or TRD FIFO underrun */
|
||||
u32 tx_rd_eop; /* The number of times that read beyond the EOP into the next frame area when TRD was not written timely */
|
||||
u32 tx_len_err; /* The number of transmit packets with length field does NOT match the actual frame size. */
|
||||
u32 tx_trunc; /* The number of transmit packets truncated due to size exceeding MTU. */
|
||||
u32 tx_bcast_byte; /* The byte count of broadcast packet transmitted, excluding FCS. */
|
||||
u32 tx_mcast_byte; /* The byte count of multicast packet transmitted, excluding FCS. */
|
||||
u32 smb_updated; /* 1: SMB Updated. This is used by software as the indication of the statistics update.
|
||||
* Software should clear this bit as soon as retrieving the statistics information. */
|
||||
};
|
||||
|
||||
/* Coalescing Message Block */
|
||||
struct coals_msg_block {
|
||||
u32 int_stats; /* interrupt status */
|
||||
u16 rrd_prod_idx; /* TRD Producer Index. */
|
||||
u16 rfd_cons_idx; /* RFD Consumer Index. */
|
||||
u16 update; /* Selene sets this bit every time it DMA the CMB to host memory.
|
||||
* Software supposes to clear this bit when CMB information is processed. */
|
||||
u16 tpd_cons_idx; /* TPD Consumer Index. */
|
||||
};
|
||||
|
||||
/* RRD descriptor */
|
||||
struct rx_return_desc {
|
||||
u8 num_buf; /* Number of RFD buffers used by the received packet */
|
||||
u8 resved;
|
||||
u16 buf_indx; /* RFD Index of the first buffer */
|
||||
union {
|
||||
u32 valid;
|
||||
struct {
|
||||
u16 rx_chksum;
|
||||
u16 pkt_size;
|
||||
} xsum_sz;
|
||||
} xsz;
|
||||
|
||||
u16 pkt_flg; /* Packet flags */
|
||||
u16 err_flg; /* Error flags */
|
||||
u16 resved2;
|
||||
u16 vlan_tag; /* VLAN TAG */
|
||||
};
|
||||
|
||||
#define PACKET_FLAG_ETH_TYPE 0x0080
|
||||
#define PACKET_FLAG_VLAN_INS 0x0100
|
||||
#define PACKET_FLAG_ERR 0x0200
|
||||
#define PACKET_FLAG_IPV4 0x0400
|
||||
#define PACKET_FLAG_UDP 0x0800
|
||||
#define PACKET_FLAG_TCP 0x1000
|
||||
#define PACKET_FLAG_BCAST 0x2000
|
||||
#define PACKET_FLAG_MCAST 0x4000
|
||||
#define PACKET_FLAG_PAUSE 0x8000
|
||||
|
||||
#define ERR_FLAG_CRC 0x0001
|
||||
#define ERR_FLAG_CODE 0x0002
|
||||
#define ERR_FLAG_DRIBBLE 0x0004
|
||||
#define ERR_FLAG_RUNT 0x0008
|
||||
#define ERR_FLAG_OV 0x0010
|
||||
#define ERR_FLAG_TRUNC 0x0020
|
||||
#define ERR_FLAG_IP_CHKSUM 0x0040
|
||||
#define ERR_FLAG_L4_CHKSUM 0x0080
|
||||
#define ERR_FLAG_LEN 0x0100
|
||||
#define ERR_FLAG_DES_ADDR 0x0200
|
||||
|
||||
/* RFD descriptor */
|
||||
struct rx_free_desc {
|
||||
__le64 buffer_addr; /* Address of the descriptor's data buffer */
|
||||
__le16 buf_len; /* Size of the receive buffer in host memory, in byte */
|
||||
u16 coalese; /* Update consumer index to host after the reception of this frame */
|
||||
/* __attribute__ ((packed)) is required */
|
||||
} __attribute__ ((packed));
|
||||
|
||||
/* tsopu defines */
|
||||
#define TSO_PARAM_BUFLEN_MASK 0x3FFF
|
||||
#define TSO_PARAM_BUFLEN_SHIFT 0
|
||||
#define TSO_PARAM_DMAINT_MASK 0x0001
|
||||
#define TSO_PARAM_DMAINT_SHIFT 14
|
||||
#define TSO_PARAM_PKTNT_MASK 0x0001
|
||||
#define TSO_PARAM_PKTINT_SHIFT 15
|
||||
#define TSO_PARAM_VLANTAG_MASK 0xFFFF
|
||||
#define TSO_PARAM_VLAN_SHIFT 16
|
||||
|
||||
/* tsopl defines */
|
||||
#define TSO_PARAM_EOP_MASK 0x0001
|
||||
#define TSO_PARAM_EOP_SHIFT 0
|
||||
#define TSO_PARAM_COALESCE_MASK 0x0001
|
||||
#define TSO_PARAM_COALESCE_SHIFT 1
|
||||
#define TSO_PARAM_INSVLAG_MASK 0x0001
|
||||
#define TSO_PARAM_INSVLAG_SHIFT 2
|
||||
#define TSO_PARAM_CUSTOMCKSUM_MASK 0x0001
|
||||
#define TSO_PARAM_CUSTOMCKSUM_SHIFT 3
|
||||
#define TSO_PARAM_SEGMENT_MASK 0x0001
|
||||
#define TSO_PARAM_SEGMENT_SHIFT 4
|
||||
#define TSO_PARAM_IPCKSUM_MASK 0x0001
|
||||
#define TSO_PARAM_IPCKSUM_SHIFT 5
|
||||
#define TSO_PARAM_TCPCKSUM_MASK 0x0001
|
||||
#define TSO_PARAM_TCPCKSUM_SHIFT 6
|
||||
#define TSO_PARAM_UDPCKSUM_MASK 0x0001
|
||||
#define TSO_PARAM_UDPCKSUM_SHIFT 7
|
||||
#define TSO_PARAM_VLANTAGGED_MASK 0x0001
|
||||
#define TSO_PARAM_VLANTAGGED_SHIFT 8
|
||||
#define TSO_PARAM_ETHTYPE_MASK 0x0001
|
||||
#define TSO_PARAM_ETHTYPE_SHIFT 9
|
||||
#define TSO_PARAM_IPHL_MASK 0x000F
|
||||
#define TSO_PARAM_IPHL_SHIFT 10
|
||||
#define TSO_PARAM_TCPHDRLEN_MASK 0x000F
|
||||
#define TSO_PARAM_TCPHDRLEN_SHIFT 14
|
||||
#define TSO_PARAM_HDRFLAG_MASK 0x0001
|
||||
#define TSO_PARAM_HDRFLAG_SHIFT 18
|
||||
#define TSO_PARAM_MSS_MASK 0x1FFF
|
||||
#define TSO_PARAM_MSS_SHIFT 19
|
||||
|
||||
/* csumpu defines */
|
||||
#define CSUM_PARAM_BUFLEN_MASK 0x3FFF
|
||||
#define CSUM_PARAM_BUFLEN_SHIFT 0
|
||||
#define CSUM_PARAM_DMAINT_MASK 0x0001
|
||||
#define CSUM_PARAM_DMAINT_SHIFT 14
|
||||
#define CSUM_PARAM_PKTINT_MASK 0x0001
|
||||
#define CSUM_PARAM_PKTINT_SHIFT 15
|
||||
#define CSUM_PARAM_VALANTAG_MASK 0xFFFF
|
||||
#define CSUM_PARAM_VALAN_SHIFT 16
|
||||
|
||||
/* csumpl defines*/
|
||||
#define CSUM_PARAM_EOP_MASK 0x0001
|
||||
#define CSUM_PARAM_EOP_SHIFT 0
|
||||
#define CSUM_PARAM_COALESCE_MASK 0x0001
|
||||
#define CSUM_PARAM_COALESCE_SHIFT 1
|
||||
#define CSUM_PARAM_INSVLAG_MASK 0x0001
|
||||
#define CSUM_PARAM_INSVLAG_SHIFT 2
|
||||
#define CSUM_PARAM_CUSTOMCKSUM_MASK 0x0001
|
||||
#define CSUM_PARAM_CUSTOMCKSUM_SHIFT 3
|
||||
#define CSUM_PARAM_SEGMENT_MASK 0x0001
|
||||
#define CSUM_PARAM_SEGMENT_SHIFT 4
|
||||
#define CSUM_PARAM_IPCKSUM_MASK 0x0001
|
||||
#define CSUM_PARAM_IPCKSUM_SHIFT 5
|
||||
#define CSUM_PARAM_TCPCKSUM_MASK 0x0001
|
||||
#define CSUM_PARAM_TCPCKSUM_SHIFT 6
|
||||
#define CSUM_PARAM_UDPCKSUM_MASK 0x0001
|
||||
#define CSUM_PARAM_UDPCKSUM_SHIFT 7
|
||||
#define CSUM_PARAM_VLANTAGGED_MASK 0x0001
|
||||
#define CSUM_PARAM_VLANTAGGED_SHIFT 8
|
||||
#define CSUM_PARAM_ETHTYPE_MASK 0x0001
|
||||
#define CSUM_PARAM_ETHTYPE_SHIFT 9
|
||||
#define CSUM_PARAM_IPHL_MASK 0x000F
|
||||
#define CSUM_PARAM_IPHL_SHIFT 10
|
||||
#define CSUM_PARAM_PLOADOFFSET_MASK 0x00FF
|
||||
#define CSUM_PARAM_PLOADOFFSET_SHIFT 16
|
||||
#define CSUM_PARAM_XSUMOFFSET_MASK 0x00FF
|
||||
#define CSUM_PARAM_XSUMOFFSET_SHIFT 24
|
||||
|
||||
/* TPD descriptor */
|
||||
struct tso_param {
|
||||
/* The order of these declarations is important -- don't change it */
|
||||
u32 tsopu; /* tso_param upper word */
|
||||
u32 tsopl; /* tso_param lower word */
|
||||
};
|
||||
|
||||
struct csum_param {
|
||||
/* The order of these declarations is important -- don't change it */
|
||||
u32 csumpu; /* csum_param upper word */
|
||||
u32 csumpl; /* csum_param lower word */
|
||||
};
|
||||
|
||||
union tpd_descr {
|
||||
u64 data;
|
||||
struct csum_param csum;
|
||||
struct tso_param tso;
|
||||
};
|
||||
|
||||
struct tx_packet_desc {
|
||||
__le64 buffer_addr;
|
||||
union tpd_descr desc;
|
||||
};
|
||||
|
||||
/* DMA Order Settings */
|
||||
enum atl1_dma_order {
|
||||
atl1_dma_ord_in = 1,
|
||||
atl1_dma_ord_enh = 2,
|
||||
atl1_dma_ord_out = 4
|
||||
};
|
||||
|
||||
enum atl1_dma_rcb {
|
||||
atl1_rcb_64 = 0,
|
||||
atl1_rcb_128 = 1
|
||||
};
|
||||
|
||||
enum atl1_dma_req_block {
|
||||
atl1_dma_req_128 = 0,
|
||||
atl1_dma_req_256 = 1,
|
||||
atl1_dma_req_512 = 2,
|
||||
atl1_dma_req_1024 = 3,
|
||||
atl1_dma_req_2048 = 4,
|
||||
atl1_dma_req_4096 = 5
|
||||
};
|
||||
|
||||
struct atl1_spi_flash_dev {
|
||||
const char *manu_name; /* manufacturer id */
|
||||
/* op-code */
|
||||
u8 cmd_wrsr;
|
||||
u8 cmd_read;
|
||||
u8 cmd_program;
|
||||
u8 cmd_wren;
|
||||
u8 cmd_wrdi;
|
||||
u8 cmd_rdsr;
|
||||
u8 cmd_rdid;
|
||||
u8 cmd_sector_erase;
|
||||
u8 cmd_chip_erase;
|
||||
};
|
||||
|
||||
#endif /* _ATL1_HW_H_ */
|
|
@ -1,203 +0,0 @@
|
|||
/*
|
||||
* Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
|
||||
* Copyright(c) 2006 Chris Snook <csnook@redhat.com>
|
||||
* Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
|
||||
*
|
||||
* Derived from Intel e1000 driver
|
||||
* Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59
|
||||
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/moduleparam.h>
|
||||
#include <linux/pci.h>
|
||||
#include "atl1.h"
|
||||
|
||||
/*
|
||||
* This is the only thing that needs to be changed to adjust the
|
||||
* maximum number of ports that the driver can manage.
|
||||
*/
|
||||
#define ATL1_MAX_NIC 4
|
||||
|
||||
#define OPTION_UNSET -1
|
||||
#define OPTION_DISABLED 0
|
||||
#define OPTION_ENABLED 1
|
||||
|
||||
#define ATL1_PARAM_INIT { [0 ... ATL1_MAX_NIC] = OPTION_UNSET }
|
||||
|
||||
/*
|
||||
* Interrupt Moderate Timer in units of 2 us
|
||||
*
|
||||
* Valid Range: 10-65535
|
||||
*
|
||||
* Default Value: 100 (200us)
|
||||
*/
|
||||
static int __devinitdata int_mod_timer[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT;
|
||||
static int num_int_mod_timer = 0;
|
||||
module_param_array_named(int_mod_timer, int_mod_timer, int, &num_int_mod_timer, 0);
|
||||
MODULE_PARM_DESC(int_mod_timer, "Interrupt moderator timer");
|
||||
|
||||
/*
|
||||
* flash_vendor
|
||||
*
|
||||
* Valid Range: 0-2
|
||||
*
|
||||
* 0 - Atmel
|
||||
* 1 - SST
|
||||
* 2 - ST
|
||||
*
|
||||
* Default Value: 0
|
||||
*/
|
||||
static int __devinitdata flash_vendor[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT;
|
||||
static int num_flash_vendor = 0;
|
||||
module_param_array_named(flash_vendor, flash_vendor, int, &num_flash_vendor, 0);
|
||||
MODULE_PARM_DESC(flash_vendor, "SPI flash vendor");
|
||||
|
||||
#define DEFAULT_INT_MOD_CNT 100 /* 200us */
|
||||
#define MAX_INT_MOD_CNT 65000
|
||||
#define MIN_INT_MOD_CNT 50
|
||||
|
||||
#define FLASH_VENDOR_DEFAULT 0
|
||||
#define FLASH_VENDOR_MIN 0
|
||||
#define FLASH_VENDOR_MAX 2
|
||||
|
||||
struct atl1_option {
|
||||
enum { enable_option, range_option, list_option } type;
|
||||
char *name;
|
||||
char *err;
|
||||
int def;
|
||||
union {
|
||||
struct { /* range_option info */
|
||||
int min;
|
||||
int max;
|
||||
} r;
|
||||
struct { /* list_option info */
|
||||
int nr;
|
||||
struct atl1_opt_list {
|
||||
int i;
|
||||
char *str;
|
||||
} *p;
|
||||
} l;
|
||||
} arg;
|
||||
};
|
||||
|
||||
static int __devinit atl1_validate_option(int *value, struct atl1_option *opt, struct pci_dev *pdev)
|
||||
{
|
||||
if (*value == OPTION_UNSET) {
|
||||
*value = opt->def;
|
||||
return 0;
|
||||
}
|
||||
|
||||
switch (opt->type) {
|
||||
case enable_option:
|
||||
switch (*value) {
|
||||
case OPTION_ENABLED:
|
||||
dev_info(&pdev->dev, "%s enabled\n", opt->name);
|
||||
return 0;
|
||||
case OPTION_DISABLED:
|
||||
dev_info(&pdev->dev, "%s disabled\n", opt->name);
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
case range_option:
|
||||
if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
|
||||
dev_info(&pdev->dev, "%s set to %i\n", opt->name,
|
||||
*value);
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
case list_option:{
|
||||
int i;
|
||||
struct atl1_opt_list *ent;
|
||||
|
||||
for (i = 0; i < opt->arg.l.nr; i++) {
|
||||
ent = &opt->arg.l.p[i];
|
||||
if (*value == ent->i) {
|
||||
if (ent->str[0] != '\0')
|
||||
dev_info(&pdev->dev, "%s\n",
|
||||
ent->str);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
dev_info(&pdev->dev, "invalid %s specified (%i) %s\n",
|
||||
opt->name, *value, opt->err);
|
||||
*value = opt->def;
|
||||
return -1;
|
||||
}
|
||||
|
||||
/*
|
||||
* atl1_check_options - Range Checking for Command Line Parameters
|
||||
* @adapter: board private structure
|
||||
*
|
||||
* This routine checks all command line parameters for valid user
|
||||
* input. If an invalid value is given, or if no user specified
|
||||
* value exists, a default value is used. The final value is stored
|
||||
* in a variable in the adapter structure.
|
||||
*/
|
||||
void __devinit atl1_check_options(struct atl1_adapter *adapter)
|
||||
{
|
||||
struct pci_dev *pdev = adapter->pdev;
|
||||
int bd = adapter->bd_number;
|
||||
if (bd >= ATL1_MAX_NIC) {
|
||||
dev_notice(&pdev->dev, "no configuration for board#%i\n", bd);
|
||||
dev_notice(&pdev->dev, "using defaults for all values\n");
|
||||
}
|
||||
{ /* Interrupt Moderate Timer */
|
||||
struct atl1_option opt = {
|
||||
.type = range_option,
|
||||
.name = "Interrupt Moderator Timer",
|
||||
.err = "using default of "
|
||||
__MODULE_STRING(DEFAULT_INT_MOD_CNT),
|
||||
.def = DEFAULT_INT_MOD_CNT,
|
||||
.arg = {.r =
|
||||
{.min = MIN_INT_MOD_CNT,.max = MAX_INT_MOD_CNT}}
|
||||
};
|
||||
int val;
|
||||
if (num_int_mod_timer > bd) {
|
||||
val = int_mod_timer[bd];
|
||||
atl1_validate_option(&val, &opt, pdev);
|
||||
adapter->imt = (u16) val;
|
||||
} else
|
||||
adapter->imt = (u16) (opt.def);
|
||||
}
|
||||
|
||||
{ /* Flash Vendor */
|
||||
struct atl1_option opt = {
|
||||
.type = range_option,
|
||||
.name = "SPI Flash Vendor",
|
||||
.err = "using default of "
|
||||
__MODULE_STRING(FLASH_VENDOR_DEFAULT),
|
||||
.def = DEFAULT_INT_MOD_CNT,
|
||||
.arg = {.r =
|
||||
{.min = FLASH_VENDOR_MIN,.max =
|
||||
FLASH_VENDOR_MAX}}
|
||||
};
|
||||
int val;
|
||||
if (num_flash_vendor > bd) {
|
||||
val = flash_vendor[bd];
|
||||
atl1_validate_option(&val, &opt, pdev);
|
||||
adapter->hw.flash_vendor = (u8) val;
|
||||
} else
|
||||
adapter->hw.flash_vendor = (u8) (opt.def);
|
||||
}
|
||||
}
|
|
@ -0,0 +1 @@
|
|||
obj-$(CONFIG_ATL1) += atl1.o
|
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
@ -0,0 +1,796 @@
|
|||
/*
|
||||
* Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
|
||||
* Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
|
||||
* Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
|
||||
*
|
||||
* Derived from Intel e1000 driver
|
||||
* Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59
|
||||
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef ATL1_H
|
||||
#define ATL1_H
|
||||
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/ethtool.h>
|
||||
#include <linux/if_vlan.h>
|
||||
#include <linux/mii.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/skbuff.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/timer.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/workqueue.h>
|
||||
|
||||
#include "atlx.h"
|
||||
|
||||
#define ATLX_DRIVER_NAME "atl1"
|
||||
|
||||
MODULE_DESCRIPTION("Atheros L1 Gigabit Ethernet Driver");
|
||||
|
||||
#define atlx_adapter atl1_adapter
|
||||
#define atlx_check_for_link atl1_check_for_link
|
||||
#define atlx_check_link atl1_check_link
|
||||
#define atlx_hash_mc_addr atl1_hash_mc_addr
|
||||
#define atlx_hash_set atl1_hash_set
|
||||
#define atlx_hw atl1_hw
|
||||
#define atlx_mii_ioctl atl1_mii_ioctl
|
||||
#define atlx_read_phy_reg atl1_read_phy_reg
|
||||
#define atlx_set_mac atl1_set_mac
|
||||
#define atlx_set_mac_addr atl1_set_mac_addr
|
||||
|
||||
struct atl1_adapter;
|
||||
struct atl1_hw;
|
||||
|
||||
/* function prototypes needed by multiple files */
|
||||
u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr);
|
||||
void atl1_hash_set(struct atl1_hw *hw, u32 hash_value);
|
||||
s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data);
|
||||
void atl1_set_mac_addr(struct atl1_hw *hw);
|
||||
static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
|
||||
int cmd);
|
||||
static u32 atl1_check_link(struct atl1_adapter *adapter);
|
||||
|
||||
extern const struct ethtool_ops atl1_ethtool_ops;
|
||||
|
||||
/* hardware definitions specific to L1 */
|
||||
|
||||
/* Block IDLE Status Register */
|
||||
#define IDLE_STATUS_RXMAC 0x1
|
||||
#define IDLE_STATUS_TXMAC 0x2
|
||||
#define IDLE_STATUS_RXQ 0x4
|
||||
#define IDLE_STATUS_TXQ 0x8
|
||||
#define IDLE_STATUS_DMAR 0x10
|
||||
#define IDLE_STATUS_DMAW 0x20
|
||||
#define IDLE_STATUS_SMB 0x40
|
||||
#define IDLE_STATUS_CMB 0x80
|
||||
|
||||
/* MDIO Control Register */
|
||||
#define MDIO_WAIT_TIMES 30
|
||||
|
||||
/* MAC Control Register */
|
||||
#define MAC_CTRL_TX_PAUSE 0x10000
|
||||
#define MAC_CTRL_SCNT 0x20000
|
||||
#define MAC_CTRL_SRST_TX 0x40000
|
||||
#define MAC_CTRL_TX_SIMURST 0x80000
|
||||
#define MAC_CTRL_SPEED_SHIFT 20
|
||||
#define MAC_CTRL_SPEED_MASK 0x300000
|
||||
#define MAC_CTRL_SPEED_1000 0x2
|
||||
#define MAC_CTRL_SPEED_10_100 0x1
|
||||
#define MAC_CTRL_DBG_TX_BKPRESURE 0x400000
|
||||
#define MAC_CTRL_TX_HUGE 0x800000
|
||||
#define MAC_CTRL_RX_CHKSUM_EN 0x1000000
|
||||
#define MAC_CTRL_DBG 0x8000000
|
||||
|
||||
/* Wake-On-Lan control register */
|
||||
#define WOL_CLK_SWITCH_EN 0x8000
|
||||
#define WOL_PT5_EN 0x200000
|
||||
#define WOL_PT6_EN 0x400000
|
||||
#define WOL_PT5_MATCH 0x8000000
|
||||
#define WOL_PT6_MATCH 0x10000000
|
||||
|
||||
/* WOL Length ( 2 DWORD ) */
|
||||
#define REG_WOL_PATTERN_LEN 0x14A4
|
||||
#define WOL_PT_LEN_MASK 0x7F
|
||||
#define WOL_PT0_LEN_SHIFT 0
|
||||
#define WOL_PT1_LEN_SHIFT 8
|
||||
#define WOL_PT2_LEN_SHIFT 16
|
||||
#define WOL_PT3_LEN_SHIFT 24
|
||||
#define WOL_PT4_LEN_SHIFT 0
|
||||
#define WOL_PT5_LEN_SHIFT 8
|
||||
#define WOL_PT6_LEN_SHIFT 16
|
||||
|
||||
/* Internal SRAM Partition Registers, low 32 bits */
|
||||
#define REG_SRAM_RFD_LEN 0x1504
|
||||
#define REG_SRAM_RRD_ADDR 0x1508
|
||||
#define REG_SRAM_RRD_LEN 0x150C
|
||||
#define REG_SRAM_TPD_ADDR 0x1510
|
||||
#define REG_SRAM_TPD_LEN 0x1514
|
||||
#define REG_SRAM_TRD_ADDR 0x1518
|
||||
#define REG_SRAM_TRD_LEN 0x151C
|
||||
#define REG_SRAM_RXF_ADDR 0x1520
|
||||
#define REG_SRAM_RXF_LEN 0x1524
|
||||
#define REG_SRAM_TXF_ADDR 0x1528
|
||||
#define REG_SRAM_TXF_LEN 0x152C
|
||||
#define REG_SRAM_TCPH_PATH_ADDR 0x1530
|
||||
#define SRAM_TCPH_ADDR_MASK 0xFFF
|
||||
#define SRAM_TCPH_ADDR_SHIFT 0
|
||||
#define SRAM_PATH_ADDR_MASK 0xFFF
|
||||
#define SRAM_PATH_ADDR_SHIFT 16
|
||||
|
||||
/* Load Ptr Register */
|
||||
#define REG_LOAD_PTR 0x1534
|
||||
|
||||
/* Descriptor Control registers, low 32 bits */
|
||||
#define REG_DESC_RFD_ADDR_LO 0x1544
|
||||
#define REG_DESC_RRD_ADDR_LO 0x1548
|
||||
#define REG_DESC_TPD_ADDR_LO 0x154C
|
||||
#define REG_DESC_CMB_ADDR_LO 0x1550
|
||||
#define REG_DESC_SMB_ADDR_LO 0x1554
|
||||
#define REG_DESC_RFD_RRD_RING_SIZE 0x1558
|
||||
#define DESC_RFD_RING_SIZE_MASK 0x7FF
|
||||
#define DESC_RFD_RING_SIZE_SHIFT 0
|
||||
#define DESC_RRD_RING_SIZE_MASK 0x7FF
|
||||
#define DESC_RRD_RING_SIZE_SHIFT 16
|
||||
#define REG_DESC_TPD_RING_SIZE 0x155C
|
||||
#define DESC_TPD_RING_SIZE_MASK 0x3FF
|
||||
#define DESC_TPD_RING_SIZE_SHIFT 0
|
||||
|
||||
/* TXQ Control Register */
|
||||
#define REG_TXQ_CTRL 0x1580
|
||||
#define TXQ_CTRL_TPD_BURST_NUM_SHIFT 0
|
||||
#define TXQ_CTRL_TPD_BURST_NUM_MASK 0x1F
|
||||
#define TXQ_CTRL_EN 0x20
|
||||
#define TXQ_CTRL_ENH_MODE 0x40
|
||||
#define TXQ_CTRL_TPD_FETCH_TH_SHIFT 8
|
||||
#define TXQ_CTRL_TPD_FETCH_TH_MASK 0x3F
|
||||
#define TXQ_CTRL_TXF_BURST_NUM_SHIFT 16
|
||||
#define TXQ_CTRL_TXF_BURST_NUM_MASK 0xFFFF
|
||||
|
||||
/* Jumbo packet Threshold for task offload */
|
||||
#define REG_TX_JUMBO_TASK_TH_TPD_IPG 0x1584
|
||||
#define TX_JUMBO_TASK_TH_MASK 0x7FF
|
||||
#define TX_JUMBO_TASK_TH_SHIFT 0
|
||||
#define TX_TPD_MIN_IPG_MASK 0x1F
|
||||
#define TX_TPD_MIN_IPG_SHIFT 16
|
||||
|
||||
/* RXQ Control Register */
|
||||
#define REG_RXQ_CTRL 0x15A0
|
||||
#define RXQ_CTRL_RFD_BURST_NUM_SHIFT 0
|
||||
#define RXQ_CTRL_RFD_BURST_NUM_MASK 0xFF
|
||||
#define RXQ_CTRL_RRD_BURST_THRESH_SHIFT 8
|
||||
#define RXQ_CTRL_RRD_BURST_THRESH_MASK 0xFF
|
||||
#define RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT 16
|
||||
#define RXQ_CTRL_RFD_PREF_MIN_IPG_MASK 0x1F
|
||||
#define RXQ_CTRL_CUT_THRU_EN 0x40000000
|
||||
#define RXQ_CTRL_EN 0x80000000
|
||||
|
||||
/* Rx jumbo packet threshold and rrd retirement timer */
|
||||
#define REG_RXQ_JMBOSZ_RRDTIM 0x15A4
|
||||
#define RXQ_JMBOSZ_TH_MASK 0x7FF
|
||||
#define RXQ_JMBOSZ_TH_SHIFT 0
|
||||
#define RXQ_JMBO_LKAH_MASK 0xF
|
||||
#define RXQ_JMBO_LKAH_SHIFT 11
|
||||
#define RXQ_RRD_TIMER_MASK 0xFFFF
|
||||
#define RXQ_RRD_TIMER_SHIFT 16
|
||||
|
||||
/* RFD flow control register */
|
||||
#define REG_RXQ_RXF_PAUSE_THRESH 0x15A8
|
||||
#define RXQ_RXF_PAUSE_TH_HI_SHIFT 16
|
||||
#define RXQ_RXF_PAUSE_TH_HI_MASK 0xFFF
|
||||
#define RXQ_RXF_PAUSE_TH_LO_SHIFT 0
|
||||
#define RXQ_RXF_PAUSE_TH_LO_MASK 0xFFF
|
||||
|
||||
/* RRD flow control register */
|
||||
#define REG_RXQ_RRD_PAUSE_THRESH 0x15AC
|
||||
#define RXQ_RRD_PAUSE_TH_HI_SHIFT 0
|
||||
#define RXQ_RRD_PAUSE_TH_HI_MASK 0xFFF
|
||||
#define RXQ_RRD_PAUSE_TH_LO_SHIFT 16
|
||||
#define RXQ_RRD_PAUSE_TH_LO_MASK 0xFFF
|
||||
|
||||
/* DMA Engine Control Register */
|
||||
#define REG_DMA_CTRL 0x15C0
|
||||
#define DMA_CTRL_DMAR_IN_ORDER 0x1
|
||||
#define DMA_CTRL_DMAR_ENH_ORDER 0x2
|
||||
#define DMA_CTRL_DMAR_OUT_ORDER 0x4
|
||||
#define DMA_CTRL_RCB_VALUE 0x8
|
||||
#define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4
|
||||
#define DMA_CTRL_DMAR_BURST_LEN_MASK 7
|
||||
#define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7
|
||||
#define DMA_CTRL_DMAW_BURST_LEN_MASK 7
|
||||
#define DMA_CTRL_DMAR_EN 0x400
|
||||
#define DMA_CTRL_DMAW_EN 0x800
|
||||
|
||||
/* CMB/SMB Control Register */
|
||||
#define REG_CSMB_CTRL 0x15D0
|
||||
#define CSMB_CTRL_CMB_NOW 1
|
||||
#define CSMB_CTRL_SMB_NOW 2
|
||||
#define CSMB_CTRL_CMB_EN 4
|
||||
#define CSMB_CTRL_SMB_EN 8
|
||||
|
||||
/* CMB DMA Write Threshold Register */
|
||||
#define REG_CMB_WRITE_TH 0x15D4
|
||||
#define CMB_RRD_TH_SHIFT 0
|
||||
#define CMB_RRD_TH_MASK 0x7FF
|
||||
#define CMB_TPD_TH_SHIFT 16
|
||||
#define CMB_TPD_TH_MASK 0x7FF
|
||||
|
||||
/* RX/TX count-down timer to trigger CMB-write. 2us resolution. */
|
||||
#define REG_CMB_WRITE_TIMER 0x15D8
|
||||
#define CMB_RX_TM_SHIFT 0
|
||||
#define CMB_RX_TM_MASK 0xFFFF
|
||||
#define CMB_TX_TM_SHIFT 16
|
||||
#define CMB_TX_TM_MASK 0xFFFF
|
||||
|
||||
/* Number of packet received since last CMB write */
|
||||
#define REG_CMB_RX_PKT_CNT 0x15DC
|
||||
|
||||
/* Number of packet transmitted since last CMB write */
|
||||
#define REG_CMB_TX_PKT_CNT 0x15E0
|
||||
|
||||
/* SMB auto DMA timer register */
|
||||
#define REG_SMB_TIMER 0x15E4
|
||||
|
||||
/* Mailbox Register */
|
||||
#define REG_MAILBOX 0x15F0
|
||||
#define MB_RFD_PROD_INDX_SHIFT 0
|
||||
#define MB_RFD_PROD_INDX_MASK 0x7FF
|
||||
#define MB_RRD_CONS_INDX_SHIFT 11
|
||||
#define MB_RRD_CONS_INDX_MASK 0x7FF
|
||||
#define MB_TPD_PROD_INDX_SHIFT 22
|
||||
#define MB_TPD_PROD_INDX_MASK 0x3FF
|
||||
|
||||
/* Interrupt Status Register */
|
||||
#define ISR_SMB 0x1
|
||||
#define ISR_TIMER 0x2
|
||||
#define ISR_MANUAL 0x4
|
||||
#define ISR_RXF_OV 0x8
|
||||
#define ISR_RFD_UNRUN 0x10
|
||||
#define ISR_RRD_OV 0x20
|
||||
#define ISR_TXF_UNRUN 0x40
|
||||
#define ISR_LINK 0x80
|
||||
#define ISR_HOST_RFD_UNRUN 0x100
|
||||
#define ISR_HOST_RRD_OV 0x200
|
||||
#define ISR_DMAR_TO_RST 0x400
|
||||
#define ISR_DMAW_TO_RST 0x800
|
||||
#define ISR_GPHY 0x1000
|
||||
#define ISR_RX_PKT 0x10000
|
||||
#define ISR_TX_PKT 0x20000
|
||||
#define ISR_TX_DMA 0x40000
|
||||
#define ISR_RX_DMA 0x80000
|
||||
#define ISR_CMB_RX 0x100000
|
||||
#define ISR_CMB_TX 0x200000
|
||||
#define ISR_MAC_RX 0x400000
|
||||
#define ISR_MAC_TX 0x800000
|
||||
#define ISR_DIS_SMB 0x20000000
|
||||
#define ISR_DIS_DMA 0x40000000
|
||||
|
||||
/* Normal Interrupt mask */
|
||||
#define IMR_NORMAL_MASK (\
|
||||
ISR_SMB |\
|
||||
ISR_GPHY |\
|
||||
ISR_PHY_LINKDOWN|\
|
||||
ISR_DMAR_TO_RST |\
|
||||
ISR_DMAW_TO_RST |\
|
||||
ISR_CMB_TX |\
|
||||
ISR_CMB_RX)
|
||||
|
||||
/* Debug Interrupt Mask (enable all interrupt) */
|
||||
#define IMR_DEBUG_MASK (\
|
||||
ISR_SMB |\
|
||||
ISR_TIMER |\
|
||||
ISR_MANUAL |\
|
||||
ISR_RXF_OV |\
|
||||
ISR_RFD_UNRUN |\
|
||||
ISR_RRD_OV |\
|
||||
ISR_TXF_UNRUN |\
|
||||
ISR_LINK |\
|
||||
ISR_CMB_TX |\
|
||||
ISR_CMB_RX |\
|
||||
ISR_RX_PKT |\
|
||||
ISR_TX_PKT |\
|
||||
ISR_MAC_RX |\
|
||||
ISR_MAC_TX)
|
||||
|
||||
#define MEDIA_TYPE_1000M_FULL 1
|
||||
#define MEDIA_TYPE_100M_FULL 2
|
||||
#define MEDIA_TYPE_100M_HALF 3
|
||||
#define MEDIA_TYPE_10M_FULL 4
|
||||
#define MEDIA_TYPE_10M_HALF 5
|
||||
|
||||
#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* All but 1000-Half */
|
||||
|
||||
#define MAX_JUMBO_FRAME_SIZE 10240
|
||||
|
||||
#define ATL1_EEDUMP_LEN 48
|
||||
|
||||
/* Statistics counters collected by the MAC */
|
||||
struct stats_msg_block {
|
||||
/* rx */
|
||||
u32 rx_ok; /* good RX packets */
|
||||
u32 rx_bcast; /* good RX broadcast packets */
|
||||
u32 rx_mcast; /* good RX multicast packets */
|
||||
u32 rx_pause; /* RX pause frames */
|
||||
u32 rx_ctrl; /* RX control packets other than pause frames */
|
||||
u32 rx_fcs_err; /* RX packets with bad FCS */
|
||||
u32 rx_len_err; /* RX packets with length != actual size */
|
||||
u32 rx_byte_cnt; /* good bytes received. FCS is NOT included */
|
||||
u32 rx_runt; /* RX packets < 64 bytes with good FCS */
|
||||
u32 rx_frag; /* RX packets < 64 bytes with bad FCS */
|
||||
u32 rx_sz_64; /* 64 byte RX packets */
|
||||
u32 rx_sz_65_127;
|
||||
u32 rx_sz_128_255;
|
||||
u32 rx_sz_256_511;
|
||||
u32 rx_sz_512_1023;
|
||||
u32 rx_sz_1024_1518;
|
||||
u32 rx_sz_1519_max; /* 1519 byte to MTU RX packets */
|
||||
u32 rx_sz_ov; /* truncated RX packets > MTU */
|
||||
u32 rx_rxf_ov; /* frames dropped due to RX FIFO overflow */
|
||||
u32 rx_rrd_ov; /* frames dropped due to RRD overflow */
|
||||
u32 rx_align_err; /* alignment errors */
|
||||
u32 rx_bcast_byte_cnt; /* RX broadcast bytes, excluding FCS */
|
||||
u32 rx_mcast_byte_cnt; /* RX multicast bytes, excluding FCS */
|
||||
u32 rx_err_addr; /* packets dropped due to address filtering */
|
||||
|
||||
/* tx */
|
||||
u32 tx_ok; /* good TX packets */
|
||||
u32 tx_bcast; /* good TX broadcast packets */
|
||||
u32 tx_mcast; /* good TX multicast packets */
|
||||
u32 tx_pause; /* TX pause frames */
|
||||
u32 tx_exc_defer; /* TX packets deferred excessively */
|
||||
u32 tx_ctrl; /* TX control frames, excluding pause frames */
|
||||
u32 tx_defer; /* TX packets deferred */
|
||||
u32 tx_byte_cnt; /* bytes transmitted, FCS is NOT included */
|
||||
u32 tx_sz_64; /* 64 byte TX packets */
|
||||
u32 tx_sz_65_127;
|
||||
u32 tx_sz_128_255;
|
||||
u32 tx_sz_256_511;
|
||||
u32 tx_sz_512_1023;
|
||||
u32 tx_sz_1024_1518;
|
||||
u32 tx_sz_1519_max; /* 1519 byte to MTU TX packets */
|
||||
u32 tx_1_col; /* packets TX after a single collision */
|
||||
u32 tx_2_col; /* packets TX after multiple collisions */
|
||||
u32 tx_late_col; /* TX packets with late collisions */
|
||||
u32 tx_abort_col; /* TX packets aborted w/excessive collisions */
|
||||
u32 tx_underrun; /* TX packets aborted due to TX FIFO underrun
|
||||
* or TRD FIFO underrun */
|
||||
u32 tx_rd_eop; /* reads beyond the EOP into the next frame
|
||||
* when TRD was not written timely */
|
||||
u32 tx_len_err; /* TX packets where length != actual size */
|
||||
u32 tx_trunc; /* TX packets truncated due to size > MTU */
|
||||
u32 tx_bcast_byte; /* broadcast bytes transmitted, excluding FCS */
|
||||
u32 tx_mcast_byte; /* multicast bytes transmitted, excluding FCS */
|
||||
u32 smb_updated; /* 1: SMB Updated. This is used by software to
|
||||
* indicate the statistics update. Software
|
||||
* should clear this bit after retrieving the
|
||||
* statistics information. */
|
||||
};
|
||||
|
||||
/* Coalescing Message Block */
|
||||
struct coals_msg_block {
|
||||
u32 int_stats; /* interrupt status */
|
||||
u16 rrd_prod_idx; /* TRD Producer Index. */
|
||||
u16 rfd_cons_idx; /* RFD Consumer Index. */
|
||||
u16 update; /* Selene sets this bit every time it DMAs the
|
||||
* CMB to host memory. Software should clear
|
||||
* this bit when CMB info is processed. */
|
||||
u16 tpd_cons_idx; /* TPD Consumer Index. */
|
||||
};
|
||||
|
||||
/* RRD descriptor */
|
||||
struct rx_return_desc {
|
||||
u8 num_buf; /* Number of RFD buffers used by the received packet */
|
||||
u8 resved;
|
||||
u16 buf_indx; /* RFD Index of the first buffer */
|
||||
union {
|
||||
u32 valid;
|
||||
struct {
|
||||
u16 rx_chksum;
|
||||
u16 pkt_size;
|
||||
} xsum_sz;
|
||||
} xsz;
|
||||
|
||||
u16 pkt_flg; /* Packet flags */
|
||||
u16 err_flg; /* Error flags */
|
||||
u16 resved2;
|
||||
u16 vlan_tag; /* VLAN TAG */
|
||||
};
|
||||
|
||||
#define PACKET_FLAG_ETH_TYPE 0x0080
|
||||
#define PACKET_FLAG_VLAN_INS 0x0100
|
||||
#define PACKET_FLAG_ERR 0x0200
|
||||
#define PACKET_FLAG_IPV4 0x0400
|
||||
#define PACKET_FLAG_UDP 0x0800
|
||||
#define PACKET_FLAG_TCP 0x1000
|
||||
#define PACKET_FLAG_BCAST 0x2000
|
||||
#define PACKET_FLAG_MCAST 0x4000
|
||||
#define PACKET_FLAG_PAUSE 0x8000
|
||||
|
||||
#define ERR_FLAG_CRC 0x0001
|
||||
#define ERR_FLAG_CODE 0x0002
|
||||
#define ERR_FLAG_DRIBBLE 0x0004
|
||||
#define ERR_FLAG_RUNT 0x0008
|
||||
#define ERR_FLAG_OV 0x0010
|
||||
#define ERR_FLAG_TRUNC 0x0020
|
||||
#define ERR_FLAG_IP_CHKSUM 0x0040
|
||||
#define ERR_FLAG_L4_CHKSUM 0x0080
|
||||
#define ERR_FLAG_LEN 0x0100
|
||||
#define ERR_FLAG_DES_ADDR 0x0200
|
||||
|
||||
/* RFD descriptor */
|
||||
struct rx_free_desc {
|
||||
__le64 buffer_addr; /* Address of the descriptor's data buffer */
|
||||
__le16 buf_len; /* Size of the receive buffer in host memory */
|
||||
u16 coalese; /* Update consumer index to host after the
|
||||
* reception of this frame */
|
||||
/* __attribute__ ((packed)) is required */
|
||||
} __attribute__ ((packed));
|
||||
|
||||
/*
|
||||
* The L1 transmit packet descriptor is comprised of four 32-bit words.
|
||||
*
|
||||
* 31 0
|
||||
* +---------------------------------------+
|
||||
* | Word 0: Buffer addr lo |
|
||||
* +---------------------------------------+
|
||||
* | Word 1: Buffer addr hi |
|
||||
* +---------------------------------------+
|
||||
* | Word 2 |
|
||||
* +---------------------------------------+
|
||||
* | Word 3 |
|
||||
* +---------------------------------------+
|
||||
*
|
||||
* Words 0 and 1 combine to form a 64-bit buffer address.
|
||||
*
|
||||
* Word 2 is self explanatory in the #define block below.
|
||||
*
|
||||
* Word 3 has two forms, depending upon the state of bits 3 and 4.
|
||||
* If bits 3 and 4 are both zero, then bits 14:31 are unused by the
|
||||
* hardware. Otherwise, if either bit 3 or 4 is set, the definition
|
||||
* of bits 14:31 vary according to the following depiction.
|
||||
*
|
||||
* 0 End of packet 0 End of packet
|
||||
* 1 Coalesce 1 Coalesce
|
||||
* 2 Insert VLAN tag 2 Insert VLAN tag
|
||||
* 3 Custom csum enable = 0 3 Custom csum enable = 1
|
||||
* 4 Segment enable = 1 4 Segment enable = 0
|
||||
* 5 Generate IP checksum 5 Generate IP checksum
|
||||
* 6 Generate TCP checksum 6 Generate TCP checksum
|
||||
* 7 Generate UDP checksum 7 Generate UDP checksum
|
||||
* 8 VLAN tagged 8 VLAN tagged
|
||||
* 9 Ethernet frame type 9 Ethernet frame type
|
||||
* 10-+ 10-+
|
||||
* 11 | IP hdr length (10:13) 11 | IP hdr length (10:13)
|
||||
* 12 | (num 32-bit words) 12 | (num 32-bit words)
|
||||
* 13-+ 13-+
|
||||
* 14-+ 14 Unused
|
||||
* 15 | TCP hdr length (14:17) 15 Unused
|
||||
* 16 | (num 32-bit words) 16-+
|
||||
* 17-+ 17 |
|
||||
* 18 Header TPD flag 18 |
|
||||
* 19-+ 19 | Payload offset
|
||||
* 20 | 20 | (16:23)
|
||||
* 21 | 21 |
|
||||
* 22 | 22 |
|
||||
* 23 | 23-+
|
||||
* 24 | 24-+
|
||||
* 25 | MSS (19:31) 25 |
|
||||
* 26 | 26 |
|
||||
* 27 | 27 | Custom csum offset
|
||||
* 28 | 28 | (24:31)
|
||||
* 29 | 29 |
|
||||
* 30 | 30 |
|
||||
* 31-+ 31-+
|
||||
*/
|
||||
|
||||
/* tpd word 2 */
|
||||
#define TPD_BUFLEN_MASK 0x3FFF
|
||||
#define TPD_BUFLEN_SHIFT 0
|
||||
#define TPD_DMAINT_MASK 0x0001
|
||||
#define TPD_DMAINT_SHIFT 14
|
||||
#define TPD_PKTNT_MASK 0x0001
|
||||
#define TPD_PKTINT_SHIFT 15
|
||||
#define TPD_VLANTAG_MASK 0xFFFF
|
||||
#define TPD_VLAN_SHIFT 16
|
||||
|
||||
/* tpd word 3 bits 0:13 */
|
||||
#define TPD_EOP_MASK 0x0001
|
||||
#define TPD_EOP_SHIFT 0
|
||||
#define TPD_COALESCE_MASK 0x0001
|
||||
#define TPD_COALESCE_SHIFT 1
|
||||
#define TPD_INS_VL_TAG_MASK 0x0001
|
||||
#define TPD_INS_VL_TAG_SHIFT 2
|
||||
#define TPD_CUST_CSUM_EN_MASK 0x0001
|
||||
#define TPD_CUST_CSUM_EN_SHIFT 3
|
||||
#define TPD_SEGMENT_EN_MASK 0x0001
|
||||
#define TPD_SEGMENT_EN_SHIFT 4
|
||||
#define TPD_IP_CSUM_MASK 0x0001
|
||||
#define TPD_IP_CSUM_SHIFT 5
|
||||
#define TPD_TCP_CSUM_MASK 0x0001
|
||||
#define TPD_TCP_CSUM_SHIFT 6
|
||||
#define TPD_UDP_CSUM_MASK 0x0001
|
||||
#define TPD_UDP_CSUM_SHIFT 7
|
||||
#define TPD_VL_TAGGED_MASK 0x0001
|
||||
#define TPD_VL_TAGGED_SHIFT 8
|
||||
#define TPD_ETHTYPE_MASK 0x0001
|
||||
#define TPD_ETHTYPE_SHIFT 9
|
||||
#define TPD_IPHL_MASK 0x000F
|
||||
#define TPD_IPHL_SHIFT 10
|
||||
|
||||
/* tpd word 3 bits 14:31 if segment enabled */
|
||||
#define TPD_TCPHDRLEN_MASK 0x000F
|
||||
#define TPD_TCPHDRLEN_SHIFT 14
|
||||
#define TPD_HDRFLAG_MASK 0x0001
|
||||
#define TPD_HDRFLAG_SHIFT 18
|
||||
#define TPD_MSS_MASK 0x1FFF
|
||||
#define TPD_MSS_SHIFT 19
|
||||
|
||||
/* tpd word 3 bits 16:31 if custom csum enabled */
|
||||
#define TPD_PLOADOFFSET_MASK 0x00FF
|
||||
#define TPD_PLOADOFFSET_SHIFT 16
|
||||
#define TPD_CCSUMOFFSET_MASK 0x00FF
|
||||
#define TPD_CCSUMOFFSET_SHIFT 24
|
||||
|
||||
struct tx_packet_desc {
|
||||
__le64 buffer_addr;
|
||||
__le32 word2;
|
||||
__le32 word3;
|
||||
};
|
||||
|
||||
/* DMA Order Settings */
|
||||
enum atl1_dma_order {
|
||||
atl1_dma_ord_in = 1,
|
||||
atl1_dma_ord_enh = 2,
|
||||
atl1_dma_ord_out = 4
|
||||
};
|
||||
|
||||
enum atl1_dma_rcb {
|
||||
atl1_rcb_64 = 0,
|
||||
atl1_rcb_128 = 1
|
||||
};
|
||||
|
||||
enum atl1_dma_req_block {
|
||||
atl1_dma_req_128 = 0,
|
||||
atl1_dma_req_256 = 1,
|
||||
atl1_dma_req_512 = 2,
|
||||
atl1_dma_req_1024 = 3,
|
||||
atl1_dma_req_2048 = 4,
|
||||
atl1_dma_req_4096 = 5
|
||||
};
|
||||
|
||||
#define ATL1_MAX_INTR 3
|
||||
#define ATL1_MAX_TX_BUF_LEN 0x3000 /* 12288 bytes */
|
||||
|
||||
#define ATL1_DEFAULT_TPD 256
|
||||
#define ATL1_MAX_TPD 1024
|
||||
#define ATL1_MIN_TPD 64
|
||||
#define ATL1_DEFAULT_RFD 512
|
||||
#define ATL1_MIN_RFD 128
|
||||
#define ATL1_MAX_RFD 2048
|
||||
#define ATL1_REG_COUNT 1538
|
||||
|
||||
#define ATL1_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i]))
|
||||
#define ATL1_RFD_DESC(R, i) ATL1_GET_DESC(R, i, struct rx_free_desc)
|
||||
#define ATL1_TPD_DESC(R, i) ATL1_GET_DESC(R, i, struct tx_packet_desc)
|
||||
#define ATL1_RRD_DESC(R, i) ATL1_GET_DESC(R, i, struct rx_return_desc)
|
||||
|
||||
/*
|
||||
* atl1_ring_header represents a single, contiguous block of DMA space
|
||||
* mapped for the three descriptor rings (tpd, rfd, rrd) and the two
|
||||
* message blocks (cmb, smb) described below
|
||||
*/
|
||||
struct atl1_ring_header {
|
||||
void *desc; /* virtual address */
|
||||
dma_addr_t dma; /* physical address*/
|
||||
unsigned int size; /* length in bytes */
|
||||
};
|
||||
|
||||
/*
|
||||
* atl1_buffer is wrapper around a pointer to a socket buffer
|
||||
* so a DMA handle can be stored along with the skb
|
||||
*/
|
||||
struct atl1_buffer {
|
||||
struct sk_buff *skb; /* socket buffer */
|
||||
u16 length; /* rx buffer length */
|
||||
u16 alloced; /* 1 if skb allocated */
|
||||
dma_addr_t dma;
|
||||
};
|
||||
|
||||
/* transmit packet descriptor (tpd) ring */
|
||||
struct atl1_tpd_ring {
|
||||
void *desc; /* descriptor ring virtual address */
|
||||
dma_addr_t dma; /* descriptor ring physical address */
|
||||
u16 size; /* descriptor ring length in bytes */
|
||||
u16 count; /* number of descriptors in the ring */
|
||||
u16 hw_idx; /* hardware index */
|
||||
atomic_t next_to_clean;
|
||||
atomic_t next_to_use;
|
||||
struct atl1_buffer *buffer_info;
|
||||
};
|
||||
|
||||
/* receive free descriptor (rfd) ring */
|
||||
struct atl1_rfd_ring {
|
||||
void *desc; /* descriptor ring virtual address */
|
||||
dma_addr_t dma; /* descriptor ring physical address */
|
||||
u16 size; /* descriptor ring length in bytes */
|
||||
u16 count; /* number of descriptors in the ring */
|
||||
atomic_t next_to_use;
|
||||
u16 next_to_clean;
|
||||
struct atl1_buffer *buffer_info;
|
||||
};
|
||||
|
||||
/* receive return descriptor (rrd) ring */
|
||||
struct atl1_rrd_ring {
|
||||
void *desc; /* descriptor ring virtual address */
|
||||
dma_addr_t dma; /* descriptor ring physical address */
|
||||
unsigned int size; /* descriptor ring length in bytes */
|
||||
u16 count; /* number of descriptors in the ring */
|
||||
u16 next_to_use;
|
||||
atomic_t next_to_clean;
|
||||
};
|
||||
|
||||
/* coalescing message block (cmb) */
|
||||
struct atl1_cmb {
|
||||
struct coals_msg_block *cmb;
|
||||
dma_addr_t dma;
|
||||
};
|
||||
|
||||
/* statistics message block (smb) */
|
||||
struct atl1_smb {
|
||||
struct stats_msg_block *smb;
|
||||
dma_addr_t dma;
|
||||
};
|
||||
|
||||
/* Statistics counters */
|
||||
struct atl1_sft_stats {
|
||||
u64 rx_packets;
|
||||
u64 tx_packets;
|
||||
u64 rx_bytes;
|
||||
u64 tx_bytes;
|
||||
u64 multicast;
|
||||
u64 collisions;
|
||||
u64 rx_errors;
|
||||
u64 rx_length_errors;
|
||||
u64 rx_crc_errors;
|
||||
u64 rx_frame_errors;
|
||||
u64 rx_fifo_errors;
|
||||
u64 rx_missed_errors;
|
||||
u64 tx_errors;
|
||||
u64 tx_fifo_errors;
|
||||
u64 tx_aborted_errors;
|
||||
u64 tx_window_errors;
|
||||
u64 tx_carrier_errors;
|
||||
u64 tx_pause; /* TX pause frames */
|
||||
u64 excecol; /* TX packets w/ excessive collisions */
|
||||
u64 deffer; /* TX packets deferred */
|
||||
u64 scc; /* packets TX after a single collision */
|
||||
u64 mcc; /* packets TX after multiple collisions */
|
||||
u64 latecol; /* TX packets w/ late collisions */
|
||||
u64 tx_underun; /* TX packets aborted due to TX FIFO underrun
|
||||
* or TRD FIFO underrun */
|
||||
u64 tx_trunc; /* TX packets truncated due to size > MTU */
|
||||
u64 rx_pause; /* num Pause packets received. */
|
||||
u64 rx_rrd_ov;
|
||||
u64 rx_trunc;
|
||||
};
|
||||
|
||||
/* hardware structure */
|
||||
struct atl1_hw {
|
||||
u8 __iomem *hw_addr;
|
||||
struct atl1_adapter *back;
|
||||
enum atl1_dma_order dma_ord;
|
||||
enum atl1_dma_rcb rcb_value;
|
||||
enum atl1_dma_req_block dmar_block;
|
||||
enum atl1_dma_req_block dmaw_block;
|
||||
u8 preamble_len;
|
||||
u8 max_retry;
|
||||
u8 jam_ipg; /* IPG to start JAM for collision based flow
|
||||
* control in half-duplex mode. In units of
|
||||
* 8-bit time */
|
||||
u8 ipgt; /* Desired back to back inter-packet gap.
|
||||
* The default is 96-bit time */
|
||||
u8 min_ifg; /* Minimum number of IFG to enforce in between
|
||||
* receive frames. Frame gap below such IFP
|
||||
* is dropped */
|
||||
u8 ipgr1; /* 64bit Carrier-Sense window */
|
||||
u8 ipgr2; /* 96-bit IPG window */
|
||||
u8 tpd_burst; /* Number of TPD to prefetch in cache-aligned
|
||||
* burst. Each TPD is 16 bytes long */
|
||||
u8 rfd_burst; /* Number of RFD to prefetch in cache-aligned
|
||||
* burst. Each RFD is 12 bytes long */
|
||||
u8 rfd_fetch_gap;
|
||||
u8 rrd_burst; /* Threshold number of RRDs that can be retired
|
||||
* in a burst. Each RRD is 16 bytes long */
|
||||
u8 tpd_fetch_th;
|
||||
u8 tpd_fetch_gap;
|
||||
u16 tx_jumbo_task_th;
|
||||
u16 txf_burst; /* Number of data bytes to read in a cache-
|
||||
* aligned burst. Each SRAM entry is 8 bytes */
|
||||
u16 rx_jumbo_th; /* Jumbo packet size for non-VLAN packet. VLAN
|
||||
* packets should add 4 bytes */
|
||||
u16 rx_jumbo_lkah;
|
||||
u16 rrd_ret_timer; /* RRD retirement timer. Decrement by 1 after
|
||||
* every 512ns passes. */
|
||||
u16 lcol; /* Collision Window */
|
||||
|
||||
u16 cmb_tpd;
|
||||
u16 cmb_rrd;
|
||||
u16 cmb_rx_timer;
|
||||
u16 cmb_tx_timer;
|
||||
u32 smb_timer;
|
||||
u16 media_type;
|
||||
u16 autoneg_advertised;
|
||||
|
||||
u16 mii_autoneg_adv_reg;
|
||||
u16 mii_1000t_ctrl_reg;
|
||||
|
||||
u32 max_frame_size;
|
||||
u32 min_frame_size;
|
||||
|
||||
u16 dev_rev;
|
||||
|
||||
/* spi flash */
|
||||
u8 flash_vendor;
|
||||
|
||||
u8 mac_addr[ETH_ALEN];
|
||||
u8 perm_mac_addr[ETH_ALEN];
|
||||
|
||||
bool phy_configured;
|
||||
};
|
||||
|
||||
struct atl1_adapter {
|
||||
struct net_device *netdev;
|
||||
struct pci_dev *pdev;
|
||||
struct net_device_stats net_stats;
|
||||
struct atl1_sft_stats soft_stats;
|
||||
struct vlan_group *vlgrp;
|
||||
u32 rx_buffer_len;
|
||||
u32 wol;
|
||||
u16 link_speed;
|
||||
u16 link_duplex;
|
||||
spinlock_t lock;
|
||||
struct work_struct tx_timeout_task;
|
||||
struct work_struct link_chg_task;
|
||||
struct work_struct pcie_dma_to_rst_task;
|
||||
struct timer_list watchdog_timer;
|
||||
struct timer_list phy_config_timer;
|
||||
bool phy_timer_pending;
|
||||
|
||||
/* all descriptor rings' memory */
|
||||
struct atl1_ring_header ring_header;
|
||||
|
||||
/* TX */
|
||||
struct atl1_tpd_ring tpd_ring;
|
||||
spinlock_t mb_lock;
|
||||
|
||||
/* RX */
|
||||
struct atl1_rfd_ring rfd_ring;
|
||||
struct atl1_rrd_ring rrd_ring;
|
||||
u64 hw_csum_err;
|
||||
u64 hw_csum_good;
|
||||
u32 msg_enable;
|
||||
u16 imt; /* interrupt moderator timer (2us resolution) */
|
||||
u16 ict; /* interrupt clear timer (2us resolution */
|
||||
struct mii_if_info mii; /* MII interface info */
|
||||
|
||||
u32 bd_number; /* board number */
|
||||
bool pci_using_64;
|
||||
struct atl1_hw hw;
|
||||
struct atl1_smb smb;
|
||||
struct atl1_cmb cmb;
|
||||
};
|
||||
|
||||
#endif /* ATL1_H */
|
|
@ -0,0 +1,433 @@
|
|||
/* atlx.c -- common functions for Attansic network drivers
|
||||
*
|
||||
* Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
|
||||
* Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
|
||||
* Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
|
||||
* Copyright(c) 2007 Atheros Corporation. All rights reserved.
|
||||
*
|
||||
* Derived from Intel e1000 driver
|
||||
* Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59
|
||||
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
/* Including this file like a header is a temporary hack, I promise. -- CHS */
|
||||
#ifndef ATLX_C
|
||||
#define ATLX_C
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/etherdevice.h>
|
||||
#include <linux/if.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/socket.h>
|
||||
#include <linux/sockios.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/workqueue.h>
|
||||
|
||||
#include "atlx.h"
|
||||
|
||||
static struct atlx_spi_flash_dev flash_table[] = {
|
||||
/* MFR_NAME WRSR READ PRGM WREN WRDI RDSR RDID SEC_ERS CHIP_ERS */
|
||||
{"Atmel", 0x00, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62},
|
||||
{"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60},
|
||||
{"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7},
|
||||
};
|
||||
|
||||
static int atlx_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
|
||||
{
|
||||
switch (cmd) {
|
||||
case SIOCGMIIPHY:
|
||||
case SIOCGMIIREG:
|
||||
case SIOCSMIIREG:
|
||||
return atlx_mii_ioctl(netdev, ifr, cmd);
|
||||
default:
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* atlx_set_mac - Change the Ethernet Address of the NIC
|
||||
* @netdev: network interface device structure
|
||||
* @p: pointer to an address structure
|
||||
*
|
||||
* Returns 0 on success, negative on failure
|
||||
*/
|
||||
static int atlx_set_mac(struct net_device *netdev, void *p)
|
||||
{
|
||||
struct atlx_adapter *adapter = netdev_priv(netdev);
|
||||
struct sockaddr *addr = p;
|
||||
|
||||
if (netif_running(netdev))
|
||||
return -EBUSY;
|
||||
|
||||
if (!is_valid_ether_addr(addr->sa_data))
|
||||
return -EADDRNOTAVAIL;
|
||||
|
||||
memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
|
||||
memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
|
||||
|
||||
atlx_set_mac_addr(&adapter->hw);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void atlx_check_for_link(struct atlx_adapter *adapter)
|
||||
{
|
||||
struct net_device *netdev = adapter->netdev;
|
||||
u16 phy_data = 0;
|
||||
|
||||
spin_lock(&adapter->lock);
|
||||
adapter->phy_timer_pending = false;
|
||||
atlx_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
|
||||
atlx_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
|
||||
spin_unlock(&adapter->lock);
|
||||
|
||||
/* notify upper layer link down ASAP */
|
||||
if (!(phy_data & BMSR_LSTATUS)) {
|
||||
/* Link Down */
|
||||
if (netif_carrier_ok(netdev)) {
|
||||
/* old link state: Up */
|
||||
dev_info(&adapter->pdev->dev, "%s link is down\n",
|
||||
netdev->name);
|
||||
adapter->link_speed = SPEED_0;
|
||||
netif_carrier_off(netdev);
|
||||
netif_stop_queue(netdev);
|
||||
}
|
||||
}
|
||||
schedule_work(&adapter->link_chg_task);
|
||||
}
|
||||
|
||||
/*
|
||||
* atlx_set_multi - Multicast and Promiscuous mode set
|
||||
* @netdev: network interface device structure
|
||||
*
|
||||
* The set_multi entry point is called whenever the multicast address
|
||||
* list or the network interface flags are updated. This routine is
|
||||
* responsible for configuring the hardware for proper multicast,
|
||||
* promiscuous mode, and all-multi behavior.
|
||||
*/
|
||||
static void atlx_set_multi(struct net_device *netdev)
|
||||
{
|
||||
struct atlx_adapter *adapter = netdev_priv(netdev);
|
||||
struct atlx_hw *hw = &adapter->hw;
|
||||
struct dev_mc_list *mc_ptr;
|
||||
u32 rctl;
|
||||
u32 hash_value;
|
||||
|
||||
/* Check for Promiscuous and All Multicast modes */
|
||||
rctl = ioread32(hw->hw_addr + REG_MAC_CTRL);
|
||||
if (netdev->flags & IFF_PROMISC)
|
||||
rctl |= MAC_CTRL_PROMIS_EN;
|
||||
else if (netdev->flags & IFF_ALLMULTI) {
|
||||
rctl |= MAC_CTRL_MC_ALL_EN;
|
||||
rctl &= ~MAC_CTRL_PROMIS_EN;
|
||||
} else
|
||||
rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
|
||||
|
||||
iowrite32(rctl, hw->hw_addr + REG_MAC_CTRL);
|
||||
|
||||
/* clear the old settings from the multicast hash table */
|
||||
iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
|
||||
iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
|
||||
|
||||
/* compute mc addresses' hash value ,and put it into hash table */
|
||||
for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
|
||||
hash_value = atlx_hash_mc_addr(hw, mc_ptr->dmi_addr);
|
||||
atlx_hash_set(hw, hash_value);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* atlx_irq_enable - Enable default interrupt generation settings
|
||||
* @adapter: board private structure
|
||||
*/
|
||||
static void atlx_irq_enable(struct atlx_adapter *adapter)
|
||||
{
|
||||
iowrite32(IMR_NORMAL_MASK, adapter->hw.hw_addr + REG_IMR);
|
||||
ioread32(adapter->hw.hw_addr + REG_IMR);
|
||||
}
|
||||
|
||||
/*
|
||||
* atlx_irq_disable - Mask off interrupt generation on the NIC
|
||||
* @adapter: board private structure
|
||||
*/
|
||||
static void atlx_irq_disable(struct atlx_adapter *adapter)
|
||||
{
|
||||
iowrite32(0, adapter->hw.hw_addr + REG_IMR);
|
||||
ioread32(adapter->hw.hw_addr + REG_IMR);
|
||||
synchronize_irq(adapter->pdev->irq);
|
||||
}
|
||||
|
||||
static void atlx_clear_phy_int(struct atlx_adapter *adapter)
|
||||
{
|
||||
u16 phy_data;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&adapter->lock, flags);
|
||||
atlx_read_phy_reg(&adapter->hw, 19, &phy_data);
|
||||
spin_unlock_irqrestore(&adapter->lock, flags);
|
||||
}
|
||||
|
||||
/*
|
||||
* atlx_get_stats - Get System Network Statistics
|
||||
* @netdev: network interface device structure
|
||||
*
|
||||
* Returns the address of the device statistics structure.
|
||||
* The statistics are actually updated from the timer callback.
|
||||
*/
|
||||
static struct net_device_stats *atlx_get_stats(struct net_device *netdev)
|
||||
{
|
||||
struct atlx_adapter *adapter = netdev_priv(netdev);
|
||||
return &adapter->net_stats;
|
||||
}
|
||||
|
||||
/*
|
||||
* atlx_tx_timeout - Respond to a Tx Hang
|
||||
* @netdev: network interface device structure
|
||||
*/
|
||||
static void atlx_tx_timeout(struct net_device *netdev)
|
||||
{
|
||||
struct atlx_adapter *adapter = netdev_priv(netdev);
|
||||
/* Do the reset outside of interrupt context */
|
||||
schedule_work(&adapter->tx_timeout_task);
|
||||
}
|
||||
|
||||
/*
|
||||
* atlx_link_chg_task - deal with link change event Out of interrupt context
|
||||
*/
|
||||
static void atlx_link_chg_task(struct work_struct *work)
|
||||
{
|
||||
struct atlx_adapter *adapter;
|
||||
unsigned long flags;
|
||||
|
||||
adapter = container_of(work, struct atlx_adapter, link_chg_task);
|
||||
|
||||
spin_lock_irqsave(&adapter->lock, flags);
|
||||
atlx_check_link(adapter);
|
||||
spin_unlock_irqrestore(&adapter->lock, flags);
|
||||
}
|
||||
|
||||
static void atlx_vlan_rx_register(struct net_device *netdev,
|
||||
struct vlan_group *grp)
|
||||
{
|
||||
struct atlx_adapter *adapter = netdev_priv(netdev);
|
||||
unsigned long flags;
|
||||
u32 ctrl;
|
||||
|
||||
spin_lock_irqsave(&adapter->lock, flags);
|
||||
/* atlx_irq_disable(adapter); FIXME: confirm/remove */
|
||||
adapter->vlgrp = grp;
|
||||
|
||||
if (grp) {
|
||||
/* enable VLAN tag insert/strip */
|
||||
ctrl = ioread32(adapter->hw.hw_addr + REG_MAC_CTRL);
|
||||
ctrl |= MAC_CTRL_RMV_VLAN;
|
||||
iowrite32(ctrl, adapter->hw.hw_addr + REG_MAC_CTRL);
|
||||
} else {
|
||||
/* disable VLAN tag insert/strip */
|
||||
ctrl = ioread32(adapter->hw.hw_addr + REG_MAC_CTRL);
|
||||
ctrl &= ~MAC_CTRL_RMV_VLAN;
|
||||
iowrite32(ctrl, adapter->hw.hw_addr + REG_MAC_CTRL);
|
||||
}
|
||||
|
||||
/* atlx_irq_enable(adapter); FIXME */
|
||||
spin_unlock_irqrestore(&adapter->lock, flags);
|
||||
}
|
||||
|
||||
static void atlx_restore_vlan(struct atlx_adapter *adapter)
|
||||
{
|
||||
atlx_vlan_rx_register(adapter->netdev, adapter->vlgrp);
|
||||
}
|
||||
|
||||
/*
|
||||
* This is the only thing that needs to be changed to adjust the
|
||||
* maximum number of ports that the driver can manage.
|
||||
*/
|
||||
#define ATL1_MAX_NIC 4
|
||||
|
||||
#define OPTION_UNSET -1
|
||||
#define OPTION_DISABLED 0
|
||||
#define OPTION_ENABLED 1
|
||||
|
||||
#define ATL1_PARAM_INIT { [0 ... ATL1_MAX_NIC] = OPTION_UNSET }
|
||||
|
||||
/*
|
||||
* Interrupt Moderate Timer in units of 2 us
|
||||
*
|
||||
* Valid Range: 10-65535
|
||||
*
|
||||
* Default Value: 100 (200us)
|
||||
*/
|
||||
static int __devinitdata int_mod_timer[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT;
|
||||
static int num_int_mod_timer;
|
||||
module_param_array_named(int_mod_timer, int_mod_timer, int,
|
||||
&num_int_mod_timer, 0);
|
||||
MODULE_PARM_DESC(int_mod_timer, "Interrupt moderator timer");
|
||||
|
||||
/*
|
||||
* flash_vendor
|
||||
*
|
||||
* Valid Range: 0-2
|
||||
*
|
||||
* 0 - Atmel
|
||||
* 1 - SST
|
||||
* 2 - ST
|
||||
*
|
||||
* Default Value: 0
|
||||
*/
|
||||
static int __devinitdata flash_vendor[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT;
|
||||
static int num_flash_vendor;
|
||||
module_param_array_named(flash_vendor, flash_vendor, int, &num_flash_vendor, 0);
|
||||
MODULE_PARM_DESC(flash_vendor, "SPI flash vendor");
|
||||
|
||||
#define DEFAULT_INT_MOD_CNT 100 /* 200us */
|
||||
#define MAX_INT_MOD_CNT 65000
|
||||
#define MIN_INT_MOD_CNT 50
|
||||
|
||||
#define FLASH_VENDOR_DEFAULT 0
|
||||
#define FLASH_VENDOR_MIN 0
|
||||
#define FLASH_VENDOR_MAX 2
|
||||
|
||||
struct atl1_option {
|
||||
enum { enable_option, range_option, list_option } type;
|
||||
char *name;
|
||||
char *err;
|
||||
int def;
|
||||
union {
|
||||
struct { /* range_option info */
|
||||
int min;
|
||||
int max;
|
||||
} r;
|
||||
struct { /* list_option info */
|
||||
int nr;
|
||||
struct atl1_opt_list {
|
||||
int i;
|
||||
char *str;
|
||||
} *p;
|
||||
} l;
|
||||
} arg;
|
||||
};
|
||||
|
||||
static int __devinit atl1_validate_option(int *value, struct atl1_option *opt,
|
||||
struct pci_dev *pdev)
|
||||
{
|
||||
if (*value == OPTION_UNSET) {
|
||||
*value = opt->def;
|
||||
return 0;
|
||||
}
|
||||
|
||||
switch (opt->type) {
|
||||
case enable_option:
|
||||
switch (*value) {
|
||||
case OPTION_ENABLED:
|
||||
dev_info(&pdev->dev, "%s enabled\n", opt->name);
|
||||
return 0;
|
||||
case OPTION_DISABLED:
|
||||
dev_info(&pdev->dev, "%s disabled\n", opt->name);
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
case range_option:
|
||||
if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
|
||||
dev_info(&pdev->dev, "%s set to %i\n", opt->name,
|
||||
*value);
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
case list_option:{
|
||||
int i;
|
||||
struct atl1_opt_list *ent;
|
||||
|
||||
for (i = 0; i < opt->arg.l.nr; i++) {
|
||||
ent = &opt->arg.l.p[i];
|
||||
if (*value == ent->i) {
|
||||
if (ent->str[0] != '\0')
|
||||
dev_info(&pdev->dev, "%s\n",
|
||||
ent->str);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
dev_info(&pdev->dev, "invalid %s specified (%i) %s\n",
|
||||
opt->name, *value, opt->err);
|
||||
*value = opt->def;
|
||||
return -1;
|
||||
}
|
||||
|
||||
/*
|
||||
* atl1_check_options - Range Checking for Command Line Parameters
|
||||
* @adapter: board private structure
|
||||
*
|
||||
* This routine checks all command line parameters for valid user
|
||||
* input. If an invalid value is given, or if no user specified
|
||||
* value exists, a default value is used. The final value is stored
|
||||
* in a variable in the adapter structure.
|
||||
*/
|
||||
void __devinit atl1_check_options(struct atl1_adapter *adapter)
|
||||
{
|
||||
struct pci_dev *pdev = adapter->pdev;
|
||||
int bd = adapter->bd_number;
|
||||
if (bd >= ATL1_MAX_NIC) {
|
||||
dev_notice(&pdev->dev, "no configuration for board#%i\n", bd);
|
||||
dev_notice(&pdev->dev, "using defaults for all values\n");
|
||||
}
|
||||
{ /* Interrupt Moderate Timer */
|
||||
struct atl1_option opt = {
|
||||
.type = range_option,
|
||||
.name = "Interrupt Moderator Timer",
|
||||
.err = "using default of "
|
||||
__MODULE_STRING(DEFAULT_INT_MOD_CNT),
|
||||
.def = DEFAULT_INT_MOD_CNT,
|
||||
.arg = {.r = {.min = MIN_INT_MOD_CNT,
|
||||
.max = MAX_INT_MOD_CNT} }
|
||||
};
|
||||
int val;
|
||||
if (num_int_mod_timer > bd) {
|
||||
val = int_mod_timer[bd];
|
||||
atl1_validate_option(&val, &opt, pdev);
|
||||
adapter->imt = (u16) val;
|
||||
} else
|
||||
adapter->imt = (u16) (opt.def);
|
||||
}
|
||||
|
||||
{ /* Flash Vendor */
|
||||
struct atl1_option opt = {
|
||||
.type = range_option,
|
||||
.name = "SPI Flash Vendor",
|
||||
.err = "using default of "
|
||||
__MODULE_STRING(FLASH_VENDOR_DEFAULT),
|
||||
.def = DEFAULT_INT_MOD_CNT,
|
||||
.arg = {.r = {.min = FLASH_VENDOR_MIN,
|
||||
.max = FLASH_VENDOR_MAX} }
|
||||
};
|
||||
int val;
|
||||
if (num_flash_vendor > bd) {
|
||||
val = flash_vendor[bd];
|
||||
atl1_validate_option(&val, &opt, pdev);
|
||||
adapter->hw.flash_vendor = (u8) val;
|
||||
} else
|
||||
adapter->hw.flash_vendor = (u8) (opt.def);
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* ATLX_C */
|
|
@ -0,0 +1,506 @@
|
|||
/* atlx_hw.h -- common hardware definitions for Attansic network drivers
|
||||
*
|
||||
* Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
|
||||
* Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
|
||||
* Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
|
||||
* Copyright(c) 2007 Atheros Corporation. All rights reserved.
|
||||
*
|
||||
* Derived from Intel e1000 driver
|
||||
* Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59
|
||||
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef ATLX_H
|
||||
#define ATLX_H
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#define ATLX_DRIVER_VERSION "2.1.1"
|
||||
MODULE_AUTHOR("Xiong Huang <xiong.huang@atheros.com>, \
|
||||
Chris Snook <csnook@redhat.com>, Jay Cliburn <jcliburn@gmail.com>");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_VERSION(ATLX_DRIVER_VERSION);
|
||||
|
||||
#define ATLX_ERR_PHY 2
|
||||
#define ATLX_ERR_PHY_SPEED 7
|
||||
#define ATLX_ERR_PHY_RES 8
|
||||
|
||||
#define SPEED_0 0xffff
|
||||
#define SPEED_10 10
|
||||
#define SPEED_100 100
|
||||
#define SPEED_1000 1000
|
||||
#define HALF_DUPLEX 1
|
||||
#define FULL_DUPLEX 2
|
||||
|
||||
#define MEDIA_TYPE_AUTO_SENSOR 0
|
||||
|
||||
/* register definitions */
|
||||
#define REG_PM_CTRLSTAT 0x44
|
||||
|
||||
#define REG_PCIE_CAP_LIST 0x58
|
||||
|
||||
#define REG_VPD_CAP 0x6C
|
||||
#define VPD_CAP_ID_MASK 0xFF
|
||||
#define VPD_CAP_ID_SHIFT 0
|
||||
#define VPD_CAP_NEXT_PTR_MASK 0xFF
|
||||
#define VPD_CAP_NEXT_PTR_SHIFT 8
|
||||
#define VPD_CAP_VPD_ADDR_MASK 0x7FFF
|
||||
#define VPD_CAP_VPD_ADDR_SHIFT 16
|
||||
#define VPD_CAP_VPD_FLAG 0x80000000
|
||||
|
||||
#define REG_VPD_DATA 0x70
|
||||
|
||||
#define REG_SPI_FLASH_CTRL 0x200
|
||||
#define SPI_FLASH_CTRL_STS_NON_RDY 0x1
|
||||
#define SPI_FLASH_CTRL_STS_WEN 0x2
|
||||
#define SPI_FLASH_CTRL_STS_WPEN 0x80
|
||||
#define SPI_FLASH_CTRL_DEV_STS_MASK 0xFF
|
||||
#define SPI_FLASH_CTRL_DEV_STS_SHIFT 0
|
||||
#define SPI_FLASH_CTRL_INS_MASK 0x7
|
||||
#define SPI_FLASH_CTRL_INS_SHIFT 8
|
||||
#define SPI_FLASH_CTRL_START 0x800
|
||||
#define SPI_FLASH_CTRL_EN_VPD 0x2000
|
||||
#define SPI_FLASH_CTRL_LDSTART 0x8000
|
||||
#define SPI_FLASH_CTRL_CS_HI_MASK 0x3
|
||||
#define SPI_FLASH_CTRL_CS_HI_SHIFT 16
|
||||
#define SPI_FLASH_CTRL_CS_HOLD_MASK 0x3
|
||||
#define SPI_FLASH_CTRL_CS_HOLD_SHIFT 18
|
||||
#define SPI_FLASH_CTRL_CLK_LO_MASK 0x3
|
||||
#define SPI_FLASH_CTRL_CLK_LO_SHIFT 20
|
||||
#define SPI_FLASH_CTRL_CLK_HI_MASK 0x3
|
||||
#define SPI_FLASH_CTRL_CLK_HI_SHIFT 22
|
||||
#define SPI_FLASH_CTRL_CS_SETUP_MASK 0x3
|
||||
#define SPI_FLASH_CTRL_CS_SETUP_SHIFT 24
|
||||
#define SPI_FLASH_CTRL_EROM_PGSZ_MASK 0x3
|
||||
#define SPI_FLASH_CTRL_EROM_PGSZ_SHIFT 26
|
||||
#define SPI_FLASH_CTRL_WAIT_READY 0x10000000
|
||||
|
||||
#define REG_SPI_ADDR 0x204
|
||||
|
||||
#define REG_SPI_DATA 0x208
|
||||
|
||||
#define REG_SPI_FLASH_CONFIG 0x20C
|
||||
#define SPI_FLASH_CONFIG_LD_ADDR_MASK 0xFFFFFF
|
||||
#define SPI_FLASH_CONFIG_LD_ADDR_SHIFT 0
|
||||
#define SPI_FLASH_CONFIG_VPD_ADDR_MASK 0x3
|
||||
#define SPI_FLASH_CONFIG_VPD_ADDR_SHIFT 24
|
||||
#define SPI_FLASH_CONFIG_LD_EXIST 0x4000000
|
||||
|
||||
#define REG_SPI_FLASH_OP_PROGRAM 0x210
|
||||
#define REG_SPI_FLASH_OP_SC_ERASE 0x211
|
||||
#define REG_SPI_FLASH_OP_CHIP_ERASE 0x212
|
||||
#define REG_SPI_FLASH_OP_RDID 0x213
|
||||
#define REG_SPI_FLASH_OP_WREN 0x214
|
||||
#define REG_SPI_FLASH_OP_RDSR 0x215
|
||||
#define REG_SPI_FLASH_OP_WRSR 0x216
|
||||
#define REG_SPI_FLASH_OP_READ 0x217
|
||||
|
||||
#define REG_TWSI_CTRL 0x218
|
||||
#define TWSI_CTRL_LD_OFFSET_MASK 0xFF
|
||||
#define TWSI_CTRL_LD_OFFSET_SHIFT 0
|
||||
#define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7
|
||||
#define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8
|
||||
#define TWSI_CTRL_SW_LDSTART 0x800
|
||||
#define TWSI_CTRL_HW_LDSTART 0x1000
|
||||
#define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x7F
|
||||
#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15
|
||||
#define TWSI_CTRL_LD_EXIST 0x400000
|
||||
#define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3
|
||||
#define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23
|
||||
#define TWSI_CTRL_FREQ_SEL_100K 0
|
||||
#define TWSI_CTRL_FREQ_SEL_200K 1
|
||||
#define TWSI_CTRL_FREQ_SEL_300K 2
|
||||
#define TWSI_CTRL_FREQ_SEL_400K 3
|
||||
#define TWSI_CTRL_SMB_SLV_ADDR /* FIXME: define or remove */
|
||||
#define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3
|
||||
#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24
|
||||
|
||||
#define REG_PCIE_DEV_MISC_CTRL 0x21C
|
||||
#define PCIE_DEV_MISC_CTRL_EXT_PIPE 0x2
|
||||
#define PCIE_DEV_MISC_CTRL_RETRY_BUFDIS 0x1
|
||||
#define PCIE_DEV_MISC_CTRL_SPIROM_EXIST 0x4
|
||||
#define PCIE_DEV_MISC_CTRL_SERDES_ENDIAN 0x8
|
||||
#define PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN 0x10
|
||||
|
||||
#define REG_PCIE_PHYMISC 0x1000
|
||||
#define PCIE_PHYMISC_FORCE_RCV_DET 0x4
|
||||
|
||||
#define REG_PCIE_DLL_TX_CTRL1 0x1104
|
||||
#define PCIE_DLL_TX_CTRL1_SEL_NOR_CLK 0x400
|
||||
#define PCIE_DLL_TX_CTRL1_DEF 0x568
|
||||
|
||||
#define REG_LTSSM_TEST_MODE 0x12FC
|
||||
#define LTSSM_TEST_MODE_DEF 0x6500
|
||||
|
||||
/* Master Control Register */
|
||||
#define REG_MASTER_CTRL 0x1400
|
||||
#define MASTER_CTRL_SOFT_RST 0x1
|
||||
#define MASTER_CTRL_MTIMER_EN 0x2
|
||||
#define MASTER_CTRL_ITIMER_EN 0x4
|
||||
#define MASTER_CTRL_MANUAL_INT 0x8
|
||||
#define MASTER_CTRL_REV_NUM_SHIFT 16
|
||||
#define MASTER_CTRL_REV_NUM_MASK 0xFF
|
||||
#define MASTER_CTRL_DEV_ID_SHIFT 24
|
||||
#define MASTER_CTRL_DEV_ID_MASK 0xFF
|
||||
|
||||
/* Timer Initial Value Register */
|
||||
#define REG_MANUAL_TIMER_INIT 0x1404
|
||||
|
||||
/* IRQ Moderator Timer Initial Value Register */
|
||||
#define REG_IRQ_MODU_TIMER_INIT 0x1408
|
||||
|
||||
#define REG_PHY_ENABLE 0x140C
|
||||
|
||||
/* IRQ Anti-Lost Timer Initial Value Register */
|
||||
#define REG_CMBDISDMA_TIMER 0x140E
|
||||
|
||||
/* Block IDLE Status Register */
|
||||
#define REG_IDLE_STATUS 0x1410
|
||||
|
||||
/* MDIO Control Register */
|
||||
#define REG_MDIO_CTRL 0x1414
|
||||
#define MDIO_DATA_MASK 0xFFFF
|
||||
#define MDIO_DATA_SHIFT 0
|
||||
#define MDIO_REG_ADDR_MASK 0x1F
|
||||
#define MDIO_REG_ADDR_SHIFT 16
|
||||
#define MDIO_RW 0x200000
|
||||
#define MDIO_SUP_PREAMBLE 0x400000
|
||||
#define MDIO_START 0x800000
|
||||
#define MDIO_CLK_SEL_SHIFT 24
|
||||
#define MDIO_CLK_25_4 0
|
||||
#define MDIO_CLK_25_6 2
|
||||
#define MDIO_CLK_25_8 3
|
||||
#define MDIO_CLK_25_10 4
|
||||
#define MDIO_CLK_25_14 5
|
||||
#define MDIO_CLK_25_20 6
|
||||
#define MDIO_CLK_25_28 7
|
||||
#define MDIO_BUSY 0x8000000
|
||||
|
||||
/* MII PHY Status Register */
|
||||
#define REG_PHY_STATUS 0x1418
|
||||
|
||||
/* BIST Control and Status Register0 (for the Packet Memory) */
|
||||
#define REG_BIST0_CTRL 0x141C
|
||||
#define BIST0_NOW 0x1
|
||||
#define BIST0_SRAM_FAIL 0x2
|
||||
#define BIST0_FUSE_FLAG 0x4
|
||||
#define REG_BIST1_CTRL 0x1420
|
||||
#define BIST1_NOW 0x1
|
||||
#define BIST1_SRAM_FAIL 0x2
|
||||
#define BIST1_FUSE_FLAG 0x4
|
||||
|
||||
/* SerDes Lock Detect Control and Status Register */
|
||||
#define REG_SERDES_LOCK 0x1424
|
||||
#define SERDES_LOCK_DETECT 1
|
||||
#define SERDES_LOCK_DETECT_EN 2
|
||||
|
||||
/* MAC Control Register */
|
||||
#define REG_MAC_CTRL 0x1480
|
||||
#define MAC_CTRL_TX_EN 1
|
||||
#define MAC_CTRL_RX_EN 2
|
||||
#define MAC_CTRL_TX_FLOW 4
|
||||
#define MAC_CTRL_RX_FLOW 8
|
||||
#define MAC_CTRL_LOOPBACK 0x10
|
||||
#define MAC_CTRL_DUPLX 0x20
|
||||
#define MAC_CTRL_ADD_CRC 0x40
|
||||
#define MAC_CTRL_PAD 0x80
|
||||
#define MAC_CTRL_LENCHK 0x100
|
||||
#define MAC_CTRL_HUGE_EN 0x200
|
||||
#define MAC_CTRL_PRMLEN_SHIFT 10
|
||||
#define MAC_CTRL_PRMLEN_MASK 0xF
|
||||
#define MAC_CTRL_RMV_VLAN 0x4000
|
||||
#define MAC_CTRL_PROMIS_EN 0x8000
|
||||
#define MAC_CTRL_MC_ALL_EN 0x2000000
|
||||
#define MAC_CTRL_BC_EN 0x4000000
|
||||
|
||||
/* MAC IPG/IFG Control Register */
|
||||
#define REG_MAC_IPG_IFG 0x1484
|
||||
#define MAC_IPG_IFG_IPGT_SHIFT 0
|
||||
#define MAC_IPG_IFG_IPGT_MASK 0x7F
|
||||
#define MAC_IPG_IFG_MIFG_SHIFT 8
|
||||
#define MAC_IPG_IFG_MIFG_MASK 0xFF
|
||||
#define MAC_IPG_IFG_IPGR1_SHIFT 16
|
||||
#define MAC_IPG_IFG_IPGR1_MASK 0x7F
|
||||
#define MAC_IPG_IFG_IPGR2_SHIFT 24
|
||||
#define MAC_IPG_IFG_IPGR2_MASK 0x7F
|
||||
|
||||
/* MAC STATION ADDRESS */
|
||||
#define REG_MAC_STA_ADDR 0x1488
|
||||
|
||||
/* Hash table for multicast address */
|
||||
#define REG_RX_HASH_TABLE 0x1490
|
||||
|
||||
/* MAC Half-Duplex Control Register */
|
||||
#define REG_MAC_HALF_DUPLX_CTRL 0x1498
|
||||
#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0
|
||||
#define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3FF
|
||||
#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12
|
||||
#define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xF
|
||||
#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000
|
||||
#define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000
|
||||
#define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000
|
||||
#define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000
|
||||
#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20
|
||||
#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xF
|
||||
#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24
|
||||
#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xF
|
||||
|
||||
/* Maximum Frame Length Control Register */
|
||||
#define REG_MTU 0x149C
|
||||
|
||||
/* Wake-On-Lan control register */
|
||||
#define REG_WOL_CTRL 0x14A0
|
||||
#define WOL_PATTERN_EN 0x1
|
||||
#define WOL_PATTERN_PME_EN 0x2
|
||||
#define WOL_MAGIC_EN 0x4
|
||||
#define WOL_MAGIC_PME_EN 0x8
|
||||
#define WOL_LINK_CHG_EN 0x10
|
||||
#define WOL_LINK_CHG_PME_EN 0x20
|
||||
#define WOL_PATTERN_ST 0x100
|
||||
#define WOL_MAGIC_ST 0x200
|
||||
#define WOL_LINKCHG_ST 0x400
|
||||
#define WOL_PT0_EN 0x10000
|
||||
#define WOL_PT1_EN 0x20000
|
||||
#define WOL_PT2_EN 0x40000
|
||||
#define WOL_PT3_EN 0x80000
|
||||
#define WOL_PT4_EN 0x100000
|
||||
#define WOL_PT0_MATCH 0x1000000
|
||||
#define WOL_PT1_MATCH 0x2000000
|
||||
#define WOL_PT2_MATCH 0x4000000
|
||||
#define WOL_PT3_MATCH 0x8000000
|
||||
#define WOL_PT4_MATCH 0x10000000
|
||||
|
||||
/* Internal SRAM Partition Register, high 32 bits */
|
||||
#define REG_SRAM_RFD_ADDR 0x1500
|
||||
|
||||
/* Descriptor Control register, high 32 bits */
|
||||
#define REG_DESC_BASE_ADDR_HI 0x1540
|
||||
|
||||
/* Interrupt Status Register */
|
||||
#define REG_ISR 0x1600
|
||||
#define ISR_UR_DETECTED 0x1000000
|
||||
#define ISR_FERR_DETECTED 0x2000000
|
||||
#define ISR_NFERR_DETECTED 0x4000000
|
||||
#define ISR_CERR_DETECTED 0x8000000
|
||||
#define ISR_PHY_LINKDOWN 0x10000000
|
||||
#define ISR_DIS_INT 0x80000000
|
||||
|
||||
/* Interrupt Mask Register */
|
||||
#define REG_IMR 0x1604
|
||||
|
||||
#define REG_RFD_RRD_IDX 0x1800
|
||||
#define REG_TPD_IDX 0x1804
|
||||
|
||||
/* MII definitions */
|
||||
|
||||
/* PHY Common Register */
|
||||
#define MII_ATLX_CR 0x09
|
||||
#define MII_ATLX_SR 0x0A
|
||||
#define MII_ATLX_ESR 0x0F
|
||||
#define MII_ATLX_PSCR 0x10
|
||||
#define MII_ATLX_PSSR 0x11
|
||||
|
||||
/* PHY Control Register */
|
||||
#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100,
|
||||
* 00=10
|
||||
*/
|
||||
#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
|
||||
#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
|
||||
#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
|
||||
#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
|
||||
#define MII_CR_POWER_DOWN 0x0800 /* Power down */
|
||||
#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
|
||||
#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100,
|
||||
* 00=10
|
||||
*/
|
||||
#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
|
||||
#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
|
||||
#define MII_CR_SPEED_MASK 0x2040
|
||||
#define MII_CR_SPEED_1000 0x0040
|
||||
#define MII_CR_SPEED_100 0x2000
|
||||
#define MII_CR_SPEED_10 0x0000
|
||||
|
||||
/* PHY Status Register */
|
||||
#define MII_SR_EXTENDED_CAPS 0x0001 /* Ext register capabilities */
|
||||
#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
|
||||
#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
|
||||
#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
|
||||
#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
|
||||
#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
|
||||
#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
|
||||
#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext stat info in Reg 0x0F */
|
||||
#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
|
||||
#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
|
||||
#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
|
||||
#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
|
||||
#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
|
||||
#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
|
||||
#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
|
||||
|
||||
/* Link partner ability register */
|
||||
#define MII_LPA_SLCT 0x001f /* Same as advertise selector */
|
||||
#define MII_LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
|
||||
#define MII_LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
|
||||
#define MII_LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
|
||||
#define MII_LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
|
||||
#define MII_LPA_100BASE4 0x0200 /* 100BASE-T4 */
|
||||
#define MII_LPA_PAUSE 0x0400 /* PAUSE */
|
||||
#define MII_LPA_ASYPAUSE 0x0800 /* Asymmetrical PAUSE */
|
||||
#define MII_LPA_RFAULT 0x2000 /* Link partner faulted */
|
||||
#define MII_LPA_LPACK 0x4000 /* Link partner acked us */
|
||||
#define MII_LPA_NPAGE 0x8000 /* Next page bit */
|
||||
|
||||
/* Autoneg Advertisement Register */
|
||||
#define MII_AR_SELECTOR_FIELD 0x0001 /* IEEE 802.3 CSMA/CD */
|
||||
#define MII_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
|
||||
#define MII_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
|
||||
#define MII_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
|
||||
#define MII_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
|
||||
#define MII_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
|
||||
#define MII_AR_PAUSE 0x0400 /* Pause operation desired */
|
||||
#define MII_AR_ASM_DIR 0x0800 /* Asymmetric Pause Dir bit */
|
||||
#define MII_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
|
||||
#define MII_AR_NEXT_PAGE 0x8000 /* Next Page ability support */
|
||||
#define MII_AR_SPEED_MASK 0x01E0
|
||||
#define MII_AR_DEFAULT_CAP_MASK 0x0DE0
|
||||
|
||||
/* 1000BASE-T Control Register */
|
||||
#define MII_ATLX_CR_1000T_HD_CAPS 0x0100 /* Adv 1000T HD cap */
|
||||
#define MII_ATLX_CR_1000T_FD_CAPS 0x0200 /* Adv 1000T FD cap */
|
||||
#define MII_ATLX_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device,
|
||||
* 0=DTE device */
|
||||
#define MII_ATLX_CR_1000T_MS_VALUE 0x0800 /* 1=Config PHY as Master,
|
||||
* 0=Configure PHY as Slave */
|
||||
#define MII_ATLX_CR_1000T_MS_ENABLE 0x1000 /* 1=Man Master/Slave config,
|
||||
* 0=Auto Master/Slave config
|
||||
*/
|
||||
#define MII_ATLX_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
|
||||
#define MII_ATLX_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
|
||||
#define MII_ATLX_CR_1000T_TEST_MODE_2 0x4000 /* Master Xmit Jitter test */
|
||||
#define MII_ATLX_CR_1000T_TEST_MODE_3 0x6000 /* Slave Xmit Jitter test */
|
||||
#define MII_ATLX_CR_1000T_TEST_MODE_4 0x8000 /* Xmitter Distortion test */
|
||||
#define MII_ATLX_CR_1000T_SPEED_MASK 0x0300
|
||||
#define MII_ATLX_CR_1000T_DEFAULT_CAP_MASK 0x0300
|
||||
|
||||
/* 1000BASE-T Status Register */
|
||||
#define MII_ATLX_SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
|
||||
#define MII_ATLX_SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
|
||||
#define MII_ATLX_SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
|
||||
#define MII_ATLX_SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
|
||||
#define MII_ATLX_SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master
|
||||
* 0=Slave
|
||||
*/
|
||||
#define MII_ATLX_SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config
|
||||
* fault */
|
||||
#define MII_ATLX_SR_1000T_REMOTE_RX_STATUS_SHIFT 12
|
||||
#define MII_ATLX_SR_1000T_LOCAL_RX_STATUS_SHIFT 13
|
||||
|
||||
/* Extended Status Register */
|
||||
#define MII_ATLX_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
|
||||
#define MII_ATLX_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
|
||||
#define MII_ATLX_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
|
||||
#define MII_ATLX_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
|
||||
|
||||
/* ATLX PHY Specific Control Register */
|
||||
#define MII_ATLX_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Func disabled */
|
||||
#define MII_ATLX_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enbld */
|
||||
#define MII_ATLX_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
|
||||
#define MII_ATLX_PSCR_MAC_POWERDOWN 0x0008
|
||||
#define MII_ATLX_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low
|
||||
* 0=CLK125 toggling
|
||||
*/
|
||||
#define MII_ATLX_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5,
|
||||
* Manual MDI configuration
|
||||
*/
|
||||
#define MII_ATLX_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
|
||||
#define MII_ATLX_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover
|
||||
* 100BASE-TX/10BASE-T: MDI
|
||||
* Mode */
|
||||
#define MII_ATLX_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
|
||||
* all speeds.
|
||||
*/
|
||||
#define MII_ATLX_PSCR_10BT_EXT_DIST_ENABLE 0x0080 /* 1=Enable Extended
|
||||
* 10BASE-T distance
|
||||
* (Lower 10BASE-T RX
|
||||
* Threshold)
|
||||
* 0=Normal 10BASE-T RX
|
||||
* Threshold
|
||||
*/
|
||||
#define MII_ATLX_PSCR_MII_5BIT_ENABLE 0x0100 /* 1=5-Bit interface in
|
||||
* 100BASE-TX
|
||||
* 0=MII interface in
|
||||
* 100BASE-TX
|
||||
*/
|
||||
#define MII_ATLX_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler dsbl */
|
||||
#define MII_ATLX_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
|
||||
#define MII_ATLX_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
|
||||
#define MII_ATLX_PSCR_POLARITY_REVERSAL_SHIFT 1
|
||||
#define MII_ATLX_PSCR_AUTO_X_MODE_SHIFT 5
|
||||
#define MII_ATLX_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
|
||||
|
||||
/* ATLX PHY Specific Status Register */
|
||||
#define MII_ATLX_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
|
||||
#define MII_ATLX_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
|
||||
#define MII_ATLX_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
|
||||
#define MII_ATLX_PSSR_10MBS 0x0000 /* 00=10Mbs */
|
||||
#define MII_ATLX_PSSR_100MBS 0x4000 /* 01=100Mbs */
|
||||
#define MII_ATLX_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
|
||||
|
||||
/* PCI Command Register Bit Definitions */
|
||||
#define PCI_REG_COMMAND 0x04 /* PCI Command Register */
|
||||
#define CMD_IO_SPACE 0x0001
|
||||
#define CMD_MEMORY_SPACE 0x0002
|
||||
#define CMD_BUS_MASTER 0x0004
|
||||
|
||||
/* Wake Up Filter Control */
|
||||
#define ATLX_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
|
||||
#define ATLX_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
|
||||
#define ATLX_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
|
||||
#define ATLX_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */
|
||||
#define ATLX_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
|
||||
|
||||
#define ADVERTISE_10_HALF 0x0001
|
||||
#define ADVERTISE_10_FULL 0x0002
|
||||
#define ADVERTISE_100_HALF 0x0004
|
||||
#define ADVERTISE_100_FULL 0x0008
|
||||
#define ADVERTISE_1000_HALF 0x0010
|
||||
#define ADVERTISE_1000_FULL 0x0020
|
||||
#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds */
|
||||
#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds */
|
||||
|
||||
#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
|
||||
#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
|
||||
|
||||
/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA */
|
||||
#define EEPROM_SUM 0xBABA
|
||||
#define NODE_ADDRESS_SIZE 6
|
||||
|
||||
struct atlx_spi_flash_dev {
|
||||
const char *manu_name; /* manufacturer id */
|
||||
/* op-code */
|
||||
u8 cmd_wrsr;
|
||||
u8 cmd_read;
|
||||
u8 cmd_program;
|
||||
u8 cmd_wren;
|
||||
u8 cmd_wrdi;
|
||||
u8 cmd_rdsr;
|
||||
u8 cmd_rdid;
|
||||
u8 cmd_sector_erase;
|
||||
u8 cmd_chip_erase;
|
||||
};
|
||||
|
||||
#endif /* ATLX_H */
|
|
@ -36,6 +36,9 @@
|
|||
#include "ixgbe_type.h"
|
||||
#include "ixgbe_common.h"
|
||||
|
||||
#ifdef CONFIG_DCA
|
||||
#include <linux/dca.h>
|
||||
#endif
|
||||
|
||||
#define IXGBE_ERR(args...) printk(KERN_ERR "ixgbe: " args)
|
||||
|
||||
|
@ -120,7 +123,6 @@ struct ixgbe_queue_stats {
|
|||
};
|
||||
|
||||
struct ixgbe_ring {
|
||||
struct ixgbe_adapter *adapter; /* backlink */
|
||||
void *desc; /* descriptor ring memory */
|
||||
dma_addr_t dma; /* phys. address of descriptor ring */
|
||||
unsigned int size; /* length in bytes */
|
||||
|
@ -128,6 +130,7 @@ struct ixgbe_ring {
|
|||
unsigned int next_to_use;
|
||||
unsigned int next_to_clean;
|
||||
|
||||
int queue_index; /* needed for multiqueue queue management */
|
||||
union {
|
||||
struct ixgbe_tx_buffer *tx_buffer_info;
|
||||
struct ixgbe_rx_buffer *rx_buffer_info;
|
||||
|
@ -136,8 +139,21 @@ struct ixgbe_ring {
|
|||
u16 head;
|
||||
u16 tail;
|
||||
|
||||
unsigned int total_bytes;
|
||||
unsigned int total_packets;
|
||||
|
||||
u16 reg_idx; /* holds the special value that gets the hardware register
|
||||
* offset associated with this ring, which is different
|
||||
* for DCE and RSS modes */
|
||||
|
||||
#ifdef CONFIG_DCA
|
||||
/* cpu for tx queue */
|
||||
int cpu;
|
||||
#endif
|
||||
struct ixgbe_queue_stats stats;
|
||||
u8 v_idx; /* maps directly to the index for this ring in the hardware
|
||||
* vector array, can also be used for finding the bit in EICR
|
||||
* and friends that represents the vector for this ring */
|
||||
|
||||
u32 eims_value;
|
||||
u16 itr_register;
|
||||
|
@ -146,6 +162,33 @@ struct ixgbe_ring {
|
|||
u16 work_limit; /* max work per interrupt */
|
||||
};
|
||||
|
||||
#define RING_F_VMDQ 1
|
||||
#define RING_F_RSS 2
|
||||
#define IXGBE_MAX_RSS_INDICES 16
|
||||
#define IXGBE_MAX_VMDQ_INDICES 16
|
||||
struct ixgbe_ring_feature {
|
||||
int indices;
|
||||
int mask;
|
||||
};
|
||||
|
||||
#define MAX_RX_QUEUES 64
|
||||
#define MAX_TX_QUEUES 32
|
||||
|
||||
/* MAX_MSIX_Q_VECTORS of these are allocated,
|
||||
* but we only use one per queue-specific vector.
|
||||
*/
|
||||
struct ixgbe_q_vector {
|
||||
struct ixgbe_adapter *adapter;
|
||||
struct napi_struct napi;
|
||||
DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
|
||||
DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
|
||||
u8 rxr_count; /* Rx ring count assigned to this vector */
|
||||
u8 txr_count; /* Tx ring count assigned to this vector */
|
||||
u8 tx_eitr;
|
||||
u8 rx_eitr;
|
||||
u32 eitr;
|
||||
};
|
||||
|
||||
/* Helper macros to switch between ints/sec and what the register uses.
|
||||
* And yes, it's the same math going both ways.
|
||||
*/
|
||||
|
@ -166,6 +209,14 @@ struct ixgbe_ring {
|
|||
|
||||
#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
|
||||
|
||||
#define OTHER_VECTOR 1
|
||||
#define NON_Q_VECTORS (OTHER_VECTOR)
|
||||
|
||||
#define MAX_MSIX_Q_VECTORS 16
|
||||
#define MIN_MSIX_Q_VECTORS 2
|
||||
#define MAX_MSIX_COUNT (MAX_MSIX_Q_VECTORS + NON_Q_VECTORS)
|
||||
#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
|
||||
|
||||
/* board specific private data structure */
|
||||
struct ixgbe_adapter {
|
||||
struct timer_list watchdog_timer;
|
||||
|
@ -173,10 +224,16 @@ struct ixgbe_adapter {
|
|||
u16 bd_number;
|
||||
u16 rx_buf_len;
|
||||
struct work_struct reset_task;
|
||||
struct ixgbe_q_vector q_vector[MAX_MSIX_Q_VECTORS];
|
||||
char name[MAX_MSIX_COUNT][IFNAMSIZ + 5];
|
||||
|
||||
/* Interrupt Throttle Rate */
|
||||
u32 itr_setting;
|
||||
u16 eitr_low;
|
||||
u16 eitr_high;
|
||||
|
||||
/* TX */
|
||||
struct ixgbe_ring *tx_ring; /* One per active queue */
|
||||
struct napi_struct napi;
|
||||
u64 restart_queue;
|
||||
u64 lsc_int;
|
||||
u64 hw_tso_ctxt;
|
||||
|
@ -192,22 +249,27 @@ struct ixgbe_adapter {
|
|||
u64 non_eop_descs;
|
||||
int num_tx_queues;
|
||||
int num_rx_queues;
|
||||
int num_msix_vectors;
|
||||
struct ixgbe_ring_feature ring_feature[3];
|
||||
struct msix_entry *msix_entries;
|
||||
|
||||
u64 rx_hdr_split;
|
||||
u32 alloc_rx_page_failed;
|
||||
u32 alloc_rx_buff_failed;
|
||||
|
||||
/* Some features need tri-state capability,
|
||||
* thus the additional *_CAPABLE flags.
|
||||
*/
|
||||
u32 flags;
|
||||
#define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
|
||||
#define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1 << 0)
|
||||
#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 1)
|
||||
#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 2)
|
||||
#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 3)
|
||||
#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 4)
|
||||
|
||||
/* Interrupt Throttle Rate */
|
||||
u32 rx_eitr;
|
||||
u32 tx_eitr;
|
||||
#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 5)
|
||||
#define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 6)
|
||||
#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 7)
|
||||
#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 8)
|
||||
|
||||
/* OS defined structs */
|
||||
struct net_device *netdev;
|
||||
|
@ -218,7 +280,10 @@ struct ixgbe_adapter {
|
|||
struct ixgbe_hw hw;
|
||||
u16 msg_enable;
|
||||
struct ixgbe_hw_stats stats;
|
||||
char lsc_name[IFNAMSIZ + 5];
|
||||
|
||||
/* Interrupt Throttle Rate */
|
||||
u32 rx_eitr;
|
||||
u32 tx_eitr;
|
||||
|
||||
unsigned long state;
|
||||
u64 tx_busy;
|
||||
|
|
|
@ -246,13 +246,26 @@ static int ixgbe_set_tx_csum(struct net_device *netdev, u32 data)
|
|||
|
||||
static int ixgbe_set_tso(struct net_device *netdev, u32 data)
|
||||
{
|
||||
|
||||
if (data) {
|
||||
netdev->features |= NETIF_F_TSO;
|
||||
netdev->features |= NETIF_F_TSO6;
|
||||
} else {
|
||||
#ifdef CONFIG_NETDEVICES_MULTIQUEUE
|
||||
struct ixgbe_adapter *adapter = netdev_priv(netdev);
|
||||
int i;
|
||||
#endif
|
||||
netif_stop_queue(netdev);
|
||||
#ifdef CONFIG_NETDEVICES_MULTIQUEUE
|
||||
for (i = 0; i < adapter->num_tx_queues; i++)
|
||||
netif_stop_subqueue(netdev, i);
|
||||
#endif
|
||||
netdev->features &= ~NETIF_F_TSO;
|
||||
netdev->features &= ~NETIF_F_TSO6;
|
||||
#ifdef CONFIG_NETDEVICES_MULTIQUEUE
|
||||
for (i = 0; i < adapter->num_tx_queues; i++)
|
||||
netif_start_subqueue(netdev, i);
|
||||
#endif
|
||||
netif_start_queue(netdev);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
@ -873,13 +886,13 @@ static int ixgbe_get_coalesce(struct net_device *netdev,
|
|||
{
|
||||
struct ixgbe_adapter *adapter = netdev_priv(netdev);
|
||||
|
||||
if (adapter->rx_eitr == 0)
|
||||
ec->rx_coalesce_usecs = 0;
|
||||
if (adapter->rx_eitr < IXGBE_MIN_ITR_USECS)
|
||||
ec->rx_coalesce_usecs = adapter->rx_eitr;
|
||||
else
|
||||
ec->rx_coalesce_usecs = 1000000 / adapter->rx_eitr;
|
||||
|
||||
if (adapter->tx_eitr == 0)
|
||||
ec->tx_coalesce_usecs = 0;
|
||||
if (adapter->tx_eitr < IXGBE_MIN_ITR_USECS)
|
||||
ec->tx_coalesce_usecs = adapter->tx_eitr;
|
||||
else
|
||||
ec->tx_coalesce_usecs = 1000000 / adapter->tx_eitr;
|
||||
|
||||
|
@ -893,22 +906,26 @@ static int ixgbe_set_coalesce(struct net_device *netdev,
|
|||
struct ixgbe_adapter *adapter = netdev_priv(netdev);
|
||||
|
||||
if ((ec->rx_coalesce_usecs > IXGBE_MAX_ITR_USECS) ||
|
||||
((ec->rx_coalesce_usecs > 0) &&
|
||||
((ec->rx_coalesce_usecs != 0) &&
|
||||
(ec->rx_coalesce_usecs != 1) &&
|
||||
(ec->rx_coalesce_usecs != 3) &&
|
||||
(ec->rx_coalesce_usecs < IXGBE_MIN_ITR_USECS)))
|
||||
return -EINVAL;
|
||||
if ((ec->tx_coalesce_usecs > IXGBE_MAX_ITR_USECS) ||
|
||||
((ec->tx_coalesce_usecs > 0) &&
|
||||
((ec->tx_coalesce_usecs != 0) &&
|
||||
(ec->tx_coalesce_usecs != 1) &&
|
||||
(ec->tx_coalesce_usecs != 3) &&
|
||||
(ec->tx_coalesce_usecs < IXGBE_MIN_ITR_USECS)))
|
||||
return -EINVAL;
|
||||
|
||||
/* convert to rate of irq's per second */
|
||||
if (ec->rx_coalesce_usecs == 0)
|
||||
adapter->rx_eitr = 0;
|
||||
if (ec->rx_coalesce_usecs < IXGBE_MIN_ITR_USECS)
|
||||
adapter->rx_eitr = ec->rx_coalesce_usecs;
|
||||
else
|
||||
adapter->rx_eitr = (1000000 / ec->rx_coalesce_usecs);
|
||||
|
||||
if (ec->tx_coalesce_usecs == 0)
|
||||
adapter->tx_eitr = 0;
|
||||
if (ec->tx_coalesce_usecs < IXGBE_MIN_ITR_USECS)
|
||||
adapter->tx_eitr = ec->rx_coalesce_usecs;
|
||||
else
|
||||
adapter->tx_eitr = (1000000 / ec->tx_coalesce_usecs);
|
||||
|
||||
|
|
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
@ -50,6 +50,8 @@
|
|||
* Possible values '1' for enable , '0' for disable.
|
||||
* Default is '2' - which means disable in promisc mode
|
||||
* and enable in non-promiscuous mode.
|
||||
* multiq: This parameter used to enable/disable MULTIQUEUE support.
|
||||
* Possible values '1' for enable and '0' for disable. Default is '0'
|
||||
************************************************************************/
|
||||
|
||||
#include <linux/module.h>
|
||||
|
@ -84,7 +86,7 @@
|
|||
#include "s2io.h"
|
||||
#include "s2io-regs.h"
|
||||
|
||||
#define DRV_VERSION "2.0.26.15-2"
|
||||
#define DRV_VERSION "2.0.26.19"
|
||||
|
||||
/* S2io Driver name & version. */
|
||||
static char s2io_driver_name[] = "Neterion";
|
||||
|
@ -386,6 +388,26 @@ static void s2io_vlan_rx_register(struct net_device *dev,
|
|||
/* A flag indicating whether 'RX_PA_CFG_STRIP_VLAN_TAG' bit is set or not */
|
||||
static int vlan_strip_flag;
|
||||
|
||||
/* Unregister the vlan */
|
||||
static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
|
||||
{
|
||||
int i;
|
||||
struct s2io_nic *nic = dev->priv;
|
||||
unsigned long flags[MAX_TX_FIFOS];
|
||||
struct mac_info *mac_control = &nic->mac_control;
|
||||
struct config_param *config = &nic->config;
|
||||
|
||||
for (i = 0; i < config->tx_fifo_num; i++)
|
||||
spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]);
|
||||
|
||||
if (nic->vlgrp)
|
||||
vlan_group_set_device(nic->vlgrp, vid, NULL);
|
||||
|
||||
for (i = config->tx_fifo_num - 1; i >= 0; i--)
|
||||
spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock,
|
||||
flags[i]);
|
||||
}
|
||||
|
||||
/*
|
||||
* Constants to be programmed into the Xena's registers, to configure
|
||||
* the XAUI.
|
||||
|
@ -456,10 +478,9 @@ MODULE_VERSION(DRV_VERSION);
|
|||
|
||||
|
||||
/* Module Loadable parameters. */
|
||||
S2IO_PARM_INT(tx_fifo_num, 1);
|
||||
S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
|
||||
S2IO_PARM_INT(rx_ring_num, 1);
|
||||
|
||||
|
||||
S2IO_PARM_INT(multiq, 0);
|
||||
S2IO_PARM_INT(rx_ring_mode, 1);
|
||||
S2IO_PARM_INT(use_continuous_tx_intrs, 1);
|
||||
S2IO_PARM_INT(rmac_pause_time, 0x100);
|
||||
|
@ -469,6 +490,8 @@ S2IO_PARM_INT(shared_splits, 0);
|
|||
S2IO_PARM_INT(tmac_util_period, 5);
|
||||
S2IO_PARM_INT(rmac_util_period, 5);
|
||||
S2IO_PARM_INT(l3l4hdr_size, 128);
|
||||
/* 0 is no steering, 1 is Priority steering, 2 is Default steering */
|
||||
S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
|
||||
/* Frequency of Rx desc syncs expressed as power of 2 */
|
||||
S2IO_PARM_INT(rxsync_frequency, 3);
|
||||
/* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
|
||||
|
@ -533,6 +556,101 @@ static struct pci_driver s2io_driver = {
|
|||
/* A simplifier macro used both by init and free shared_mem Fns(). */
|
||||
#define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
|
||||
|
||||
/* netqueue manipulation helper functions */
|
||||
static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
|
||||
{
|
||||
int i;
|
||||
#ifdef CONFIG_NETDEVICES_MULTIQUEUE
|
||||
if (sp->config.multiq) {
|
||||
for (i = 0; i < sp->config.tx_fifo_num; i++)
|
||||
netif_stop_subqueue(sp->dev, i);
|
||||
} else
|
||||
#endif
|
||||
{
|
||||
for (i = 0; i < sp->config.tx_fifo_num; i++)
|
||||
sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
|
||||
netif_stop_queue(sp->dev);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
|
||||
{
|
||||
#ifdef CONFIG_NETDEVICES_MULTIQUEUE
|
||||
if (sp->config.multiq)
|
||||
netif_stop_subqueue(sp->dev, fifo_no);
|
||||
else
|
||||
#endif
|
||||
{
|
||||
sp->mac_control.fifos[fifo_no].queue_state =
|
||||
FIFO_QUEUE_STOP;
|
||||
netif_stop_queue(sp->dev);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
|
||||
{
|
||||
int i;
|
||||
#ifdef CONFIG_NETDEVICES_MULTIQUEUE
|
||||
if (sp->config.multiq) {
|
||||
for (i = 0; i < sp->config.tx_fifo_num; i++)
|
||||
netif_start_subqueue(sp->dev, i);
|
||||
} else
|
||||
#endif
|
||||
{
|
||||
for (i = 0; i < sp->config.tx_fifo_num; i++)
|
||||
sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
|
||||
netif_start_queue(sp->dev);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
|
||||
{
|
||||
#ifdef CONFIG_NETDEVICES_MULTIQUEUE
|
||||
if (sp->config.multiq)
|
||||
netif_start_subqueue(sp->dev, fifo_no);
|
||||
else
|
||||
#endif
|
||||
{
|
||||
sp->mac_control.fifos[fifo_no].queue_state =
|
||||
FIFO_QUEUE_START;
|
||||
netif_start_queue(sp->dev);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
|
||||
{
|
||||
int i;
|
||||
#ifdef CONFIG_NETDEVICES_MULTIQUEUE
|
||||
if (sp->config.multiq) {
|
||||
for (i = 0; i < sp->config.tx_fifo_num; i++)
|
||||
netif_wake_subqueue(sp->dev, i);
|
||||
} else
|
||||
#endif
|
||||
{
|
||||
for (i = 0; i < sp->config.tx_fifo_num; i++)
|
||||
sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
|
||||
netif_wake_queue(sp->dev);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void s2io_wake_tx_queue(
|
||||
struct fifo_info *fifo, int cnt, u8 multiq)
|
||||
{
|
||||
|
||||
#ifdef CONFIG_NETDEVICES_MULTIQUEUE
|
||||
if (multiq) {
|
||||
if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
|
||||
netif_wake_subqueue(fifo->dev, fifo->fifo_no);
|
||||
} else
|
||||
#endif
|
||||
if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
|
||||
if (netif_queue_stopped(fifo->dev)) {
|
||||
fifo->queue_state = FIFO_QUEUE_START;
|
||||
netif_wake_queue(fifo->dev);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* init_shared_mem - Allocation and Initialization of Memory
|
||||
* @nic: Device private variable.
|
||||
|
@ -614,6 +732,7 @@ static int init_shared_mem(struct s2io_nic *nic)
|
|||
mac_control->fifos[i].fifo_no = i;
|
||||
mac_control->fifos[i].nic = nic;
|
||||
mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
|
||||
mac_control->fifos[i].dev = dev;
|
||||
|
||||
for (j = 0; j < page_num; j++) {
|
||||
int k = 0;
|
||||
|
@ -2948,7 +3067,7 @@ static void rx_intr_handler(struct ring_info *ring_data)
|
|||
struct lro *lro = &nic->lro0_n[i];
|
||||
if (lro->in_use) {
|
||||
update_L3L4_header(nic, lro);
|
||||
queue_rx_frame(lro->parent);
|
||||
queue_rx_frame(lro->parent, lro->vlan_tag);
|
||||
clear_lro_session(lro);
|
||||
}
|
||||
}
|
||||
|
@ -2972,10 +3091,10 @@ static void rx_intr_handler(struct ring_info *ring_data)
|
|||
static void tx_intr_handler(struct fifo_info *fifo_data)
|
||||
{
|
||||
struct s2io_nic *nic = fifo_data->nic;
|
||||
struct net_device *dev = (struct net_device *) nic->dev;
|
||||
struct tx_curr_get_info get_info, put_info;
|
||||
struct sk_buff *skb;
|
||||
struct sk_buff *skb = NULL;
|
||||
struct TxD *txdlp;
|
||||
int pkt_cnt = 0;
|
||||
unsigned long flags = 0;
|
||||
u8 err_mask;
|
||||
|
||||
|
@ -3036,6 +3155,7 @@ static void tx_intr_handler(struct fifo_info *fifo_data)
|
|||
DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
|
||||
return;
|
||||
}
|
||||
pkt_cnt++;
|
||||
|
||||
/* Updating the statistics block */
|
||||
nic->stats.tx_bytes += skb->len;
|
||||
|
@ -3051,8 +3171,7 @@ static void tx_intr_handler(struct fifo_info *fifo_data)
|
|||
get_info.offset;
|
||||
}
|
||||
|
||||
if (netif_queue_stopped(dev))
|
||||
netif_wake_queue(dev);
|
||||
s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
|
||||
|
||||
spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
|
||||
}
|
||||
|
@ -3933,8 +4052,7 @@ static int s2io_open(struct net_device *dev)
|
|||
err = -ENODEV;
|
||||
goto hw_init_failed;
|
||||
}
|
||||
|
||||
netif_start_queue(dev);
|
||||
s2io_start_all_tx_queue(sp);
|
||||
return 0;
|
||||
|
||||
hw_init_failed:
|
||||
|
@ -3979,8 +4097,7 @@ static int s2io_close(struct net_device *dev)
|
|||
if (!is_s2io_card_up(sp))
|
||||
return 0;
|
||||
|
||||
netif_stop_queue(dev);
|
||||
|
||||
s2io_stop_all_tx_queue(sp);
|
||||
/* delete all populated mac entries */
|
||||
for (offset = 1; offset < config->max_mc_addr; offset++) {
|
||||
tmp64 = do_s2io_read_unicast_mc(sp, offset);
|
||||
|
@ -4016,11 +4133,12 @@ static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
|
|||
struct TxFIFO_element __iomem *tx_fifo;
|
||||
unsigned long flags = 0;
|
||||
u16 vlan_tag = 0;
|
||||
int vlan_priority = 0;
|
||||
struct fifo_info *fifo = NULL;
|
||||
struct mac_info *mac_control;
|
||||
struct config_param *config;
|
||||
int do_spin_lock = 1;
|
||||
int offload_type;
|
||||
int enable_per_list_interrupt = 0;
|
||||
struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
|
||||
|
||||
mac_control = &sp->mac_control;
|
||||
|
@ -4042,15 +4160,67 @@ static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
|
|||
}
|
||||
|
||||
queue = 0;
|
||||
/* Get Fifo number to Transmit based on vlan priority */
|
||||
if (sp->vlgrp && vlan_tx_tag_present(skb)) {
|
||||
if (sp->vlgrp && vlan_tx_tag_present(skb))
|
||||
vlan_tag = vlan_tx_tag_get(skb);
|
||||
vlan_priority = vlan_tag >> 13;
|
||||
queue = config->fifo_mapping[vlan_priority];
|
||||
if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
|
||||
if (skb->protocol == htons(ETH_P_IP)) {
|
||||
struct iphdr *ip;
|
||||
struct tcphdr *th;
|
||||
ip = ip_hdr(skb);
|
||||
|
||||
if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
|
||||
th = (struct tcphdr *)(((unsigned char *)ip) +
|
||||
ip->ihl*4);
|
||||
|
||||
if (ip->protocol == IPPROTO_TCP) {
|
||||
queue_len = sp->total_tcp_fifos;
|
||||
queue = (ntohs(th->source) +
|
||||
ntohs(th->dest)) &
|
||||
sp->fifo_selector[queue_len - 1];
|
||||
if (queue >= queue_len)
|
||||
queue = queue_len - 1;
|
||||
} else if (ip->protocol == IPPROTO_UDP) {
|
||||
queue_len = sp->total_udp_fifos;
|
||||
queue = (ntohs(th->source) +
|
||||
ntohs(th->dest)) &
|
||||
sp->fifo_selector[queue_len - 1];
|
||||
if (queue >= queue_len)
|
||||
queue = queue_len - 1;
|
||||
queue += sp->udp_fifo_idx;
|
||||
if (skb->len > 1024)
|
||||
enable_per_list_interrupt = 1;
|
||||
do_spin_lock = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
} else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
|
||||
/* get fifo number based on skb->priority value */
|
||||
queue = config->fifo_mapping
|
||||
[skb->priority & (MAX_TX_FIFOS - 1)];
|
||||
fifo = &mac_control->fifos[queue];
|
||||
|
||||
if (do_spin_lock)
|
||||
spin_lock_irqsave(&fifo->tx_lock, flags);
|
||||
else {
|
||||
if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
|
||||
return NETDEV_TX_LOCKED;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_NETDEVICES_MULTIQUEUE
|
||||
if (sp->config.multiq) {
|
||||
if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
|
||||
spin_unlock_irqrestore(&fifo->tx_lock, flags);
|
||||
return NETDEV_TX_BUSY;
|
||||
}
|
||||
} else
|
||||
#endif
|
||||
if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
|
||||
if (netif_queue_stopped(dev)) {
|
||||
spin_unlock_irqrestore(&fifo->tx_lock, flags);
|
||||
return NETDEV_TX_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
fifo = &mac_control->fifos[queue];
|
||||
spin_lock_irqsave(&fifo->tx_lock, flags);
|
||||
put_off = (u16) fifo->tx_curr_put_info.offset;
|
||||
get_off = (u16) fifo->tx_curr_get_info.offset;
|
||||
txdp = (struct TxD *) fifo->list_info[put_off].list_virt_addr;
|
||||
|
@ -4060,7 +4230,7 @@ static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
|
|||
if (txdp->Host_Control ||
|
||||
((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
|
||||
DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
|
||||
netif_stop_queue(dev);
|
||||
s2io_stop_tx_queue(sp, fifo->fifo_no);
|
||||
dev_kfree_skb(skb);
|
||||
spin_unlock_irqrestore(&fifo->tx_lock, flags);
|
||||
return 0;
|
||||
|
@ -4079,8 +4249,10 @@ static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
|
|||
txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
|
||||
txdp->Control_1 |= TXD_LIST_OWN_XENA;
|
||||
txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
|
||||
|
||||
if (sp->vlgrp && vlan_tx_tag_present(skb)) {
|
||||
if (enable_per_list_interrupt)
|
||||
if (put_off & (queue_len >> 5))
|
||||
txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
|
||||
if (vlan_tag) {
|
||||
txdp->Control_2 |= TXD_VLAN_ENABLE;
|
||||
txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
|
||||
}
|
||||
|
@ -4166,7 +4338,7 @@ static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
|
|||
DBG_PRINT(TX_DBG,
|
||||
"No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
|
||||
put_off, get_off);
|
||||
netif_stop_queue(dev);
|
||||
s2io_stop_tx_queue(sp, fifo->fifo_no);
|
||||
}
|
||||
mac_control->stats_info->sw_stat.mem_allocated += skb->truesize;
|
||||
dev->trans_start = jiffies;
|
||||
|
@ -4175,7 +4347,7 @@ static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
|
|||
return 0;
|
||||
pci_map_failed:
|
||||
stats->pci_map_fail_cnt++;
|
||||
netif_stop_queue(dev);
|
||||
s2io_stop_tx_queue(sp, fifo->fifo_no);
|
||||
stats->mem_freed += skb->truesize;
|
||||
dev_kfree_skb(skb);
|
||||
spin_unlock_irqrestore(&fifo->tx_lock, flags);
|
||||
|
@ -4587,7 +4759,7 @@ static void s2io_handle_errors(void * dev_id)
|
|||
return;
|
||||
|
||||
reset:
|
||||
netif_stop_queue(dev);
|
||||
s2io_stop_all_tx_queue(sp);
|
||||
schedule_work(&sp->rst_timer_task);
|
||||
sw_stat->soft_reset_cnt++;
|
||||
return;
|
||||
|
@ -6574,16 +6746,15 @@ static int s2io_change_mtu(struct net_device *dev, int new_mtu)
|
|||
|
||||
dev->mtu = new_mtu;
|
||||
if (netif_running(dev)) {
|
||||
s2io_stop_all_tx_queue(sp);
|
||||
s2io_card_down(sp);
|
||||
netif_stop_queue(dev);
|
||||
ret = s2io_card_up(sp);
|
||||
if (ret) {
|
||||
DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
|
||||
__FUNCTION__);
|
||||
return ret;
|
||||
}
|
||||
if (netif_queue_stopped(dev))
|
||||
netif_wake_queue(dev);
|
||||
s2io_wake_all_tx_queue(sp);
|
||||
} else { /* Device is down */
|
||||
struct XENA_dev_config __iomem *bar0 = sp->bar0;
|
||||
u64 val64 = new_mtu;
|
||||
|
@ -6691,7 +6862,7 @@ static void s2io_set_link(struct work_struct *work)
|
|||
} else {
|
||||
DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
|
||||
DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
|
||||
netif_stop_queue(dev);
|
||||
s2io_stop_all_tx_queue(nic);
|
||||
}
|
||||
}
|
||||
val64 = readq(&bar0->adapter_control);
|
||||
|
@ -7181,7 +7352,7 @@ static void s2io_restart_nic(struct work_struct *work)
|
|||
DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
|
||||
dev->name);
|
||||
}
|
||||
netif_wake_queue(dev);
|
||||
s2io_wake_all_tx_queue(sp);
|
||||
DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
|
||||
dev->name);
|
||||
out_unlock:
|
||||
|
@ -7371,7 +7542,8 @@ static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
|
|||
{
|
||||
lro_append_pkt(sp, lro,
|
||||
skb, tcp_len);
|
||||
queue_rx_frame(lro->parent);
|
||||
queue_rx_frame(lro->parent,
|
||||
lro->vlan_tag);
|
||||
clear_lro_session(lro);
|
||||
sp->mac_control.stats_info->
|
||||
sw_stat.flush_max_pkts++;
|
||||
|
@ -7382,7 +7554,8 @@ static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
|
|||
lro->frags_len;
|
||||
sp->mac_control.stats_info->
|
||||
sw_stat.sending_both++;
|
||||
queue_rx_frame(lro->parent);
|
||||
queue_rx_frame(lro->parent,
|
||||
lro->vlan_tag);
|
||||
clear_lro_session(lro);
|
||||
goto send_up;
|
||||
case 0: /* sessions exceeded */
|
||||
|
@ -7408,31 +7581,12 @@ static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
|
|||
*/
|
||||
skb->ip_summed = CHECKSUM_NONE;
|
||||
}
|
||||
} else {
|
||||
} else
|
||||
skb->ip_summed = CHECKSUM_NONE;
|
||||
}
|
||||
|
||||
sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
|
||||
if (!sp->lro) {
|
||||
skb->protocol = eth_type_trans(skb, dev);
|
||||
if ((sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2) &&
|
||||
vlan_strip_flag)) {
|
||||
/* Queueing the vlan frame to the upper layer */
|
||||
if (napi)
|
||||
vlan_hwaccel_receive_skb(skb, sp->vlgrp,
|
||||
RXD_GET_VLAN_TAG(rxdp->Control_2));
|
||||
else
|
||||
vlan_hwaccel_rx(skb, sp->vlgrp,
|
||||
RXD_GET_VLAN_TAG(rxdp->Control_2));
|
||||
} else {
|
||||
if (napi)
|
||||
netif_receive_skb(skb);
|
||||
else
|
||||
netif_rx(skb);
|
||||
}
|
||||
} else {
|
||||
send_up:
|
||||
queue_rx_frame(skb);
|
||||
}
|
||||
queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
|
||||
dev->last_rx = jiffies;
|
||||
aggregate:
|
||||
atomic_dec(&sp->rx_bufs_left[ring_no]);
|
||||
|
@ -7460,6 +7614,7 @@ static void s2io_link(struct s2io_nic * sp, int link)
|
|||
init_tti(sp, link);
|
||||
if (link == LINK_DOWN) {
|
||||
DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
|
||||
s2io_stop_all_tx_queue(sp);
|
||||
netif_carrier_off(dev);
|
||||
if(sp->mac_control.stats_info->sw_stat.link_up_cnt)
|
||||
sp->mac_control.stats_info->sw_stat.link_up_time =
|
||||
|
@ -7472,6 +7627,7 @@ static void s2io_link(struct s2io_nic * sp, int link)
|
|||
jiffies - sp->start_time;
|
||||
sp->mac_control.stats_info->sw_stat.link_up_cnt++;
|
||||
netif_carrier_on(dev);
|
||||
s2io_wake_all_tx_queue(sp);
|
||||
}
|
||||
}
|
||||
sp->last_link_state = link;
|
||||
|
@ -7508,20 +7664,48 @@ static void s2io_init_pci(struct s2io_nic * sp)
|
|||
pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
|
||||
}
|
||||
|
||||
static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type)
|
||||
static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
|
||||
u8 *dev_multiq)
|
||||
{
|
||||
if ((tx_fifo_num > MAX_TX_FIFOS) ||
|
||||
(tx_fifo_num < FIFO_DEFAULT_NUM)) {
|
||||
(tx_fifo_num < 1)) {
|
||||
DBG_PRINT(ERR_DBG, "s2io: Requested number of tx fifos "
|
||||
"(%d) not supported\n", tx_fifo_num);
|
||||
tx_fifo_num =
|
||||
((tx_fifo_num > MAX_TX_FIFOS)? MAX_TX_FIFOS :
|
||||
((tx_fifo_num < FIFO_DEFAULT_NUM) ? FIFO_DEFAULT_NUM :
|
||||
tx_fifo_num));
|
||||
|
||||
if (tx_fifo_num < 1)
|
||||
tx_fifo_num = 1;
|
||||
else
|
||||
tx_fifo_num = MAX_TX_FIFOS;
|
||||
|
||||
DBG_PRINT(ERR_DBG, "s2io: Default to %d ", tx_fifo_num);
|
||||
DBG_PRINT(ERR_DBG, "tx fifos\n");
|
||||
}
|
||||
|
||||
#ifndef CONFIG_NETDEVICES_MULTIQUEUE
|
||||
if (multiq) {
|
||||
DBG_PRINT(ERR_DBG, "s2io: Multiqueue support not enabled\n");
|
||||
multiq = 0;
|
||||
}
|
||||
#endif
|
||||
if (multiq)
|
||||
*dev_multiq = multiq;
|
||||
|
||||
if (tx_steering_type && (1 == tx_fifo_num)) {
|
||||
if (tx_steering_type != TX_DEFAULT_STEERING)
|
||||
DBG_PRINT(ERR_DBG,
|
||||
"s2io: Tx steering is not supported with "
|
||||
"one fifo. Disabling Tx steering.\n");
|
||||
tx_steering_type = NO_STEERING;
|
||||
}
|
||||
|
||||
if ((tx_steering_type < NO_STEERING) ||
|
||||
(tx_steering_type > TX_DEFAULT_STEERING)) {
|
||||
DBG_PRINT(ERR_DBG, "s2io: Requested transmit steering not "
|
||||
"supported\n");
|
||||
DBG_PRINT(ERR_DBG, "s2io: Disabling transmit steering\n");
|
||||
tx_steering_type = NO_STEERING;
|
||||
}
|
||||
|
||||
if ( rx_ring_num > 8) {
|
||||
DBG_PRINT(ERR_DBG, "s2io: Requested number of Rx rings not "
|
||||
"supported\n");
|
||||
|
@ -7613,9 +7797,11 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
|
|||
struct config_param *config;
|
||||
int mode;
|
||||
u8 dev_intr_type = intr_type;
|
||||
u8 dev_multiq = 0;
|
||||
DECLARE_MAC_BUF(mac);
|
||||
|
||||
if ((ret = s2io_verify_parm(pdev, &dev_intr_type)))
|
||||
ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if ((ret = pci_enable_device(pdev))) {
|
||||
|
@ -7646,7 +7832,11 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
|
|||
pci_disable_device(pdev);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_NETDEVICES_MULTIQUEUE
|
||||
if (dev_multiq)
|
||||
dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
|
||||
else
|
||||
#endif
|
||||
dev = alloc_etherdev(sizeof(struct s2io_nic));
|
||||
if (dev == NULL) {
|
||||
DBG_PRINT(ERR_DBG, "Device allocation failed\n");
|
||||
|
@ -7695,17 +7885,45 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
|
|||
config = &sp->config;
|
||||
|
||||
config->napi = napi;
|
||||
config->tx_steering_type = tx_steering_type;
|
||||
|
||||
/* Tx side parameters. */
|
||||
if (config->tx_steering_type == TX_PRIORITY_STEERING)
|
||||
config->tx_fifo_num = MAX_TX_FIFOS;
|
||||
else
|
||||
config->tx_fifo_num = tx_fifo_num;
|
||||
for (i = 0; i < MAX_TX_FIFOS; i++) {
|
||||
|
||||
/* Initialize the fifos used for tx steering */
|
||||
if (config->tx_fifo_num < 5) {
|
||||
if (config->tx_fifo_num == 1)
|
||||
sp->total_tcp_fifos = 1;
|
||||
else
|
||||
sp->total_tcp_fifos = config->tx_fifo_num - 1;
|
||||
sp->udp_fifo_idx = config->tx_fifo_num - 1;
|
||||
sp->total_udp_fifos = 1;
|
||||
sp->other_fifo_idx = sp->total_tcp_fifos - 1;
|
||||
} else {
|
||||
sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
|
||||
FIFO_OTHER_MAX_NUM);
|
||||
sp->udp_fifo_idx = sp->total_tcp_fifos;
|
||||
sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
|
||||
sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
|
||||
}
|
||||
|
||||
config->multiq = dev_multiq;
|
||||
for (i = 0; i < config->tx_fifo_num; i++) {
|
||||
config->tx_cfg[i].fifo_len = tx_fifo_len[i];
|
||||
config->tx_cfg[i].fifo_priority = i;
|
||||
}
|
||||
|
||||
/* mapping the QoS priority to the configured fifos */
|
||||
for (i = 0; i < MAX_TX_FIFOS; i++)
|
||||
config->fifo_mapping[i] = fifo_map[config->tx_fifo_num][i];
|
||||
config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
|
||||
|
||||
/* map the hashing selector table to the configured fifos */
|
||||
for (i = 0; i < config->tx_fifo_num; i++)
|
||||
sp->fifo_selector[i] = fifo_selector[i];
|
||||
|
||||
|
||||
config->tx_intr_type = TXD_INT_TYPE_UTILZ;
|
||||
for (i = 0; i < config->tx_fifo_num; i++) {
|
||||
|
@ -7790,6 +8008,7 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
|
|||
SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
|
||||
dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
|
||||
dev->vlan_rx_register = s2io_vlan_rx_register;
|
||||
dev->vlan_rx_kill_vid = (void *)s2io_vlan_rx_kill_vid;
|
||||
|
||||
/*
|
||||
* will use eth_mac_addr() for dev->set_mac_address
|
||||
|
@ -7810,7 +8029,10 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
|
|||
dev->features |= NETIF_F_UFO;
|
||||
dev->features |= NETIF_F_HW_CSUM;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_NETDEVICES_MULTIQUEUE
|
||||
if (config->multiq)
|
||||
dev->features |= NETIF_F_MULTI_QUEUE;
|
||||
#endif
|
||||
dev->tx_timeout = &s2io_tx_watchdog;
|
||||
dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
|
||||
INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
|
||||
|
@ -7959,6 +8181,10 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
|
|||
|
||||
if (napi)
|
||||
DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
|
||||
|
||||
DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
|
||||
sp->config.tx_fifo_num);
|
||||
|
||||
switch(sp->config.intr_type) {
|
||||
case INTA:
|
||||
DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
|
||||
|
@ -7967,6 +8193,29 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
|
|||
DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
|
||||
break;
|
||||
}
|
||||
if (sp->config.multiq) {
|
||||
for (i = 0; i < sp->config.tx_fifo_num; i++)
|
||||
mac_control->fifos[i].multiq = config->multiq;
|
||||
DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
|
||||
dev->name);
|
||||
} else
|
||||
DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
|
||||
dev->name);
|
||||
|
||||
switch (sp->config.tx_steering_type) {
|
||||
case NO_STEERING:
|
||||
DBG_PRINT(ERR_DBG, "%s: No steering enabled for"
|
||||
" transmit\n", dev->name);
|
||||
break;
|
||||
case TX_PRIORITY_STEERING:
|
||||
DBG_PRINT(ERR_DBG, "%s: Priority steering enabled for"
|
||||
" transmit\n", dev->name);
|
||||
break;
|
||||
case TX_DEFAULT_STEERING:
|
||||
DBG_PRINT(ERR_DBG, "%s: Default steering enabled for"
|
||||
" transmit\n", dev->name);
|
||||
}
|
||||
|
||||
if (sp->lro)
|
||||
DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
|
||||
dev->name);
|
||||
|
@ -8061,7 +8310,8 @@ module_init(s2io_starter);
|
|||
module_exit(s2io_closer);
|
||||
|
||||
static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
|
||||
struct tcphdr **tcp, struct RxD_t *rxdp)
|
||||
struct tcphdr **tcp, struct RxD_t *rxdp,
|
||||
struct s2io_nic *sp)
|
||||
{
|
||||
int ip_off;
|
||||
u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
|
||||
|
@ -8072,18 +8322,19 @@ static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
|
|||
return -1;
|
||||
}
|
||||
|
||||
/* TODO:
|
||||
* By default the VLAN field in the MAC is stripped by the card, if this
|
||||
* feature is turned off in rx_pa_cfg register, then the ip_off field
|
||||
* has to be shifted by a further 2 bytes
|
||||
*/
|
||||
switch (l2_type) {
|
||||
case 0: /* DIX type */
|
||||
case 4: /* DIX type with VLAN */
|
||||
/* Checking for DIX type or DIX type with VLAN */
|
||||
if ((l2_type == 0)
|
||||
|| (l2_type == 4)) {
|
||||
ip_off = HEADER_ETHERNET_II_802_3_SIZE;
|
||||
break;
|
||||
/*
|
||||
* If vlan stripping is disabled and the frame is VLAN tagged,
|
||||
* shift the offset by the VLAN header size bytes.
|
||||
*/
|
||||
if ((!vlan_strip_flag) &&
|
||||
(rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
|
||||
ip_off += HEADER_VLAN_SIZE;
|
||||
} else {
|
||||
/* LLC, SNAP etc are considered non-mergeable */
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
@ -8111,7 +8362,7 @@ static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
|
|||
}
|
||||
|
||||
static void initiate_new_session(struct lro *lro, u8 *l2h,
|
||||
struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len)
|
||||
struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len, u16 vlan_tag)
|
||||
{
|
||||
DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
|
||||
lro->l2h = l2h;
|
||||
|
@ -8122,6 +8373,7 @@ static void initiate_new_session(struct lro *lro, u8 *l2h,
|
|||
lro->sg_num = 1;
|
||||
lro->total_len = ntohs(ip->tot_len);
|
||||
lro->frags_len = 0;
|
||||
lro->vlan_tag = vlan_tag;
|
||||
/*
|
||||
* check if we saw TCP timestamp. Other consistency checks have
|
||||
* already been done.
|
||||
|
@ -8253,15 +8505,16 @@ s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
|
|||
struct iphdr *ip;
|
||||
struct tcphdr *tcph;
|
||||
int ret = 0, i;
|
||||
u16 vlan_tag = 0;
|
||||
|
||||
if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
|
||||
rxdp))) {
|
||||
rxdp, sp))) {
|
||||
DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
|
||||
ip->saddr, ip->daddr);
|
||||
} else {
|
||||
} else
|
||||
return ret;
|
||||
}
|
||||
|
||||
vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
|
||||
tcph = (struct tcphdr *)*tcp;
|
||||
*tcp_len = get_l4_pyld_length(ip, tcph);
|
||||
for (i=0; i<MAX_LRO_SESSIONS; i++) {
|
||||
|
@ -8321,7 +8574,8 @@ s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
|
|||
|
||||
switch (ret) {
|
||||
case 3:
|
||||
initiate_new_session(*lro, buffer, ip, tcph, *tcp_len);
|
||||
initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
|
||||
vlan_tag);
|
||||
break;
|
||||
case 2:
|
||||
update_L3L4_header(sp, *lro);
|
||||
|
@ -8349,16 +8603,26 @@ static void clear_lro_session(struct lro *lro)
|
|||
memset(lro, 0, lro_struct_size);
|
||||
}
|
||||
|
||||
static void queue_rx_frame(struct sk_buff *skb)
|
||||
static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
|
||||
{
|
||||
struct net_device *dev = skb->dev;
|
||||
struct s2io_nic *sp = dev->priv;
|
||||
|
||||
skb->protocol = eth_type_trans(skb, dev);
|
||||
if (napi)
|
||||
if (sp->vlgrp && vlan_tag
|
||||
&& (vlan_strip_flag)) {
|
||||
/* Queueing the vlan frame to the upper layer */
|
||||
if (sp->config.napi)
|
||||
vlan_hwaccel_receive_skb(skb, sp->vlgrp, vlan_tag);
|
||||
else
|
||||
vlan_hwaccel_rx(skb, sp->vlgrp, vlan_tag);
|
||||
} else {
|
||||
if (sp->config.napi)
|
||||
netif_receive_skb(skb);
|
||||
else
|
||||
netif_rx(skb);
|
||||
}
|
||||
}
|
||||
|
||||
static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
|
||||
struct sk_buff *skb,
|
||||
|
|
|
@ -360,7 +360,10 @@ struct stat_block {
|
|||
#define MAX_TX_FIFOS 8
|
||||
#define MAX_RX_RINGS 8
|
||||
|
||||
#define FIFO_DEFAULT_NUM 1
|
||||
#define FIFO_DEFAULT_NUM 5
|
||||
#define FIFO_UDP_MAX_NUM 2 /* 0 - even, 1 -odd ports */
|
||||
#define FIFO_OTHER_MAX_NUM 1
|
||||
|
||||
|
||||
#define MAX_RX_DESC_1 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 127 )
|
||||
#define MAX_RX_DESC_2 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 )
|
||||
|
@ -379,6 +382,8 @@ static int fifo_map[][MAX_TX_FIFOS] = {
|
|||
{0, 1, 2, 3, 4, 5, 6, 7},
|
||||
};
|
||||
|
||||
static u16 fifo_selector[MAX_TX_FIFOS] = {0, 1, 3, 3, 7, 7, 7, 7};
|
||||
|
||||
/* Maintains Per FIFO related information. */
|
||||
struct tx_fifo_config {
|
||||
#define MAX_AVAILABLE_TXDS 8192
|
||||
|
@ -431,6 +436,12 @@ struct config_param {
|
|||
/* Tx Side */
|
||||
u32 tx_fifo_num; /*Number of Tx FIFOs */
|
||||
|
||||
/* 0-No steering, 1-Priority steering, 2-Default fifo map */
|
||||
#define NO_STEERING 0
|
||||
#define TX_PRIORITY_STEERING 0x1
|
||||
#define TX_DEFAULT_STEERING 0x2
|
||||
u8 tx_steering_type;
|
||||
|
||||
u8 fifo_mapping[MAX_TX_FIFOS];
|
||||
struct tx_fifo_config tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */
|
||||
u32 max_txds; /*Max no. of Tx buffer descriptor per TxDL */
|
||||
|
@ -464,6 +475,7 @@ struct config_param {
|
|||
int max_mc_addr; /* xena=64 herc=256 */
|
||||
int max_mac_addr; /* xena=16 herc=64 */
|
||||
int mc_start_offset; /* xena=16 herc=64 */
|
||||
u8 multiq;
|
||||
};
|
||||
|
||||
/* Structure representing MAC Addrs */
|
||||
|
@ -534,6 +546,7 @@ struct RxD_t {
|
|||
#define RXD_OWN_XENA s2BIT(7)
|
||||
#define RXD_T_CODE (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15))
|
||||
#define RXD_FRAME_PROTO vBIT(0xFFFF,24,8)
|
||||
#define RXD_FRAME_VLAN_TAG s2BIT(24)
|
||||
#define RXD_FRAME_PROTO_IPV4 s2BIT(27)
|
||||
#define RXD_FRAME_PROTO_IPV6 s2BIT(28)
|
||||
#define RXD_FRAME_IP_FRAG s2BIT(29)
|
||||
|
@ -720,6 +733,15 @@ struct fifo_info {
|
|||
* the buffers
|
||||
*/
|
||||
struct tx_curr_get_info tx_curr_get_info;
|
||||
#define FIFO_QUEUE_START 0
|
||||
#define FIFO_QUEUE_STOP 1
|
||||
int queue_state;
|
||||
|
||||
/* copy of sp->dev pointer */
|
||||
struct net_device *dev;
|
||||
|
||||
/* copy of multiq status */
|
||||
u8 multiq;
|
||||
|
||||
/* Per fifo lock */
|
||||
spinlock_t tx_lock;
|
||||
|
@ -808,10 +830,11 @@ struct lro {
|
|||
int sg_num;
|
||||
int in_use;
|
||||
__be16 window;
|
||||
u16 vlan_tag;
|
||||
u32 cur_tsval;
|
||||
__be32 cur_tsecr;
|
||||
u8 saw_ts;
|
||||
};
|
||||
} ____cacheline_aligned;
|
||||
|
||||
/* These flags represent the devices temporary state */
|
||||
enum s2io_device_state_t
|
||||
|
@ -885,6 +908,27 @@ struct s2io_nic {
|
|||
*/
|
||||
int rx_csum;
|
||||
|
||||
/* Below variables are used for fifo selection to transmit a packet */
|
||||
u16 fifo_selector[MAX_TX_FIFOS];
|
||||
|
||||
/* Total fifos for tcp packets */
|
||||
u8 total_tcp_fifos;
|
||||
|
||||
/*
|
||||
* Beginning index of udp for udp packets
|
||||
* Value will be equal to
|
||||
* (tx_fifo_num - FIFO_UDP_MAX_NUM - FIFO_OTHER_MAX_NUM)
|
||||
*/
|
||||
u8 udp_fifo_idx;
|
||||
|
||||
u8 total_udp_fifos;
|
||||
|
||||
/*
|
||||
* Beginning index of fifo for all other packets
|
||||
* Value will be equal to (tx_fifo_num - FIFO_OTHER_MAX_NUM)
|
||||
*/
|
||||
u8 other_fifo_idx;
|
||||
|
||||
/* after blink, the adapter must be restored with original
|
||||
* values.
|
||||
*/
|
||||
|
@ -1087,7 +1131,7 @@ static int
|
|||
s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
|
||||
struct RxD_t *rxdp, struct s2io_nic *sp);
|
||||
static void clear_lro_session(struct lro *lro);
|
||||
static void queue_rx_frame(struct sk_buff *skb);
|
||||
static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag);
|
||||
static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro);
|
||||
static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
|
||||
struct sk_buff *skb, u32 tcp_len);
|
||||
|
|
|
@ -1,87 +0,0 @@
|
|||
#
|
||||
# Makefile for the SysKonnect SK-98xx device driver.
|
||||
#
|
||||
|
||||
|
||||
#
|
||||
# Standalone driver params
|
||||
# SKPARAM += -DSK_KERNEL_24
|
||||
# SKPARAM += -DSK_KERNEL_24_26
|
||||
# SKPARAM += -DSK_KERNEL_26
|
||||
# SKPARAM += -DSK_KERNEL_22_24
|
||||
|
||||
obj-$(CONFIG_SK98LIN) += sk98lin.o
|
||||
sk98lin-objs := \
|
||||
skge.o \
|
||||
skethtool.o \
|
||||
skdim.o \
|
||||
skaddr.o \
|
||||
skgehwt.o \
|
||||
skgeinit.o \
|
||||
skgepnmi.o \
|
||||
skgesirq.o \
|
||||
ski2c.o \
|
||||
sklm80.o \
|
||||
skqueue.o \
|
||||
skrlmt.o \
|
||||
sktimer.o \
|
||||
skvpd.o \
|
||||
skxmac2.o
|
||||
|
||||
# DBGDEF = \
|
||||
# -DDEBUG
|
||||
|
||||
ifdef DEBUG
|
||||
DBGDEF += \
|
||||
-DSK_DEBUG_CHKMOD=0x00000000L \
|
||||
-DSK_DEBUG_CHKCAT=0x00000000L
|
||||
endif
|
||||
|
||||
|
||||
# **** possible debug modules for SK_DEBUG_CHKMOD *****************
|
||||
# SK_DBGMOD_MERR 0x00000001L /* general module error indication */
|
||||
# SK_DBGMOD_HWM 0x00000002L /* Hardware init module */
|
||||
# SK_DBGMOD_RLMT 0x00000004L /* RLMT module */
|
||||
# SK_DBGMOD_VPD 0x00000008L /* VPD module */
|
||||
# SK_DBGMOD_I2C 0x00000010L /* I2C module */
|
||||
# SK_DBGMOD_PNMI 0x00000020L /* PNMI module */
|
||||
# SK_DBGMOD_CSUM 0x00000040L /* CSUM module */
|
||||
# SK_DBGMOD_ADDR 0x00000080L /* ADDR module */
|
||||
# SK_DBGMOD_DRV 0x00010000L /* DRV module */
|
||||
|
||||
# **** possible debug categories for SK_DEBUG_CHKCAT **************
|
||||
# *** common modules ***
|
||||
# SK_DBGCAT_INIT 0x00000001L module/driver initialization
|
||||
# SK_DBGCAT_CTRL 0x00000002L controlling: add/rmv MCA/MAC and other controls (IOCTL)
|
||||
# SK_DBGCAT_ERR 0x00000004L error handling paths
|
||||
# SK_DBGCAT_TX 0x00000008L transmit path
|
||||
# SK_DBGCAT_RX 0x00000010L receive path
|
||||
# SK_DBGCAT_IRQ 0x00000020L general IRQ handling
|
||||
# SK_DBGCAT_QUEUE 0x00000040L any queue management
|
||||
# SK_DBGCAT_DUMP 0x00000080L large data output e.g. hex dump
|
||||
# SK_DBGCAT_FATAL 0x00000100L large data output e.g. hex dump
|
||||
|
||||
# *** driver (file skge.c) ***
|
||||
# SK_DBGCAT_DRV_ENTRY 0x00010000 entry points
|
||||
# SK_DBGCAT_DRV_??? 0x00020000 not used
|
||||
# SK_DBGCAT_DRV_MCA 0x00040000 multicast
|
||||
# SK_DBGCAT_DRV_TX_PROGRESS 0x00080000 tx path
|
||||
# SK_DBGCAT_DRV_RX_PROGRESS 0x00100000 rx path
|
||||
# SK_DBGCAT_DRV_PROGRESS 0x00200000 general runtime
|
||||
# SK_DBGCAT_DRV_??? 0x00400000 not used
|
||||
# SK_DBGCAT_DRV_PROM 0x00800000 promiscuous mode
|
||||
# SK_DBGCAT_DRV_TX_FRAME 0x01000000 display tx frames
|
||||
# SK_DBGCAT_DRV_ERROR 0x02000000 error conditions
|
||||
# SK_DBGCAT_DRV_INT_SRC 0x04000000 interrupts sources
|
||||
# SK_DBGCAT_DRV_EVENT 0x08000000 driver events
|
||||
|
||||
EXTRA_CFLAGS += -Idrivers/net/sk98lin -DSK_DIAG_SUPPORT -DGENESIS -DYUKON $(DBGDEF) $(SKPARAM)
|
||||
|
||||
clean:
|
||||
rm -f core *.o *.a *.s
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -1,179 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Name: lm80.h
|
||||
* Project: Gigabit Ethernet Adapters, Common Modules
|
||||
* Version: $Revision: 1.6 $
|
||||
* Date: $Date: 2003/05/13 17:26:52 $
|
||||
* Purpose: Contains all defines for the LM80 Chip
|
||||
* (National Semiconductor).
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* (C)Copyright 1998-2002 SysKonnect.
|
||||
* (C)Copyright 2002-2003 Marvell.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* The information in this file is provided "AS IS" without warranty.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __INC_LM80_H
|
||||
#define __INC_LM80_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/* defines ********************************************************************/
|
||||
|
||||
/*
|
||||
* LM80 register definition
|
||||
*
|
||||
* All registers are 8 bit wide
|
||||
*/
|
||||
#define LM80_CFG 0x00 /* Configuration Register */
|
||||
#define LM80_ISRC_1 0x01 /* Interrupt Status Register 1 */
|
||||
#define LM80_ISRC_2 0x02 /* Interrupt Status Register 2 */
|
||||
#define LM80_IMSK_1 0x03 /* Interrupt Mask Register 1 */
|
||||
#define LM80_IMSK_2 0x04 /* Interrupt Mask Register 2 */
|
||||
#define LM80_FAN_CTRL 0x05 /* Fan Devisor/RST#/OS# Register */
|
||||
#define LM80_TEMP_CTRL 0x06 /* OS# Config, Temp Res. Reg */
|
||||
/* 0x07 - 0x1f reserved */
|
||||
/* current values */
|
||||
#define LM80_VT0_IN 0x20 /* current Voltage 0 value */
|
||||
#define LM80_VT1_IN 0x21 /* current Voltage 1 value */
|
||||
#define LM80_VT2_IN 0x22 /* current Voltage 2 value */
|
||||
#define LM80_VT3_IN 0x23 /* current Voltage 3 value */
|
||||
#define LM80_VT4_IN 0x24 /* current Voltage 4 value */
|
||||
#define LM80_VT5_IN 0x25 /* current Voltage 5 value */
|
||||
#define LM80_VT6_IN 0x26 /* current Voltage 6 value */
|
||||
#define LM80_TEMP_IN 0x27 /* current Temperature value */
|
||||
#define LM80_FAN1_IN 0x28 /* current Fan 1 count */
|
||||
#define LM80_FAN2_IN 0x29 /* current Fan 2 count */
|
||||
/* limit values */
|
||||
#define LM80_VT0_HIGH_LIM 0x2a /* high limit val for Voltage 0 */
|
||||
#define LM80_VT0_LOW_LIM 0x2b /* low limit val for Voltage 0 */
|
||||
#define LM80_VT1_HIGH_LIM 0x2c /* high limit val for Voltage 1 */
|
||||
#define LM80_VT1_LOW_LIM 0x2d /* low limit val for Voltage 1 */
|
||||
#define LM80_VT2_HIGH_LIM 0x2e /* high limit val for Voltage 2 */
|
||||
#define LM80_VT2_LOW_LIM 0x2f /* low limit val for Voltage 2 */
|
||||
#define LM80_VT3_HIGH_LIM 0x30 /* high limit val for Voltage 3 */
|
||||
#define LM80_VT3_LOW_LIM 0x31 /* low limit val for Voltage 3 */
|
||||
#define LM80_VT4_HIGH_LIM 0x32 /* high limit val for Voltage 4 */
|
||||
#define LM80_VT4_LOW_LIM 0x33 /* low limit val for Voltage 4 */
|
||||
#define LM80_VT5_HIGH_LIM 0x34 /* high limit val for Voltage 5 */
|
||||
#define LM80_VT5_LOW_LIM 0x35 /* low limit val for Voltage 5 */
|
||||
#define LM80_VT6_HIGH_LIM 0x36 /* high limit val for Voltage 6 */
|
||||
#define LM80_VT6_LOW_LIM 0x37 /* low limit val for Voltage 6 */
|
||||
#define LM80_THOT_LIM_UP 0x38 /* hot temperature limit (high) */
|
||||
#define LM80_THOT_LIM_LO 0x39 /* hot temperature limit (low) */
|
||||
#define LM80_TOS_LIM_UP 0x3a /* OS temperature limit (high) */
|
||||
#define LM80_TOS_LIM_LO 0x3b /* OS temperature limit (low) */
|
||||
#define LM80_FAN1_COUNT_LIM 0x3c /* Fan 1 count limit (high) */
|
||||
#define LM80_FAN2_COUNT_LIM 0x3d /* Fan 2 count limit (low) */
|
||||
/* 0x3e - 0x3f reserved */
|
||||
|
||||
/*
|
||||
* LM80 bit definitions
|
||||
*/
|
||||
|
||||
/* LM80_CFG Configuration Register */
|
||||
#define LM80_CFG_START (1<<0) /* start monitoring operation */
|
||||
#define LM80_CFG_INT_ENA (1<<1) /* enables the INT# Interrupt output */
|
||||
#define LM80_CFG_INT_POL (1<<2) /* INT# pol: 0 act low, 1 act high */
|
||||
#define LM80_CFG_INT_CLR (1<<3) /* disables INT#/RST_OUT#/OS# outputs */
|
||||
#define LM80_CFG_RESET (1<<4) /* signals a reset */
|
||||
#define LM80_CFG_CHASS_CLR (1<<5) /* clears Chassis Intrusion (CI) pin */
|
||||
#define LM80_CFG_GPO (1<<6) /* drives the GPO# pin */
|
||||
#define LM80_CFG_INIT (1<<7) /* restore power on defaults */
|
||||
|
||||
/* LM80_ISRC_1 Interrupt Status Register 1 */
|
||||
/* LM80_IMSK_1 Interrupt Mask Register 1 */
|
||||
#define LM80_IS_VT0 (1<<0) /* limit exceeded for Voltage 0 */
|
||||
#define LM80_IS_VT1 (1<<1) /* limit exceeded for Voltage 1 */
|
||||
#define LM80_IS_VT2 (1<<2) /* limit exceeded for Voltage 2 */
|
||||
#define LM80_IS_VT3 (1<<3) /* limit exceeded for Voltage 3 */
|
||||
#define LM80_IS_VT4 (1<<4) /* limit exceeded for Voltage 4 */
|
||||
#define LM80_IS_VT5 (1<<5) /* limit exceeded for Voltage 5 */
|
||||
#define LM80_IS_VT6 (1<<6) /* limit exceeded for Voltage 6 */
|
||||
#define LM80_IS_INT_IN (1<<7) /* state of INT_IN# */
|
||||
|
||||
/* LM80_ISRC_2 Interrupt Status Register 2 */
|
||||
/* LM80_IMSK_2 Interrupt Mask Register 2 */
|
||||
#define LM80_IS_TEMP (1<<0) /* HOT temperature limit exceeded */
|
||||
#define LM80_IS_BTI (1<<1) /* state of BTI# pin */
|
||||
#define LM80_IS_FAN1 (1<<2) /* count limit exceeded for Fan 1 */
|
||||
#define LM80_IS_FAN2 (1<<3) /* count limit exceeded for Fan 2 */
|
||||
#define LM80_IS_CI (1<<4) /* Chassis Intrusion occured */
|
||||
#define LM80_IS_OS (1<<5) /* OS temperature limit exceeded */
|
||||
/* bit 6 and 7 are reserved in LM80_ISRC_2 */
|
||||
#define LM80_IS_HT_IRQ_MD (1<<6) /* Hot temperature interrupt mode */
|
||||
#define LM80_IS_OT_IRQ_MD (1<<7) /* OS temperature interrupt mode */
|
||||
|
||||
/* LM80_FAN_CTRL Fan Devisor/RST#/OS# Register */
|
||||
#define LM80_FAN1_MD_SEL (1<<0) /* Fan 1 mode select */
|
||||
#define LM80_FAN2_MD_SEL (1<<1) /* Fan 2 mode select */
|
||||
#define LM80_FAN1_PRM_CTL (3<<2) /* Fan 1 speed control */
|
||||
#define LM80_FAN2_PRM_CTL (3<<4) /* Fan 2 speed control */
|
||||
#define LM80_FAN_OS_ENA (1<<6) /* enable OS mode on RST_OUT#/OS# pins*/
|
||||
#define LM80_FAN_RST_ENA (1<<7) /* sets RST_OUT#/OS# pins in RST mode */
|
||||
|
||||
/* LM80_TEMP_CTRL OS# Config, Temp Res. Reg */
|
||||
#define LM80_TEMP_OS_STAT (1<<0) /* mirrors the state of RST_OUT#/OS# */
|
||||
#define LM80_TEMP_OS_POL (1<<1) /* select OS# polarity */
|
||||
#define LM80_TEMP_OS_MODE (1<<2) /* selects Interrupt mode */
|
||||
#define LM80_TEMP_RES (1<<3) /* selects 9 or 11 bit temp resulution*/
|
||||
#define LM80_TEMP_LSB (0xf<<4)/* 4 LSBs of 11 bit temp data */
|
||||
#define LM80_TEMP_LSB_9 (1<<7) /* LSB of 9 bit temperature data */
|
||||
|
||||
/* 0x07 - 0x1f reserved */
|
||||
/* LM80_VT0_IN current Voltage 0 value */
|
||||
/* LM80_VT1_IN current Voltage 1 value */
|
||||
/* LM80_VT2_IN current Voltage 2 value */
|
||||
/* LM80_VT3_IN current Voltage 3 value */
|
||||
/* LM80_VT4_IN current Voltage 4 value */
|
||||
/* LM80_VT5_IN current Voltage 5 value */
|
||||
/* LM80_VT6_IN current Voltage 6 value */
|
||||
/* LM80_TEMP_IN current temperature value */
|
||||
/* LM80_FAN1_IN current Fan 1 count */
|
||||
/* LM80_FAN2_IN current Fan 2 count */
|
||||
/* LM80_VT0_HIGH_LIM high limit val for Voltage 0 */
|
||||
/* LM80_VT0_LOW_LIM low limit val for Voltage 0 */
|
||||
/* LM80_VT1_HIGH_LIM high limit val for Voltage 1 */
|
||||
/* LM80_VT1_LOW_LIM low limit val for Voltage 1 */
|
||||
/* LM80_VT2_HIGH_LIM high limit val for Voltage 2 */
|
||||
/* LM80_VT2_LOW_LIM low limit val for Voltage 2 */
|
||||
/* LM80_VT3_HIGH_LIM high limit val for Voltage 3 */
|
||||
/* LM80_VT3_LOW_LIM low limit val for Voltage 3 */
|
||||
/* LM80_VT4_HIGH_LIM high limit val for Voltage 4 */
|
||||
/* LM80_VT4_LOW_LIM low limit val for Voltage 4 */
|
||||
/* LM80_VT5_HIGH_LIM high limit val for Voltage 5 */
|
||||
/* LM80_VT5_LOW_LIM low limit val for Voltage 5 */
|
||||
/* LM80_VT6_HIGH_LIM high limit val for Voltage 6 */
|
||||
/* LM80_VT6_LOW_LIM low limit val for Voltage 6 */
|
||||
/* LM80_THOT_LIM_UP hot temperature limit (high) */
|
||||
/* LM80_THOT_LIM_LO hot temperature limit (low) */
|
||||
/* LM80_TOS_LIM_UP OS temperature limit (high) */
|
||||
/* LM80_TOS_LIM_LO OS temperature limit (low) */
|
||||
/* LM80_FAN1_COUNT_LIM Fan 1 count limit (high) */
|
||||
/* LM80_FAN2_COUNT_LIM Fan 2 count limit (low) */
|
||||
/* 0x3e - 0x3f reserved */
|
||||
|
||||
#define LM80_ADDR 0x28 /* LM80 default addr */
|
||||
|
||||
/* typedefs *******************************************************************/
|
||||
|
||||
|
||||
/* function prototypes ********************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* __INC_LM80_H */
|
|
@ -1,285 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Name: skaddr.h
|
||||
* Project: Gigabit Ethernet Adapters, ADDR-Modul
|
||||
* Version: $Revision: 1.29 $
|
||||
* Date: $Date: 2003/05/13 16:57:24 $
|
||||
* Purpose: Header file for Address Management (MC, UC, Prom).
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* (C)Copyright 1998-2002 SysKonnect GmbH.
|
||||
* (C)Copyright 2002-2003 Marvell.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* The information in this file is provided "AS IS" without warranty.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Description:
|
||||
*
|
||||
* This module is intended to manage multicast addresses and promiscuous mode
|
||||
* on GEnesis adapters.
|
||||
*
|
||||
* Include File Hierarchy:
|
||||
*
|
||||
* "skdrv1st.h"
|
||||
* ...
|
||||
* "sktypes.h"
|
||||
* "skqueue.h"
|
||||
* "skaddr.h"
|
||||
* ...
|
||||
* "skdrv2nd.h"
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __INC_SKADDR_H
|
||||
#define __INC_SKADDR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* cplusplus */
|
||||
|
||||
/* defines ********************************************************************/
|
||||
|
||||
#define SK_MAC_ADDR_LEN 6 /* Length of MAC address. */
|
||||
#define SK_MAX_ADDRS 14 /* #Addrs for exact match. */
|
||||
|
||||
/* ----- Common return values ----- */
|
||||
|
||||
#define SK_ADDR_SUCCESS 0 /* Function returned successfully. */
|
||||
#define SK_ADDR_ILLEGAL_PORT 100 /* Port number too high. */
|
||||
#define SK_ADDR_TOO_EARLY 101 /* Function called too early. */
|
||||
|
||||
/* ----- Clear/Add flag bits ----- */
|
||||
|
||||
#define SK_ADDR_PERMANENT 1 /* RLMT Address */
|
||||
|
||||
/* ----- Additional Clear flag bits ----- */
|
||||
|
||||
#define SK_MC_SW_ONLY 2 /* Do not update HW when clearing. */
|
||||
|
||||
/* ----- Override flag bits ----- */
|
||||
|
||||
#define SK_ADDR_LOGICAL_ADDRESS 0
|
||||
#define SK_ADDR_VIRTUAL_ADDRESS (SK_ADDR_LOGICAL_ADDRESS) /* old */
|
||||
#define SK_ADDR_PHYSICAL_ADDRESS 1
|
||||
#define SK_ADDR_CLEAR_LOGICAL 2
|
||||
#define SK_ADDR_SET_LOGICAL 4
|
||||
|
||||
/* ----- Override return values ----- */
|
||||
|
||||
#define SK_ADDR_OVERRIDE_SUCCESS (SK_ADDR_SUCCESS)
|
||||
#define SK_ADDR_DUPLICATE_ADDRESS 1
|
||||
#define SK_ADDR_MULTICAST_ADDRESS 2
|
||||
|
||||
/* ----- Partitioning of excact match table ----- */
|
||||
|
||||
#define SK_ADDR_EXACT_MATCHES 16 /* #Exact match entries. */
|
||||
|
||||
#define SK_ADDR_FIRST_MATCH_RLMT 1
|
||||
#define SK_ADDR_LAST_MATCH_RLMT 2
|
||||
#define SK_ADDR_FIRST_MATCH_DRV 3
|
||||
#define SK_ADDR_LAST_MATCH_DRV (SK_ADDR_EXACT_MATCHES - 1)
|
||||
|
||||
/* ----- SkAddrMcAdd/SkAddrMcUpdate return values ----- */
|
||||
|
||||
#define SK_MC_FILTERING_EXACT 0 /* Exact filtering. */
|
||||
#define SK_MC_FILTERING_INEXACT 1 /* Inexact filtering. */
|
||||
|
||||
/* ----- Additional SkAddrMcAdd return values ----- */
|
||||
|
||||
#define SK_MC_ILLEGAL_ADDRESS 2 /* Illegal address. */
|
||||
#define SK_MC_ILLEGAL_PORT 3 /* Illegal port (not the active one). */
|
||||
#define SK_MC_RLMT_OVERFLOW 4 /* Too many RLMT mc addresses. */
|
||||
|
||||
/* Promiscuous mode bits ----- */
|
||||
|
||||
#define SK_PROM_MODE_NONE 0 /* Normal receive. */
|
||||
#define SK_PROM_MODE_LLC 1 /* Receive all LLC frames. */
|
||||
#define SK_PROM_MODE_ALL_MC 2 /* Receive all multicast frames. */
|
||||
/* #define SK_PROM_MODE_NON_LLC 4 */ /* Receive all non-LLC frames. */
|
||||
|
||||
/* Macros */
|
||||
|
||||
#ifdef OLD_STUFF
|
||||
#ifndef SK_ADDR_EQUAL
|
||||
/*
|
||||
* "&" instead of "&&" allows better optimization on IA-64.
|
||||
* The replacement is safe here, as all bytes exist.
|
||||
*/
|
||||
#ifndef SK_ADDR_DWORD_COMPARE
|
||||
#define SK_ADDR_EQUAL(A1,A2) ( \
|
||||
(((SK_U8 *)(A1))[5] == ((SK_U8 *)(A2))[5]) & \
|
||||
(((SK_U8 *)(A1))[4] == ((SK_U8 *)(A2))[4]) & \
|
||||
(((SK_U8 *)(A1))[3] == ((SK_U8 *)(A2))[3]) & \
|
||||
(((SK_U8 *)(A1))[2] == ((SK_U8 *)(A2))[2]) & \
|
||||
(((SK_U8 *)(A1))[1] == ((SK_U8 *)(A2))[1]) & \
|
||||
(((SK_U8 *)(A1))[0] == ((SK_U8 *)(A2))[0]))
|
||||
#else /* SK_ADDR_DWORD_COMPARE */
|
||||
#define SK_ADDR_EQUAL(A1,A2) ( \
|
||||
(*(SK_U32 *)&(((SK_U8 *)(A1))[2]) == *(SK_U32 *)&(((SK_U8 *)(A2))[2])) & \
|
||||
(*(SK_U32 *)&(((SK_U8 *)(A1))[0]) == *(SK_U32 *)&(((SK_U8 *)(A2))[0])))
|
||||
#endif /* SK_ADDR_DWORD_COMPARE */
|
||||
#endif /* SK_ADDR_EQUAL */
|
||||
#endif /* 0 */
|
||||
|
||||
#ifndef SK_ADDR_EQUAL
|
||||
#ifndef SK_ADDR_DWORD_COMPARE
|
||||
#define SK_ADDR_EQUAL(A1,A2) ( \
|
||||
(((SK_U8 SK_FAR *)(A1))[5] == ((SK_U8 SK_FAR *)(A2))[5]) & \
|
||||
(((SK_U8 SK_FAR *)(A1))[4] == ((SK_U8 SK_FAR *)(A2))[4]) & \
|
||||
(((SK_U8 SK_FAR *)(A1))[3] == ((SK_U8 SK_FAR *)(A2))[3]) & \
|
||||
(((SK_U8 SK_FAR *)(A1))[2] == ((SK_U8 SK_FAR *)(A2))[2]) & \
|
||||
(((SK_U8 SK_FAR *)(A1))[1] == ((SK_U8 SK_FAR *)(A2))[1]) & \
|
||||
(((SK_U8 SK_FAR *)(A1))[0] == ((SK_U8 SK_FAR *)(A2))[0]))
|
||||
#else /* SK_ADDR_DWORD_COMPARE */
|
||||
#define SK_ADDR_EQUAL(A1,A2) ( \
|
||||
(*(SK_U16 SK_FAR *)&(((SK_U8 SK_FAR *)(A1))[4]) == \
|
||||
*(SK_U16 SK_FAR *)&(((SK_U8 SK_FAR *)(A2))[4])) && \
|
||||
(*(SK_U32 SK_FAR *)&(((SK_U8 SK_FAR *)(A1))[0]) == \
|
||||
*(SK_U32 SK_FAR *)&(((SK_U8 SK_FAR *)(A2))[0])))
|
||||
#endif /* SK_ADDR_DWORD_COMPARE */
|
||||
#endif /* SK_ADDR_EQUAL */
|
||||
|
||||
/* typedefs *******************************************************************/
|
||||
|
||||
typedef struct s_MacAddr {
|
||||
SK_U8 a[SK_MAC_ADDR_LEN];
|
||||
} SK_MAC_ADDR;
|
||||
|
||||
|
||||
/* SK_FILTER is used to ensure alignment of the filter. */
|
||||
typedef union s_InexactFilter {
|
||||
SK_U8 Bytes[8];
|
||||
SK_U64 Val; /* Dummy entry for alignment only. */
|
||||
} SK_FILTER64;
|
||||
|
||||
|
||||
typedef struct s_AddrNet SK_ADDR_NET;
|
||||
|
||||
|
||||
typedef struct s_AddrPort {
|
||||
|
||||
/* ----- Public part (read-only) ----- */
|
||||
|
||||
SK_MAC_ADDR CurrentMacAddress; /* Current physical MAC Address. */
|
||||
SK_MAC_ADDR PermanentMacAddress; /* Permanent physical MAC Address. */
|
||||
int PromMode; /* Promiscuous Mode. */
|
||||
|
||||
/* ----- Private part ----- */
|
||||
|
||||
SK_MAC_ADDR PreviousMacAddress; /* Prev. phys. MAC Address. */
|
||||
SK_BOOL CurrentMacAddressSet; /* CurrentMacAddress is set. */
|
||||
SK_U8 Align01;
|
||||
|
||||
SK_U32 FirstExactMatchRlmt;
|
||||
SK_U32 NextExactMatchRlmt;
|
||||
SK_U32 FirstExactMatchDrv;
|
||||
SK_U32 NextExactMatchDrv;
|
||||
SK_MAC_ADDR Exact[SK_ADDR_EXACT_MATCHES];
|
||||
SK_FILTER64 InexactFilter; /* For 64-bit hash register. */
|
||||
SK_FILTER64 InexactRlmtFilter; /* For 64-bit hash register. */
|
||||
SK_FILTER64 InexactDrvFilter; /* For 64-bit hash register. */
|
||||
} SK_ADDR_PORT;
|
||||
|
||||
|
||||
struct s_AddrNet {
|
||||
/* ----- Public part (read-only) ----- */
|
||||
|
||||
SK_MAC_ADDR CurrentMacAddress; /* Logical MAC Address. */
|
||||
SK_MAC_ADDR PermanentMacAddress; /* Logical MAC Address. */
|
||||
|
||||
/* ----- Private part ----- */
|
||||
|
||||
SK_U32 ActivePort; /* View of module ADDR. */
|
||||
SK_BOOL CurrentMacAddressSet; /* CurrentMacAddress is set. */
|
||||
SK_U8 Align01;
|
||||
SK_U16 Align02;
|
||||
};
|
||||
|
||||
|
||||
typedef struct s_Addr {
|
||||
|
||||
/* ----- Public part (read-only) ----- */
|
||||
|
||||
SK_ADDR_NET Net[SK_MAX_NETS];
|
||||
SK_ADDR_PORT Port[SK_MAX_MACS];
|
||||
|
||||
/* ----- Private part ----- */
|
||||
} SK_ADDR;
|
||||
|
||||
/* function prototypes ********************************************************/
|
||||
|
||||
#ifndef SK_KR_PROTO
|
||||
|
||||
/* Functions provided by SkAddr */
|
||||
|
||||
/* ANSI/C++ compliant function prototypes */
|
||||
|
||||
extern int SkAddrInit(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Level);
|
||||
|
||||
extern int SkAddrMcClear(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
SK_U32 PortNumber,
|
||||
int Flags);
|
||||
|
||||
extern int SkAddrMcAdd(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
SK_U32 PortNumber,
|
||||
SK_MAC_ADDR *pMc,
|
||||
int Flags);
|
||||
|
||||
extern int SkAddrMcUpdate(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
SK_U32 PortNumber);
|
||||
|
||||
extern int SkAddrOverride(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
SK_U32 PortNumber,
|
||||
SK_MAC_ADDR SK_FAR *pNewAddr,
|
||||
int Flags);
|
||||
|
||||
extern int SkAddrPromiscuousChange(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
SK_U32 PortNumber,
|
||||
int NewPromMode);
|
||||
|
||||
#ifndef SK_SLIM
|
||||
extern int SkAddrSwap(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
SK_U32 FromPortNumber,
|
||||
SK_U32 ToPortNumber);
|
||||
#endif
|
||||
|
||||
#else /* defined(SK_KR_PROTO)) */
|
||||
|
||||
/* Non-ANSI/C++ compliant function prototypes */
|
||||
|
||||
#error KR-style prototypes are not yet provided.
|
||||
|
||||
#endif /* defined(SK_KR_PROTO)) */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* __INC_SKADDR_H */
|
|
@ -1,213 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Name: skcsum.h
|
||||
* Project: GEnesis - SysKonnect SK-NET Gigabit Ethernet (SK-98xx)
|
||||
* Version: $Revision: 1.10 $
|
||||
* Date: $Date: 2003/08/20 13:59:57 $
|
||||
* Purpose: Store/verify Internet checksum in send/receive packets.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* (C)Copyright 1998-2001 SysKonnect GmbH.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* The information in this file is provided "AS IS" without warranty.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Description:
|
||||
*
|
||||
* Public header file for the "GEnesis" common module "CSUM".
|
||||
*
|
||||
* "GEnesis" is an abbreviation of "Gigabit Ethernet Network System in Silicon"
|
||||
* and is the code name of this SysKonnect project.
|
||||
*
|
||||
* Compilation Options:
|
||||
*
|
||||
* SK_USE_CSUM - Define if CSUM is to be used. Otherwise, CSUM will be an
|
||||
* empty module.
|
||||
*
|
||||
* SKCS_OVERWRITE_PROTO - Define to overwrite the default protocol id
|
||||
* definitions. In this case, all SKCS_PROTO_xxx definitions must be made
|
||||
* external.
|
||||
*
|
||||
* SKCS_OVERWRITE_STATUS - Define to overwrite the default return status
|
||||
* definitions. In this case, all SKCS_STATUS_xxx definitions must be made
|
||||
* external.
|
||||
*
|
||||
* Include File Hierarchy:
|
||||
*
|
||||
* "h/skcsum.h"
|
||||
* "h/sktypes.h"
|
||||
* "h/skqueue.h"
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __INC_SKCSUM_H
|
||||
#define __INC_SKCSUM_H
|
||||
|
||||
#include "h/sktypes.h"
|
||||
#include "h/skqueue.h"
|
||||
|
||||
/* defines ********************************************************************/
|
||||
|
||||
/*
|
||||
* Define the default bit flags for 'SKCS_PACKET_INFO.ProtocolFlags' if no user
|
||||
* overwrite.
|
||||
*/
|
||||
#ifndef SKCS_OVERWRITE_PROTO /* User overwrite? */
|
||||
#define SKCS_PROTO_IP 0x1 /* IP (Internet Protocol version 4) */
|
||||
#define SKCS_PROTO_TCP 0x2 /* TCP (Transmission Control Protocol) */
|
||||
#define SKCS_PROTO_UDP 0x4 /* UDP (User Datagram Protocol) */
|
||||
|
||||
/* Indices for protocol statistics. */
|
||||
#define SKCS_PROTO_STATS_IP 0
|
||||
#define SKCS_PROTO_STATS_UDP 1
|
||||
#define SKCS_PROTO_STATS_TCP 2
|
||||
#define SKCS_NUM_PROTOCOLS 3 /* Number of supported protocols. */
|
||||
#endif /* !SKCS_OVERWRITE_PROTO */
|
||||
|
||||
/*
|
||||
* Define the default SKCS_STATUS type and values if no user overwrite.
|
||||
*
|
||||
* SKCS_STATUS_UNKNOWN_IP_VERSION - Not an IP v4 frame.
|
||||
* SKCS_STATUS_IP_CSUM_ERROR - IP checksum error.
|
||||
* SKCS_STATUS_IP_CSUM_ERROR_TCP - IP checksum error in TCP frame.
|
||||
* SKCS_STATUS_IP_CSUM_ERROR_UDP - IP checksum error in UDP frame
|
||||
* SKCS_STATUS_IP_FRAGMENT - IP fragment (IP checksum ok).
|
||||
* SKCS_STATUS_IP_CSUM_OK - IP checksum ok (not a TCP or UDP frame).
|
||||
* SKCS_STATUS_TCP_CSUM_ERROR - TCP checksum error (IP checksum ok).
|
||||
* SKCS_STATUS_UDP_CSUM_ERROR - UDP checksum error (IP checksum ok).
|
||||
* SKCS_STATUS_TCP_CSUM_OK - IP and TCP checksum ok.
|
||||
* SKCS_STATUS_UDP_CSUM_OK - IP and UDP checksum ok.
|
||||
* SKCS_STATUS_IP_CSUM_OK_NO_UDP - IP checksum OK and no UDP checksum.
|
||||
*/
|
||||
#ifndef SKCS_OVERWRITE_STATUS /* User overwrite? */
|
||||
#define SKCS_STATUS int /* Define status type. */
|
||||
|
||||
#define SKCS_STATUS_UNKNOWN_IP_VERSION 1
|
||||
#define SKCS_STATUS_IP_CSUM_ERROR 2
|
||||
#define SKCS_STATUS_IP_FRAGMENT 3
|
||||
#define SKCS_STATUS_IP_CSUM_OK 4
|
||||
#define SKCS_STATUS_TCP_CSUM_ERROR 5
|
||||
#define SKCS_STATUS_UDP_CSUM_ERROR 6
|
||||
#define SKCS_STATUS_TCP_CSUM_OK 7
|
||||
#define SKCS_STATUS_UDP_CSUM_OK 8
|
||||
/* needed for Microsoft */
|
||||
#define SKCS_STATUS_IP_CSUM_ERROR_UDP 9
|
||||
#define SKCS_STATUS_IP_CSUM_ERROR_TCP 10
|
||||
/* UDP checksum may be omitted */
|
||||
#define SKCS_STATUS_IP_CSUM_OK_NO_UDP 11
|
||||
#endif /* !SKCS_OVERWRITE_STATUS */
|
||||
|
||||
/* Clear protocol statistics event. */
|
||||
#define SK_CSUM_EVENT_CLEAR_PROTO_STATS 1
|
||||
|
||||
/*
|
||||
* Add two values in one's complement.
|
||||
*
|
||||
* Note: One of the two input values may be "longer" than 16-bit, but then the
|
||||
* resulting sum may be 17 bits long. In this case, add zero to the result using
|
||||
* SKCS_OC_ADD() again.
|
||||
*
|
||||
* Result = Value1 + Value2
|
||||
*/
|
||||
#define SKCS_OC_ADD(Result, Value1, Value2) { \
|
||||
unsigned long Sum; \
|
||||
\
|
||||
Sum = (unsigned long) (Value1) + (unsigned long) (Value2); \
|
||||
/* Add-in any carry. */ \
|
||||
(Result) = (Sum & 0xffff) + (Sum >> 16); \
|
||||
}
|
||||
|
||||
/*
|
||||
* Subtract two values in one's complement.
|
||||
*
|
||||
* Result = Value1 - Value2
|
||||
*/
|
||||
#define SKCS_OC_SUB(Result, Value1, Value2) \
|
||||
SKCS_OC_ADD((Result), (Value1), ~(Value2) & 0xffff)
|
||||
|
||||
/* typedefs *******************************************************************/
|
||||
|
||||
/*
|
||||
* SKCS_PROTO_STATS - The CSUM protocol statistics structure.
|
||||
*
|
||||
* There is one instance of this structure for each protocol supported.
|
||||
*/
|
||||
typedef struct s_CsProtocolStatistics {
|
||||
SK_U64 RxOkCts; /* Receive checksum ok. */
|
||||
SK_U64 RxUnableCts; /* Unable to verify receive checksum. */
|
||||
SK_U64 RxErrCts; /* Receive checksum error. */
|
||||
SK_U64 TxOkCts; /* Transmit checksum ok. */
|
||||
SK_U64 TxUnableCts; /* Unable to calculate checksum in hw. */
|
||||
} SKCS_PROTO_STATS;
|
||||
|
||||
/*
|
||||
* s_Csum - The CSUM module context structure.
|
||||
*/
|
||||
typedef struct s_Csum {
|
||||
/* Enabled receive SK_PROTO_XXX bit flags. */
|
||||
unsigned ReceiveFlags[SK_MAX_NETS];
|
||||
#ifdef TX_CSUM
|
||||
unsigned TransmitFlags[SK_MAX_NETS];
|
||||
#endif /* TX_CSUM */
|
||||
|
||||
/* The protocol statistics structure; one per supported protocol. */
|
||||
SKCS_PROTO_STATS ProtoStats[SK_MAX_NETS][SKCS_NUM_PROTOCOLS];
|
||||
} SK_CSUM;
|
||||
|
||||
/*
|
||||
* SKCS_PACKET_INFO - The packet information structure.
|
||||
*/
|
||||
typedef struct s_CsPacketInfo {
|
||||
/* Bit field specifiying the desired/found protocols. */
|
||||
unsigned ProtocolFlags;
|
||||
|
||||
/* Length of complete IP header, including any option fields. */
|
||||
unsigned IpHeaderLength;
|
||||
|
||||
/* IP header checksum. */
|
||||
unsigned IpHeaderChecksum;
|
||||
|
||||
/* TCP/UDP pseudo header checksum. */
|
||||
unsigned PseudoHeaderChecksum;
|
||||
} SKCS_PACKET_INFO;
|
||||
|
||||
/* function prototypes ********************************************************/
|
||||
|
||||
#ifndef SK_CS_CALCULATE_CHECKSUM
|
||||
extern unsigned SkCsCalculateChecksum(
|
||||
void *pData,
|
||||
unsigned Length);
|
||||
#endif /* SK_CS_CALCULATE_CHECKSUM */
|
||||
|
||||
extern int SkCsEvent(
|
||||
SK_AC *pAc,
|
||||
SK_IOC Ioc,
|
||||
SK_U32 Event,
|
||||
SK_EVPARA Param);
|
||||
|
||||
extern SKCS_STATUS SkCsGetReceiveInfo(
|
||||
SK_AC *pAc,
|
||||
void *pIpHeader,
|
||||
unsigned Checksum1,
|
||||
unsigned Checksum2,
|
||||
int NetNumber);
|
||||
|
||||
extern void SkCsSetReceiveFlags(
|
||||
SK_AC *pAc,
|
||||
unsigned ReceiveFlags,
|
||||
unsigned *pChecksum1Offset,
|
||||
unsigned *pChecksum2Offset,
|
||||
int NetNumber);
|
||||
|
||||
#endif /* __INC_SKCSUM_H */
|
|
@ -1,74 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Name: skdebug.h
|
||||
* Project: Gigabit Ethernet Adapters, Common Modules
|
||||
* Version: $Revision: 1.14 $
|
||||
* Date: $Date: 2003/05/13 17:26:00 $
|
||||
* Purpose: SK specific DEBUG support
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* (C)Copyright 1998-2002 SysKonnect.
|
||||
* (C)Copyright 2002-2003 Marvell.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* The information in this file is provided "AS IS" without warranty.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __INC_SKDEBUG_H
|
||||
#define __INC_SKDEBUG_H
|
||||
|
||||
#ifdef DEBUG
|
||||
#ifndef SK_DBG_MSG
|
||||
#define SK_DBG_MSG(pAC,comp,cat,arg) \
|
||||
if ( ((comp) & SK_DBG_CHKMOD(pAC)) && \
|
||||
((cat) & SK_DBG_CHKCAT(pAC)) ) { \
|
||||
SK_DBG_PRINTF arg ; \
|
||||
}
|
||||
#endif
|
||||
#else
|
||||
#define SK_DBG_MSG(pAC,comp,lev,arg)
|
||||
#endif
|
||||
|
||||
/* PLS NOTE:
|
||||
* =========
|
||||
* Due to any restrictions of kernel printf routines do not use other
|
||||
* format identifiers as: %x %d %c %s .
|
||||
* Never use any combined format identifiers such as: %lx %ld in your
|
||||
* printf - argument (arg) because some OS specific kernel printfs may
|
||||
* only support some basic identifiers.
|
||||
*/
|
||||
|
||||
/* Debug modules */
|
||||
|
||||
#define SK_DBGMOD_MERR 0x00000001L /* general module error indication */
|
||||
#define SK_DBGMOD_HWM 0x00000002L /* Hardware init module */
|
||||
#define SK_DBGMOD_RLMT 0x00000004L /* RLMT module */
|
||||
#define SK_DBGMOD_VPD 0x00000008L /* VPD module */
|
||||
#define SK_DBGMOD_I2C 0x00000010L /* I2C module */
|
||||
#define SK_DBGMOD_PNMI 0x00000020L /* PNMI module */
|
||||
#define SK_DBGMOD_CSUM 0x00000040L /* CSUM module */
|
||||
#define SK_DBGMOD_ADDR 0x00000080L /* ADDR module */
|
||||
#define SK_DBGMOD_PECP 0x00000100L /* PECP module */
|
||||
#define SK_DBGMOD_POWM 0x00000200L /* Power Management module */
|
||||
|
||||
/* Debug events */
|
||||
|
||||
#define SK_DBGCAT_INIT 0x00000001L /* module/driver initialization */
|
||||
#define SK_DBGCAT_CTRL 0x00000002L /* controlling devices */
|
||||
#define SK_DBGCAT_ERR 0x00000004L /* error handling paths */
|
||||
#define SK_DBGCAT_TX 0x00000008L /* transmit path */
|
||||
#define SK_DBGCAT_RX 0x00000010L /* receive path */
|
||||
#define SK_DBGCAT_IRQ 0x00000020L /* general IRQ handling */
|
||||
#define SK_DBGCAT_QUEUE 0x00000040L /* any queue management */
|
||||
#define SK_DBGCAT_DUMP 0x00000080L /* large data output e.g. hex dump */
|
||||
#define SK_DBGCAT_FATAL 0x00000100L /* fatal error */
|
||||
|
||||
#endif /* __INC_SKDEBUG_H */
|
|
@ -1,188 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Name: skdrv1st.h
|
||||
* Project: GEnesis, PCI Gigabit Ethernet Adapter
|
||||
* Version: $Revision: 1.4 $
|
||||
* Date: $Date: 2003/11/12 14:28:14 $
|
||||
* Purpose: First header file for driver and all other modules
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* (C)Copyright 1998-2002 SysKonnect GmbH.
|
||||
* (C)Copyright 2002-2003 Marvell.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* The information in this file is provided "AS IS" without warranty.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Description:
|
||||
*
|
||||
* This is the first include file of the driver, which includes all
|
||||
* neccessary system header files and some of the GEnesis header files.
|
||||
* It also defines some basic items.
|
||||
*
|
||||
* Include File Hierarchy:
|
||||
*
|
||||
* see skge.c
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __INC_SKDRV1ST_H
|
||||
#define __INC_SKDRV1ST_H
|
||||
|
||||
typedef struct s_AC SK_AC;
|
||||
|
||||
/* Set card versions */
|
||||
#define SK_FAR
|
||||
|
||||
/* override some default functions with optimized linux functions */
|
||||
|
||||
#define SK_PNMI_STORE_U16(p,v) memcpy((char*)(p),(char*)&(v),2)
|
||||
#define SK_PNMI_STORE_U32(p,v) memcpy((char*)(p),(char*)&(v),4)
|
||||
#define SK_PNMI_STORE_U64(p,v) memcpy((char*)(p),(char*)&(v),8)
|
||||
#define SK_PNMI_READ_U16(p,v) memcpy((char*)&(v),(char*)(p),2)
|
||||
#define SK_PNMI_READ_U32(p,v) memcpy((char*)&(v),(char*)(p),4)
|
||||
#define SK_PNMI_READ_U64(p,v) memcpy((char*)&(v),(char*)(p),8)
|
||||
|
||||
#define SK_ADDR_EQUAL(a1,a2) (!memcmp(a1,a2,6))
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <asm/byteorder.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/irq.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/etherdevice.h>
|
||||
#include <linux/skbuff.h>
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <asm/uaccess.h>
|
||||
#include <net/checksum.h>
|
||||
|
||||
#define SK_CS_CALCULATE_CHECKSUM
|
||||
#ifndef CONFIG_X86_64
|
||||
#define SkCsCalculateChecksum(p,l) ((~ip_compute_csum(p, l)) & 0xffff)
|
||||
#else
|
||||
#define SkCsCalculateChecksum(p,l) ((~ip_fast_csum(p, l)) & 0xffff)
|
||||
#endif
|
||||
|
||||
#include "h/sktypes.h"
|
||||
#include "h/skerror.h"
|
||||
#include "h/skdebug.h"
|
||||
#include "h/lm80.h"
|
||||
#include "h/xmac_ii.h"
|
||||
|
||||
#ifdef __LITTLE_ENDIAN
|
||||
#define SK_LITTLE_ENDIAN
|
||||
#else
|
||||
#define SK_BIG_ENDIAN
|
||||
#endif
|
||||
|
||||
#define SK_NET_DEVICE net_device
|
||||
|
||||
|
||||
/* we use gethrtime(), return unit: nanoseconds */
|
||||
#define SK_TICKS_PER_SEC 100
|
||||
|
||||
#define SK_MEM_MAPPED_IO
|
||||
|
||||
// #define SK_RLMT_SLOW_LOOKAHEAD
|
||||
|
||||
#define SK_MAX_MACS 2
|
||||
#define SK_MAX_NETS 2
|
||||
|
||||
#define SK_IOC char __iomem *
|
||||
|
||||
typedef struct s_DrvRlmtMbuf SK_MBUF;
|
||||
|
||||
#define SK_CONST64 INT64_C
|
||||
#define SK_CONSTU64 UINT64_C
|
||||
|
||||
#define SK_MEMCPY(dest,src,size) memcpy(dest,src,size)
|
||||
#define SK_MEMCMP(s1,s2,size) memcmp(s1,s2,size)
|
||||
#define SK_MEMSET(dest,val,size) memset(dest,val,size)
|
||||
#define SK_STRLEN(pStr) strlen((char*)(pStr))
|
||||
#define SK_STRNCPY(pDest,pSrc,size) strncpy((char*)(pDest),(char*)(pSrc),size)
|
||||
#define SK_STRCMP(pStr1,pStr2) strcmp((char*)(pStr1),(char*)(pStr2))
|
||||
|
||||
/* macros to access the adapter */
|
||||
#define SK_OUT8(b,a,v) writeb((v), ((b)+(a)))
|
||||
#define SK_OUT16(b,a,v) writew((v), ((b)+(a)))
|
||||
#define SK_OUT32(b,a,v) writel((v), ((b)+(a)))
|
||||
#define SK_IN8(b,a,pv) (*(pv) = readb((b)+(a)))
|
||||
#define SK_IN16(b,a,pv) (*(pv) = readw((b)+(a)))
|
||||
#define SK_IN32(b,a,pv) (*(pv) = readl((b)+(a)))
|
||||
|
||||
#define int8_t char
|
||||
#define int16_t short
|
||||
#define int32_t long
|
||||
#define int64_t long long
|
||||
#define uint8_t u_char
|
||||
#define uint16_t u_short
|
||||
#define uint32_t u_long
|
||||
#define uint64_t unsigned long long
|
||||
#define t_scalar_t int
|
||||
#define t_uscalar_t unsigned int
|
||||
#define uintptr_t unsigned long
|
||||
|
||||
#define __CONCAT__(A,B) A##B
|
||||
|
||||
#define INT32_C(a) __CONCAT__(a,L)
|
||||
#define INT64_C(a) __CONCAT__(a,LL)
|
||||
#define UINT32_C(a) __CONCAT__(a,UL)
|
||||
#define UINT64_C(a) __CONCAT__(a,ULL)
|
||||
|
||||
#ifdef DEBUG
|
||||
#define SK_DBG_PRINTF printk
|
||||
#ifndef SK_DEBUG_CHKMOD
|
||||
#define SK_DEBUG_CHKMOD 0
|
||||
#endif
|
||||
#ifndef SK_DEBUG_CHKCAT
|
||||
#define SK_DEBUG_CHKCAT 0
|
||||
#endif
|
||||
/* those come from the makefile */
|
||||
#define SK_DBG_CHKMOD(pAC) (SK_DEBUG_CHKMOD)
|
||||
#define SK_DBG_CHKCAT(pAC) (SK_DEBUG_CHKCAT)
|
||||
|
||||
extern void SkDbgPrintf(const char *format,...);
|
||||
|
||||
#define SK_DBGMOD_DRV 0x00010000
|
||||
|
||||
/**** possible driver debug categories ********************************/
|
||||
#define SK_DBGCAT_DRV_ENTRY 0x00010000
|
||||
#define SK_DBGCAT_DRV_SAP 0x00020000
|
||||
#define SK_DBGCAT_DRV_MCA 0x00040000
|
||||
#define SK_DBGCAT_DRV_TX_PROGRESS 0x00080000
|
||||
#define SK_DBGCAT_DRV_RX_PROGRESS 0x00100000
|
||||
#define SK_DBGCAT_DRV_PROGRESS 0x00200000
|
||||
#define SK_DBGCAT_DRV_MSG 0x00400000
|
||||
#define SK_DBGCAT_DRV_PROM 0x00800000
|
||||
#define SK_DBGCAT_DRV_TX_FRAME 0x01000000
|
||||
#define SK_DBGCAT_DRV_ERROR 0x02000000
|
||||
#define SK_DBGCAT_DRV_INT_SRC 0x04000000
|
||||
#define SK_DBGCAT_DRV_EVENT 0x08000000
|
||||
|
||||
#endif
|
||||
|
||||
#define SK_ERR_LOG SkErrorLog
|
||||
|
||||
extern void SkErrorLog(SK_AC*, int, int, char*);
|
||||
|
||||
#endif
|
||||
|
|
@ -1,447 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Name: skdrv2nd.h
|
||||
* Project: GEnesis, PCI Gigabit Ethernet Adapter
|
||||
* Version: $Revision: 1.10 $
|
||||
* Date: $Date: 2003/12/11 16:04:45 $
|
||||
* Purpose: Second header file for driver and all other modules
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* (C)Copyright 1998-2002 SysKonnect GmbH.
|
||||
* (C)Copyright 2002-2003 Marvell.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* The information in this file is provided "AS IS" without warranty.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Description:
|
||||
*
|
||||
* This is the second include file of the driver, which includes all other
|
||||
* neccessary files and defines all structures and constants used by the
|
||||
* driver and the common modules.
|
||||
*
|
||||
* Include File Hierarchy:
|
||||
*
|
||||
* see skge.c
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __INC_SKDRV2ND_H
|
||||
#define __INC_SKDRV2ND_H
|
||||
|
||||
#include "h/skqueue.h"
|
||||
#include "h/skgehwt.h"
|
||||
#include "h/sktimer.h"
|
||||
#include "h/ski2c.h"
|
||||
#include "h/skgepnmi.h"
|
||||
#include "h/skvpd.h"
|
||||
#include "h/skgehw.h"
|
||||
#include "h/skgeinit.h"
|
||||
#include "h/skaddr.h"
|
||||
#include "h/skgesirq.h"
|
||||
#include "h/skcsum.h"
|
||||
#include "h/skrlmt.h"
|
||||
#include "h/skgedrv.h"
|
||||
|
||||
|
||||
extern SK_MBUF *SkDrvAllocRlmtMbuf(SK_AC*, SK_IOC, unsigned);
|
||||
extern void SkDrvFreeRlmtMbuf(SK_AC*, SK_IOC, SK_MBUF*);
|
||||
extern SK_U64 SkOsGetTime(SK_AC*);
|
||||
extern int SkPciReadCfgDWord(SK_AC*, int, SK_U32*);
|
||||
extern int SkPciReadCfgWord(SK_AC*, int, SK_U16*);
|
||||
extern int SkPciReadCfgByte(SK_AC*, int, SK_U8*);
|
||||
extern int SkPciWriteCfgWord(SK_AC*, int, SK_U16);
|
||||
extern int SkPciWriteCfgByte(SK_AC*, int, SK_U8);
|
||||
extern int SkDrvEvent(SK_AC*, SK_IOC IoC, SK_U32, SK_EVPARA);
|
||||
|
||||
#ifdef SK_DIAG_SUPPORT
|
||||
extern int SkDrvEnterDiagMode(SK_AC *pAc);
|
||||
extern int SkDrvLeaveDiagMode(SK_AC *pAc);
|
||||
#endif
|
||||
|
||||
struct s_DrvRlmtMbuf {
|
||||
SK_MBUF *pNext; /* Pointer to next RLMT Mbuf. */
|
||||
SK_U8 *pData; /* Data buffer (virtually contig.). */
|
||||
unsigned Size; /* Data buffer size. */
|
||||
unsigned Length; /* Length of packet (<= Size). */
|
||||
SK_U32 PortIdx; /* Receiving/transmitting port. */
|
||||
#ifdef SK_RLMT_MBUF_PRIVATE
|
||||
SK_RLMT_MBUF Rlmt; /* Private part for RLMT. */
|
||||
#endif /* SK_RLMT_MBUF_PRIVATE */
|
||||
struct sk_buff *pOs; /* Pointer to message block */
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* Time macros
|
||||
*/
|
||||
#if SK_TICKS_PER_SEC == 100
|
||||
#define SK_PNMI_HUNDREDS_SEC(t) (t)
|
||||
#else
|
||||
#define SK_PNMI_HUNDREDS_SEC(t) ((((unsigned long)t) * 100) / \
|
||||
(SK_TICKS_PER_SEC))
|
||||
#endif
|
||||
|
||||
/*
|
||||
* New SkOsGetTime
|
||||
*/
|
||||
#define SkOsGetTimeCurrent(pAC, pUsec) {\
|
||||
struct timeval t;\
|
||||
do_gettimeofday(&t);\
|
||||
*pUsec = ((((t.tv_sec) * 1000000L)+t.tv_usec)/10000);\
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* ioctl definitions
|
||||
*/
|
||||
#define SK_IOCTL_BASE (SIOCDEVPRIVATE)
|
||||
#define SK_IOCTL_GETMIB (SK_IOCTL_BASE + 0)
|
||||
#define SK_IOCTL_SETMIB (SK_IOCTL_BASE + 1)
|
||||
#define SK_IOCTL_PRESETMIB (SK_IOCTL_BASE + 2)
|
||||
#define SK_IOCTL_GEN (SK_IOCTL_BASE + 3)
|
||||
#define SK_IOCTL_DIAG (SK_IOCTL_BASE + 4)
|
||||
|
||||
typedef struct s_IOCTL SK_GE_IOCTL;
|
||||
|
||||
struct s_IOCTL {
|
||||
char __user * pData;
|
||||
unsigned int Len;
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* define sizes of descriptor rings in bytes
|
||||
*/
|
||||
|
||||
#define TX_RING_SIZE (8*1024)
|
||||
#define RX_RING_SIZE (24*1024)
|
||||
|
||||
/*
|
||||
* Buffer size for ethernet packets
|
||||
*/
|
||||
#define ETH_BUF_SIZE 1540
|
||||
#define ETH_MAX_MTU 1514
|
||||
#define ETH_MIN_MTU 60
|
||||
#define ETH_MULTICAST_BIT 0x01
|
||||
#define SK_JUMBO_MTU 9000
|
||||
|
||||
/*
|
||||
* transmit priority selects the queue: LOW=asynchron, HIGH=synchron
|
||||
*/
|
||||
#define TX_PRIO_LOW 0
|
||||
#define TX_PRIO_HIGH 1
|
||||
|
||||
/*
|
||||
* alignment of rx/tx descriptors
|
||||
*/
|
||||
#define DESCR_ALIGN 64
|
||||
|
||||
/*
|
||||
* definitions for pnmi. TODO
|
||||
*/
|
||||
#define SK_DRIVER_RESET(pAC, IoC) 0
|
||||
#define SK_DRIVER_SENDEVENT(pAC, IoC) 0
|
||||
#define SK_DRIVER_SELFTEST(pAC, IoC) 0
|
||||
/* For get mtu you must add an own function */
|
||||
#define SK_DRIVER_GET_MTU(pAc,IoC,i) 0
|
||||
#define SK_DRIVER_SET_MTU(pAc,IoC,i,v) 0
|
||||
#define SK_DRIVER_PRESET_MTU(pAc,IoC,i,v) 0
|
||||
|
||||
/*
|
||||
** Interim definition of SK_DRV_TIMER placed in this file until
|
||||
** common modules have been finalized
|
||||
*/
|
||||
#define SK_DRV_TIMER 11
|
||||
#define SK_DRV_MODERATION_TIMER 1
|
||||
#define SK_DRV_MODERATION_TIMER_LENGTH 1000000 /* 1 second */
|
||||
#define SK_DRV_RX_CLEANUP_TIMER 2
|
||||
#define SK_DRV_RX_CLEANUP_TIMER_LENGTH 1000000 /* 100 millisecs */
|
||||
|
||||
/*
|
||||
** Definitions regarding transmitting frames
|
||||
** any calculating any checksum.
|
||||
*/
|
||||
#define C_LEN_ETHERMAC_HEADER_DEST_ADDR 6
|
||||
#define C_LEN_ETHERMAC_HEADER_SRC_ADDR 6
|
||||
#define C_LEN_ETHERMAC_HEADER_LENTYPE 2
|
||||
#define C_LEN_ETHERMAC_HEADER ( (C_LEN_ETHERMAC_HEADER_DEST_ADDR) + \
|
||||
(C_LEN_ETHERMAC_HEADER_SRC_ADDR) + \
|
||||
(C_LEN_ETHERMAC_HEADER_LENTYPE) )
|
||||
|
||||
#define C_LEN_ETHERMTU_MINSIZE 46
|
||||
#define C_LEN_ETHERMTU_MAXSIZE_STD 1500
|
||||
#define C_LEN_ETHERMTU_MAXSIZE_JUMBO 9000
|
||||
|
||||
#define C_LEN_ETHERNET_MINSIZE ( (C_LEN_ETHERMAC_HEADER) + \
|
||||
(C_LEN_ETHERMTU_MINSIZE) )
|
||||
|
||||
#define C_OFFSET_IPHEADER C_LEN_ETHERMAC_HEADER
|
||||
#define C_OFFSET_IPHEADER_IPPROTO 9
|
||||
#define C_OFFSET_TCPHEADER_TCPCS 16
|
||||
#define C_OFFSET_UDPHEADER_UDPCS 6
|
||||
|
||||
#define C_OFFSET_IPPROTO ( (C_LEN_ETHERMAC_HEADER) + \
|
||||
(C_OFFSET_IPHEADER_IPPROTO) )
|
||||
|
||||
#define C_PROTO_ID_UDP 17 /* refer to RFC 790 or Stevens' */
|
||||
#define C_PROTO_ID_TCP 6 /* TCP/IP illustrated for details */
|
||||
|
||||
/* TX and RX descriptors *****************************************************/
|
||||
|
||||
typedef struct s_RxD RXD; /* the receive descriptor */
|
||||
|
||||
struct s_RxD {
|
||||
volatile SK_U32 RBControl; /* Receive Buffer Control */
|
||||
SK_U32 VNextRxd; /* Next receive descriptor,low dword */
|
||||
SK_U32 VDataLow; /* Receive buffer Addr, low dword */
|
||||
SK_U32 VDataHigh; /* Receive buffer Addr, high dword */
|
||||
SK_U32 FrameStat; /* Receive Frame Status word */
|
||||
SK_U32 TimeStamp; /* Time stamp from XMAC */
|
||||
SK_U32 TcpSums; /* TCP Sum 2 / TCP Sum 1 */
|
||||
SK_U32 TcpSumStarts; /* TCP Sum Start 2 / TCP Sum Start 1 */
|
||||
RXD *pNextRxd; /* Pointer to next Rxd */
|
||||
struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */
|
||||
};
|
||||
|
||||
typedef struct s_TxD TXD; /* the transmit descriptor */
|
||||
|
||||
struct s_TxD {
|
||||
volatile SK_U32 TBControl; /* Transmit Buffer Control */
|
||||
SK_U32 VNextTxd; /* Next transmit descriptor,low dword */
|
||||
SK_U32 VDataLow; /* Transmit Buffer Addr, low dword */
|
||||
SK_U32 VDataHigh; /* Transmit Buffer Addr, high dword */
|
||||
SK_U32 FrameStat; /* Transmit Frame Status Word */
|
||||
SK_U32 TcpSumOfs; /* Reserved / TCP Sum Offset */
|
||||
SK_U16 TcpSumSt; /* TCP Sum Start */
|
||||
SK_U16 TcpSumWr; /* TCP Sum Write */
|
||||
SK_U32 TcpReserved; /* not used */
|
||||
TXD *pNextTxd; /* Pointer to next Txd */
|
||||
struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */
|
||||
};
|
||||
|
||||
/* Used interrupt bits in the interrupts source register *********************/
|
||||
|
||||
#define DRIVER_IRQS ((IS_IRQ_SW) | \
|
||||
(IS_R1_F) |(IS_R2_F) | \
|
||||
(IS_XS1_F) |(IS_XA1_F) | \
|
||||
(IS_XS2_F) |(IS_XA2_F))
|
||||
|
||||
#define SPECIAL_IRQS ((IS_HW_ERR) |(IS_I2C_READY) | \
|
||||
(IS_EXT_REG) |(IS_TIMINT) | \
|
||||
(IS_PA_TO_RX1) |(IS_PA_TO_RX2) | \
|
||||
(IS_PA_TO_TX1) |(IS_PA_TO_TX2) | \
|
||||
(IS_MAC1) |(IS_LNK_SYNC_M1)| \
|
||||
(IS_MAC2) |(IS_LNK_SYNC_M2)| \
|
||||
(IS_R1_C) |(IS_R2_C) | \
|
||||
(IS_XS1_C) |(IS_XA1_C) | \
|
||||
(IS_XS2_C) |(IS_XA2_C))
|
||||
|
||||
#define IRQ_MASK ((IS_IRQ_SW) | \
|
||||
(IS_R1_B) |(IS_R1_F) |(IS_R2_B) |(IS_R2_F) | \
|
||||
(IS_XS1_B) |(IS_XS1_F) |(IS_XA1_B)|(IS_XA1_F)| \
|
||||
(IS_XS2_B) |(IS_XS2_F) |(IS_XA2_B)|(IS_XA2_F)| \
|
||||
(IS_HW_ERR) |(IS_I2C_READY)| \
|
||||
(IS_EXT_REG) |(IS_TIMINT) | \
|
||||
(IS_PA_TO_RX1) |(IS_PA_TO_RX2)| \
|
||||
(IS_PA_TO_TX1) |(IS_PA_TO_TX2)| \
|
||||
(IS_MAC1) |(IS_MAC2) | \
|
||||
(IS_R1_C) |(IS_R2_C) | \
|
||||
(IS_XS1_C) |(IS_XA1_C) | \
|
||||
(IS_XS2_C) |(IS_XA2_C))
|
||||
|
||||
#define IRQ_HWE_MASK (IS_ERR_MSK) /* enable all HW irqs */
|
||||
|
||||
typedef struct s_DevNet DEV_NET;
|
||||
|
||||
struct s_DevNet {
|
||||
int PortNr;
|
||||
int NetNr;
|
||||
SK_AC *pAC;
|
||||
};
|
||||
|
||||
typedef struct s_TxPort TX_PORT;
|
||||
|
||||
struct s_TxPort {
|
||||
/* the transmit descriptor rings */
|
||||
caddr_t pTxDescrRing; /* descriptor area memory */
|
||||
SK_U64 VTxDescrRing; /* descr. area bus virt. addr. */
|
||||
TXD *pTxdRingHead; /* Head of Tx rings */
|
||||
TXD *pTxdRingTail; /* Tail of Tx rings */
|
||||
TXD *pTxdRingPrev; /* descriptor sent previously */
|
||||
int TxdRingFree; /* # of free entrys */
|
||||
spinlock_t TxDesRingLock; /* serialize descriptor accesses */
|
||||
SK_IOC HwAddr; /* bmu registers address */
|
||||
int PortIndex; /* index number of port (0 or 1) */
|
||||
};
|
||||
|
||||
typedef struct s_RxPort RX_PORT;
|
||||
|
||||
struct s_RxPort {
|
||||
/* the receive descriptor rings */
|
||||
caddr_t pRxDescrRing; /* descriptor area memory */
|
||||
SK_U64 VRxDescrRing; /* descr. area bus virt. addr. */
|
||||
RXD *pRxdRingHead; /* Head of Rx rings */
|
||||
RXD *pRxdRingTail; /* Tail of Rx rings */
|
||||
RXD *pRxdRingPrev; /* descriptor given to BMU previously */
|
||||
int RxdRingFree; /* # of free entrys */
|
||||
int RxCsum; /* use receive checksum hardware */
|
||||
spinlock_t RxDesRingLock; /* serialize descriptor accesses */
|
||||
int RxFillLimit; /* limit for buffers in ring */
|
||||
SK_IOC HwAddr; /* bmu registers address */
|
||||
int PortIndex; /* index number of port (0 or 1) */
|
||||
};
|
||||
|
||||
/* Definitions needed for interrupt moderation *******************************/
|
||||
|
||||
#define IRQ_EOF_AS_TX ((IS_XA1_F) | (IS_XA2_F))
|
||||
#define IRQ_EOF_SY_TX ((IS_XS1_F) | (IS_XS2_F))
|
||||
#define IRQ_MASK_TX_ONLY ((IRQ_EOF_AS_TX)| (IRQ_EOF_SY_TX))
|
||||
#define IRQ_MASK_RX_ONLY ((IS_R1_F) | (IS_R2_F))
|
||||
#define IRQ_MASK_SP_ONLY (SPECIAL_IRQS)
|
||||
#define IRQ_MASK_TX_RX ((IRQ_MASK_TX_ONLY)| (IRQ_MASK_RX_ONLY))
|
||||
#define IRQ_MASK_SP_RX ((SPECIAL_IRQS) | (IRQ_MASK_RX_ONLY))
|
||||
#define IRQ_MASK_SP_TX ((SPECIAL_IRQS) | (IRQ_MASK_TX_ONLY))
|
||||
#define IRQ_MASK_RX_TX_SP ((SPECIAL_IRQS) | (IRQ_MASK_TX_RX))
|
||||
|
||||
#define C_INT_MOD_NONE 1
|
||||
#define C_INT_MOD_STATIC 2
|
||||
#define C_INT_MOD_DYNAMIC 4
|
||||
|
||||
#define C_CLK_FREQ_GENESIS 53215000 /* shorter: 53.125 MHz */
|
||||
#define C_CLK_FREQ_YUKON 78215000 /* shorter: 78.125 MHz */
|
||||
|
||||
#define C_INTS_PER_SEC_DEFAULT 2000
|
||||
#define C_INT_MOD_ENABLE_PERCENTAGE 50 /* if higher 50% enable */
|
||||
#define C_INT_MOD_DISABLE_PERCENTAGE 50 /* if lower 50% disable */
|
||||
#define C_INT_MOD_IPS_LOWER_RANGE 30
|
||||
#define C_INT_MOD_IPS_UPPER_RANGE 40000
|
||||
|
||||
|
||||
typedef struct s_DynIrqModInfo DIM_INFO;
|
||||
struct s_DynIrqModInfo {
|
||||
unsigned long PrevTimeVal;
|
||||
unsigned int PrevSysLoad;
|
||||
unsigned int PrevUsedTime;
|
||||
unsigned int PrevTotalTime;
|
||||
int PrevUsedDescrRatio;
|
||||
int NbrProcessedDescr;
|
||||
SK_U64 PrevPort0RxIntrCts;
|
||||
SK_U64 PrevPort1RxIntrCts;
|
||||
SK_U64 PrevPort0TxIntrCts;
|
||||
SK_U64 PrevPort1TxIntrCts;
|
||||
SK_BOOL ModJustEnabled; /* Moderation just enabled yes/no */
|
||||
|
||||
int MaxModIntsPerSec; /* Moderation Threshold */
|
||||
int MaxModIntsPerSecUpperLimit; /* Upper limit for DIM */
|
||||
int MaxModIntsPerSecLowerLimit; /* Lower limit for DIM */
|
||||
|
||||
long MaskIrqModeration; /* ModIrqType (eg. 'TxRx') */
|
||||
SK_BOOL DisplayStats; /* Stats yes/no */
|
||||
SK_BOOL AutoSizing; /* Resize DIM-timer on/off */
|
||||
int IntModTypeSelect; /* EnableIntMod (eg. 'dynamic') */
|
||||
|
||||
SK_TIMER ModTimer; /* just some timer */
|
||||
};
|
||||
|
||||
typedef struct s_PerStrm PER_STRM;
|
||||
|
||||
#define SK_ALLOC_IRQ 0x00000001
|
||||
|
||||
#ifdef SK_DIAG_SUPPORT
|
||||
#define DIAG_ACTIVE 1
|
||||
#define DIAG_NOTACTIVE 0
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Per board structure / Adapter Context structure:
|
||||
* Allocated within attach(9e) and freed within detach(9e).
|
||||
* Contains all 'per device' necessary handles, flags, locks etc.:
|
||||
*/
|
||||
struct s_AC {
|
||||
SK_GEINIT GIni; /* GE init struct */
|
||||
SK_PNMI Pnmi; /* PNMI data struct */
|
||||
SK_VPD vpd; /* vpd data struct */
|
||||
SK_QUEUE Event; /* Event queue */
|
||||
SK_HWT Hwt; /* Hardware Timer control struct */
|
||||
SK_TIMCTRL Tim; /* Software Timer control struct */
|
||||
SK_I2C I2c; /* I2C relevant data structure */
|
||||
SK_ADDR Addr; /* for Address module */
|
||||
SK_CSUM Csum; /* for checksum module */
|
||||
SK_RLMT Rlmt; /* for rlmt module */
|
||||
spinlock_t SlowPathLock; /* Normal IRQ lock */
|
||||
struct timer_list BlinkTimer; /* for LED blinking */
|
||||
int LedsOn;
|
||||
SK_PNMI_STRUCT_DATA PnmiStruct; /* structure to get all Pnmi-Data */
|
||||
int RlmtMode; /* link check mode to set */
|
||||
int RlmtNets; /* Number of nets */
|
||||
|
||||
SK_IOC IoBase; /* register set of adapter */
|
||||
int BoardLevel; /* level of active hw init (0-2) */
|
||||
|
||||
SK_U32 AllocFlag; /* flag allocation of resources */
|
||||
struct pci_dev *PciDev; /* for access to pci config space */
|
||||
struct SK_NET_DEVICE *dev[2]; /* pointer to device struct */
|
||||
|
||||
int RxBufSize; /* length of receive buffers */
|
||||
struct net_device_stats stats; /* linux 'netstat -i' statistics */
|
||||
int Index; /* internal board index number */
|
||||
|
||||
/* adapter RAM sizes for queues of active port */
|
||||
int RxQueueSize; /* memory used for receive queue */
|
||||
int TxSQueueSize; /* memory used for sync. tx queue */
|
||||
int TxAQueueSize; /* memory used for async. tx queue */
|
||||
|
||||
int PromiscCount; /* promiscuous mode counter */
|
||||
int AllMultiCount; /* allmulticast mode counter */
|
||||
int MulticCount; /* number of different MC */
|
||||
/* addresses for this board */
|
||||
/* (may be more than HW can)*/
|
||||
|
||||
int HWRevision; /* Hardware revision */
|
||||
int ActivePort; /* the active XMAC port */
|
||||
int MaxPorts; /* number of activated ports */
|
||||
int TxDescrPerRing; /* # of descriptors per tx ring */
|
||||
int RxDescrPerRing; /* # of descriptors per rx ring */
|
||||
|
||||
caddr_t pDescrMem; /* Pointer to the descriptor area */
|
||||
dma_addr_t pDescrMemDMA; /* PCI DMA address of area */
|
||||
|
||||
/* the port structures with descriptor rings */
|
||||
TX_PORT TxPort[SK_MAX_MACS][2];
|
||||
RX_PORT RxPort[SK_MAX_MACS];
|
||||
|
||||
SK_BOOL CheckQueue; /* check event queue soon */
|
||||
SK_TIMER DrvCleanupTimer;/* to check for pending descriptors */
|
||||
DIM_INFO DynIrqModInfo; /* all data related to DIM */
|
||||
|
||||
/* Only for tests */
|
||||
int PortDown;
|
||||
int ChipsetType; /* Chipset family type
|
||||
* 0 == Genesis family support
|
||||
* 1 == Yukon family support
|
||||
*/
|
||||
#ifdef SK_DIAG_SUPPORT
|
||||
SK_U32 DiagModeActive; /* is diag active? */
|
||||
SK_BOOL DiagFlowCtrl; /* for control purposes */
|
||||
SK_PNMI_STRUCT_DATA PnmiBackup; /* backup structure for all Pnmi-Data */
|
||||
SK_BOOL WasIfUp[SK_MAX_MACS]; /* for OpenClose while
|
||||
* DIAG is busy with NIC
|
||||
*/
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
|
||||
#endif /* __INC_SKDRV2ND_H */
|
||||
|
|
@ -1,55 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Name: skerror.h
|
||||
* Project: Gigabit Ethernet Adapters, Common Modules
|
||||
* Version: $Revision: 1.7 $
|
||||
* Date: $Date: 2003/05/13 17:25:13 $
|
||||
* Purpose: SK specific Error log support
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* (C)Copyright 1998-2002 SysKonnect.
|
||||
* (C)Copyright 2002-2003 Marvell.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* The information in this file is provided "AS IS" without warranty.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _INC_SKERROR_H_
|
||||
#define _INC_SKERROR_H_
|
||||
|
||||
/*
|
||||
* Define Error Classes
|
||||
*/
|
||||
#define SK_ERRCL_OTHER (0) /* Other error */
|
||||
#define SK_ERRCL_CONFIG (1L<<0) /* Configuration error */
|
||||
#define SK_ERRCL_INIT (1L<<1) /* Initialization error */
|
||||
#define SK_ERRCL_NORES (1L<<2) /* Out of Resources error */
|
||||
#define SK_ERRCL_SW (1L<<3) /* Internal Software error */
|
||||
#define SK_ERRCL_HW (1L<<4) /* Hardware Failure */
|
||||
#define SK_ERRCL_COMM (1L<<5) /* Communication error */
|
||||
|
||||
|
||||
/*
|
||||
* Define Error Code Bases
|
||||
*/
|
||||
#define SK_ERRBASE_RLMT 100 /* Base Error number for RLMT */
|
||||
#define SK_ERRBASE_HWINIT 200 /* Base Error number for HWInit */
|
||||
#define SK_ERRBASE_VPD 300 /* Base Error number for VPD */
|
||||
#define SK_ERRBASE_PNMI 400 /* Base Error number for PNMI */
|
||||
#define SK_ERRBASE_CSUM 500 /* Base Error number for Checksum */
|
||||
#define SK_ERRBASE_SIRQ 600 /* Base Error number for Special IRQ */
|
||||
#define SK_ERRBASE_I2C 700 /* Base Error number for I2C module */
|
||||
#define SK_ERRBASE_QUEUE 800 /* Base Error number for Scheduler */
|
||||
#define SK_ERRBASE_ADDR 900 /* Base Error number for Address module */
|
||||
#define SK_ERRBASE_PECP 1000 /* Base Error number for PECP */
|
||||
#define SK_ERRBASE_DRV 1100 /* Base Error number for Driver */
|
||||
|
||||
#endif /* _INC_SKERROR_H_ */
|
|
@ -1,51 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Name: skgedrv.h
|
||||
* Project: Gigabit Ethernet Adapters, Common Modules
|
||||
* Version: $Revision: 1.10 $
|
||||
* Date: $Date: 2003/07/04 12:25:01 $
|
||||
* Purpose: Interface with the driver
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* (C)Copyright 1998-2002 SysKonnect.
|
||||
* (C)Copyright 2002-2003 Marvell.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* The information in this file is provided "AS IS" without warranty.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __INC_SKGEDRV_H_
|
||||
#define __INC_SKGEDRV_H_
|
||||
|
||||
/* defines ********************************************************************/
|
||||
|
||||
/*
|
||||
* Define the driver events.
|
||||
* Usually the events are defined by the destination module.
|
||||
* In case of the driver we put the definition of the events here.
|
||||
*/
|
||||
#define SK_DRV_PORT_RESET 1 /* The port needs to be reset */
|
||||
#define SK_DRV_NET_UP 2 /* The net is operational */
|
||||
#define SK_DRV_NET_DOWN 3 /* The net is down */
|
||||
#define SK_DRV_SWITCH_SOFT 4 /* Ports switch with both links connected */
|
||||
#define SK_DRV_SWITCH_HARD 5 /* Port switch due to link failure */
|
||||
#define SK_DRV_RLMT_SEND 6 /* Send a RLMT packet */
|
||||
#define SK_DRV_ADAP_FAIL 7 /* The whole adapter fails */
|
||||
#define SK_DRV_PORT_FAIL 8 /* One port fails */
|
||||
#define SK_DRV_SWITCH_INTERN 9 /* Port switch by the driver itself */
|
||||
#define SK_DRV_POWER_DOWN 10 /* Power down mode */
|
||||
#define SK_DRV_TIMER 11 /* Timer for free use */
|
||||
#ifdef SK_NO_RLMT
|
||||
#define SK_DRV_LINK_UP 12 /* Link Up event for driver */
|
||||
#define SK_DRV_LINK_DOWN 13 /* Link Down event for driver */
|
||||
#endif
|
||||
#define SK_DRV_DOWNSHIFT_DET 14 /* Downshift 4-Pair / 2-Pair (YUKON only) */
|
||||
#endif /* __INC_SKGEDRV_H_ */
|
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
@ -1,48 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Name: skhwt.h
|
||||
* Project: Gigabit Ethernet Adapters, Event Scheduler Module
|
||||
* Version: $Revision: 1.7 $
|
||||
* Date: $Date: 2003/09/16 12:55:08 $
|
||||
* Purpose: Defines for the hardware timer functions
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* (C)Copyright 1998-2002 SysKonnect GmbH.
|
||||
* (C)Copyright 2002-2003 Marvell.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* The information in this file is provided "AS IS" without warranty.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*
|
||||
* SKGEHWT.H contains all defines and types for the timer functions
|
||||
*/
|
||||
|
||||
#ifndef _SKGEHWT_H_
|
||||
#define _SKGEHWT_H_
|
||||
|
||||
/*
|
||||
* SK Hardware Timer
|
||||
* - needed wherever the HWT module is used
|
||||
* - use in Adapters context name pAC->Hwt
|
||||
*/
|
||||
typedef struct s_Hwt {
|
||||
SK_U32 TStart; /* HWT start */
|
||||
SK_U32 TStop; /* HWT stop */
|
||||
int TActive; /* HWT: flag : active/inactive */
|
||||
} SK_HWT;
|
||||
|
||||
extern void SkHwtInit(SK_AC *pAC, SK_IOC Ioc);
|
||||
extern void SkHwtStart(SK_AC *pAC, SK_IOC Ioc, SK_U32 Time);
|
||||
extern void SkHwtStop(SK_AC *pAC, SK_IOC Ioc);
|
||||
extern SK_U32 SkHwtRead(SK_AC *pAC, SK_IOC Ioc);
|
||||
extern void SkHwtIsr(SK_AC *pAC, SK_IOC Ioc);
|
||||
#endif /* _SKGEHWT_H_ */
|
|
@ -1,210 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Name: skgei2c.h
|
||||
* Project: Gigabit Ethernet Adapters, TWSI-Module
|
||||
* Version: $Revision: 1.25 $
|
||||
* Date: $Date: 2003/10/20 09:06:05 $
|
||||
* Purpose: Special defines for TWSI
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* (C)Copyright 1998-2002 SysKonnect.
|
||||
* (C)Copyright 2002-2003 Marvell.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* The information in this file is provided "AS IS" without warranty.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*
|
||||
* SKGEI2C.H contains all SK-98xx specific defines for the TWSI handling
|
||||
*/
|
||||
|
||||
#ifndef _INC_SKGEI2C_H_
|
||||
#define _INC_SKGEI2C_H_
|
||||
|
||||
/*
|
||||
* Macros to access the B2_I2C_CTRL
|
||||
*/
|
||||
#define SK_I2C_CTL(IoC, flag, dev, dev_size, reg, burst) \
|
||||
SK_OUT32(IoC, B2_I2C_CTRL,\
|
||||
(flag ? 0x80000000UL : 0x0L) | \
|
||||
(((SK_U32)reg << 16) & I2C_ADDR) | \
|
||||
(((SK_U32)dev << 9) & I2C_DEV_SEL) | \
|
||||
(dev_size & I2C_DEV_SIZE) | \
|
||||
((burst << 4) & I2C_BURST_LEN))
|
||||
|
||||
#define SK_I2C_STOP(IoC) { \
|
||||
SK_U32 I2cCtrl; \
|
||||
SK_IN32(IoC, B2_I2C_CTRL, &I2cCtrl); \
|
||||
SK_OUT32(IoC, B2_I2C_CTRL, I2cCtrl | I2C_STOP); \
|
||||
}
|
||||
|
||||
#define SK_I2C_GET_CTL(IoC, pI2cCtrl) SK_IN32(IoC, B2_I2C_CTRL, pI2cCtrl)
|
||||
|
||||
/*
|
||||
* Macros to access the TWSI SW Registers
|
||||
*/
|
||||
#define SK_I2C_SET_BIT(IoC, SetBits) { \
|
||||
SK_U8 OrgBits; \
|
||||
SK_IN8(IoC, B2_I2C_SW, &OrgBits); \
|
||||
SK_OUT8(IoC, B2_I2C_SW, OrgBits | (SK_U8)(SetBits)); \
|
||||
}
|
||||
|
||||
#define SK_I2C_CLR_BIT(IoC, ClrBits) { \
|
||||
SK_U8 OrgBits; \
|
||||
SK_IN8(IoC, B2_I2C_SW, &OrgBits); \
|
||||
SK_OUT8(IoC, B2_I2C_SW, OrgBits & ~((SK_U8)(ClrBits))); \
|
||||
}
|
||||
|
||||
#define SK_I2C_GET_SW(IoC, pI2cSw) SK_IN8(IoC, B2_I2C_SW, pI2cSw)
|
||||
|
||||
/*
|
||||
* define the possible sensor states
|
||||
*/
|
||||
#define SK_SEN_IDLE 0 /* Idle: sensor not read */
|
||||
#define SK_SEN_VALUE 1 /* Value Read cycle */
|
||||
#define SK_SEN_VALEXT 2 /* Extended Value Read cycle */
|
||||
|
||||
/*
|
||||
* Conversion factor to convert read Voltage sensor to milli Volt
|
||||
* Conversion factor to convert read Temperature sensor to 10th degree Celsius
|
||||
*/
|
||||
#define SK_LM80_VT_LSB 22 /* 22mV LSB resolution */
|
||||
#define SK_LM80_TEMP_LSB 10 /* 1 degree LSB resolution */
|
||||
#define SK_LM80_TEMPEXT_LSB 5 /* 0.5 degree LSB resolution for ext. val. */
|
||||
|
||||
/*
|
||||
* formula: counter = (22500*60)/(rpm * divisor * pulses/2)
|
||||
* assuming: 6500rpm, 4 pulses, divisor 1
|
||||
*/
|
||||
#define SK_LM80_FAN_FAKTOR ((22500L*60)/(1*2))
|
||||
|
||||
/*
|
||||
* Define sensor management data
|
||||
* Maximum is reached on Genesis copper dual port and Yukon-64
|
||||
* Board specific maximum is in pAC->I2c.MaxSens
|
||||
*/
|
||||
#define SK_MAX_SENSORS 8 /* maximal no. of installed sensors */
|
||||
#define SK_MIN_SENSORS 5 /* minimal no. of installed sensors */
|
||||
|
||||
/*
|
||||
* To watch the state machine (SM) use the timer in two ways
|
||||
* instead of one as hitherto
|
||||
*/
|
||||
#define SK_TIMER_WATCH_SM 0 /* Watch the SM to finish in a spec. time */
|
||||
#define SK_TIMER_NEW_GAUGING 1 /* Start a new gauging when timer expires */
|
||||
|
||||
/*
|
||||
* Defines for the individual thresholds
|
||||
*/
|
||||
|
||||
/* Temperature sensor */
|
||||
#define SK_SEN_TEMP_HIGH_ERR 800 /* Temperature High Err Threshold */
|
||||
#define SK_SEN_TEMP_HIGH_WARN 700 /* Temperature High Warn Threshold */
|
||||
#define SK_SEN_TEMP_LOW_WARN 100 /* Temperature Low Warn Threshold */
|
||||
#define SK_SEN_TEMP_LOW_ERR 0 /* Temperature Low Err Threshold */
|
||||
|
||||
/* VCC which should be 5 V */
|
||||
#define SK_SEN_PCI_5V_HIGH_ERR 5588 /* Voltage PCI High Err Threshold */
|
||||
#define SK_SEN_PCI_5V_HIGH_WARN 5346 /* Voltage PCI High Warn Threshold */
|
||||
#define SK_SEN_PCI_5V_LOW_WARN 4664 /* Voltage PCI Low Warn Threshold */
|
||||
#define SK_SEN_PCI_5V_LOW_ERR 4422 /* Voltage PCI Low Err Threshold */
|
||||
|
||||
/*
|
||||
* VIO may be 5 V or 3.3 V. Initialization takes two parts:
|
||||
* 1. Initialize lowest lower limit and highest higher limit.
|
||||
* 2. After the first value is read correct the upper or the lower limit to
|
||||
* the appropriate C constant.
|
||||
*
|
||||
* Warning limits are +-5% of the exepected voltage.
|
||||
* Error limits are +-10% of the expected voltage.
|
||||
*/
|
||||
|
||||
/* Bug fix AF: 16.Aug.2001: Correct the init base of LM80 sensor */
|
||||
|
||||
#define SK_SEN_PCI_IO_5V_HIGH_ERR 5566 /* + 10% V PCI-IO High Err Threshold */
|
||||
#define SK_SEN_PCI_IO_5V_HIGH_WARN 5324 /* + 5% V PCI-IO High Warn Threshold */
|
||||
/* 5000 mVolt */
|
||||
#define SK_SEN_PCI_IO_5V_LOW_WARN 4686 /* - 5% V PCI-IO Low Warn Threshold */
|
||||
#define SK_SEN_PCI_IO_5V_LOW_ERR 4444 /* - 10% V PCI-IO Low Err Threshold */
|
||||
|
||||
#define SK_SEN_PCI_IO_RANGE_LIMITER 4000 /* 4000 mV range delimiter */
|
||||
|
||||
/* correction values for the second pass */
|
||||
#define SK_SEN_PCI_IO_3V3_HIGH_ERR 3850 /* + 15% V PCI-IO High Err Threshold */
|
||||
#define SK_SEN_PCI_IO_3V3_HIGH_WARN 3674 /* + 10% V PCI-IO High Warn Threshold */
|
||||
/* 3300 mVolt */
|
||||
#define SK_SEN_PCI_IO_3V3_LOW_WARN 2926 /* - 10% V PCI-IO Low Warn Threshold */
|
||||
#define SK_SEN_PCI_IO_3V3_LOW_ERR 2772 /* - 15% V PCI-IO Low Err Threshold */
|
||||
|
||||
/*
|
||||
* VDD voltage
|
||||
*/
|
||||
#define SK_SEN_VDD_HIGH_ERR 3630 /* Voltage ASIC High Err Threshold */
|
||||
#define SK_SEN_VDD_HIGH_WARN 3476 /* Voltage ASIC High Warn Threshold */
|
||||
#define SK_SEN_VDD_LOW_WARN 3146 /* Voltage ASIC Low Warn Threshold */
|
||||
#define SK_SEN_VDD_LOW_ERR 2970 /* Voltage ASIC Low Err Threshold */
|
||||
|
||||
/*
|
||||
* PHY PLL 3V3 voltage
|
||||
*/
|
||||
#define SK_SEN_PLL_3V3_HIGH_ERR 3630 /* Voltage PMA High Err Threshold */
|
||||
#define SK_SEN_PLL_3V3_HIGH_WARN 3476 /* Voltage PMA High Warn Threshold */
|
||||
#define SK_SEN_PLL_3V3_LOW_WARN 3146 /* Voltage PMA Low Warn Threshold */
|
||||
#define SK_SEN_PLL_3V3_LOW_ERR 2970 /* Voltage PMA Low Err Threshold */
|
||||
|
||||
/*
|
||||
* VAUX (YUKON only)
|
||||
*/
|
||||
#define SK_SEN_VAUX_3V3_HIGH_ERR 3630 /* Voltage VAUX High Err Threshold */
|
||||
#define SK_SEN_VAUX_3V3_HIGH_WARN 3476 /* Voltage VAUX High Warn Threshold */
|
||||
#define SK_SEN_VAUX_3V3_LOW_WARN 3146 /* Voltage VAUX Low Warn Threshold */
|
||||
#define SK_SEN_VAUX_3V3_LOW_ERR 2970 /* Voltage VAUX Low Err Threshold */
|
||||
#define SK_SEN_VAUX_0V_WARN_ERR 0 /* if VAUX not present */
|
||||
#define SK_SEN_VAUX_RANGE_LIMITER 1000 /* 1000 mV range delimiter */
|
||||
|
||||
/*
|
||||
* PHY 2V5 voltage
|
||||
*/
|
||||
#define SK_SEN_PHY_2V5_HIGH_ERR 2750 /* Voltage PHY High Err Threshold */
|
||||
#define SK_SEN_PHY_2V5_HIGH_WARN 2640 /* Voltage PHY High Warn Threshold */
|
||||
#define SK_SEN_PHY_2V5_LOW_WARN 2376 /* Voltage PHY Low Warn Threshold */
|
||||
#define SK_SEN_PHY_2V5_LOW_ERR 2222 /* Voltage PHY Low Err Threshold */
|
||||
|
||||
/*
|
||||
* ASIC Core 1V5 voltage (YUKON only)
|
||||
*/
|
||||
#define SK_SEN_CORE_1V5_HIGH_ERR 1650 /* Voltage ASIC Core High Err Threshold */
|
||||
#define SK_SEN_CORE_1V5_HIGH_WARN 1575 /* Voltage ASIC Core High Warn Threshold */
|
||||
#define SK_SEN_CORE_1V5_LOW_WARN 1425 /* Voltage ASIC Core Low Warn Threshold */
|
||||
#define SK_SEN_CORE_1V5_LOW_ERR 1350 /* Voltage ASIC Core Low Err Threshold */
|
||||
|
||||
/*
|
||||
* FAN 1 speed
|
||||
*/
|
||||
/* assuming: 6500rpm +-15%, 4 pulses,
|
||||
* warning at: 80 %
|
||||
* error at: 70 %
|
||||
* no upper limit
|
||||
*/
|
||||
#define SK_SEN_FAN_HIGH_ERR 20000 /* FAN Speed High Err Threshold */
|
||||
#define SK_SEN_FAN_HIGH_WARN 20000 /* FAN Speed High Warn Threshold */
|
||||
#define SK_SEN_FAN_LOW_WARN 5200 /* FAN Speed Low Warn Threshold */
|
||||
#define SK_SEN_FAN_LOW_ERR 4550 /* FAN Speed Low Err Threshold */
|
||||
|
||||
/*
|
||||
* Some Voltages need dynamic thresholds
|
||||
*/
|
||||
#define SK_SEN_DYN_INIT_NONE 0 /* No dynamic init of thresholds */
|
||||
#define SK_SEN_DYN_INIT_PCI_IO 10 /* Init PCI-IO with new thresholds */
|
||||
#define SK_SEN_DYN_INIT_VAUX 11 /* Init VAUX with new thresholds */
|
||||
|
||||
extern int SkLm80ReadSensor(SK_AC *pAC, SK_IOC IoC, SK_SENSOR *pSen);
|
||||
#endif /* n_INC_SKGEI2C_H */
|
|
@ -1,797 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Name: skgeinit.h
|
||||
* Project: Gigabit Ethernet Adapters, Common Modules
|
||||
* Version: $Revision: 1.83 $
|
||||
* Date: $Date: 2003/09/16 14:07:37 $
|
||||
* Purpose: Structures and prototypes for the GE Init Module
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* (C)Copyright 1998-2002 SysKonnect.
|
||||
* (C)Copyright 2002-2003 Marvell.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* The information in this file is provided "AS IS" without warranty.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __INC_SKGEINIT_H_
|
||||
#define __INC_SKGEINIT_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/* defines ********************************************************************/
|
||||
|
||||
#define SK_TEST_VAL 0x11335577UL
|
||||
|
||||
/* modifying Link LED behaviour (used with SkGeLinkLED()) */
|
||||
#define SK_LNK_OFF LED_OFF
|
||||
#define SK_LNK_ON (LED_ON | LED_BLK_OFF | LED_SYNC_OFF)
|
||||
#define SK_LNK_BLINK (LED_ON | LED_BLK_ON | LED_SYNC_ON)
|
||||
#define SK_LNK_PERM (LED_ON | LED_BLK_OFF | LED_SYNC_ON)
|
||||
#define SK_LNK_TST (LED_ON | LED_BLK_ON | LED_SYNC_OFF)
|
||||
|
||||
/* parameter 'Mode' when calling SK_HWAC_LINK_LED() */
|
||||
#define SK_LED_OFF LED_OFF
|
||||
#define SK_LED_ACTIVE (LED_ON | LED_BLK_OFF | LED_SYNC_OFF)
|
||||
#define SK_LED_STANDBY (LED_ON | LED_BLK_ON | LED_SYNC_OFF)
|
||||
|
||||
/* addressing LED Registers in SkGeXmitLED() */
|
||||
#define XMIT_LED_INI 0
|
||||
#define XMIT_LED_CNT (RX_LED_VAL - RX_LED_INI)
|
||||
#define XMIT_LED_CTRL (RX_LED_CTRL- RX_LED_INI)
|
||||
#define XMIT_LED_TST (RX_LED_TST - RX_LED_INI)
|
||||
|
||||
/* parameter 'Mode' when calling SkGeXmitLED() */
|
||||
#define SK_LED_DIS 0
|
||||
#define SK_LED_ENA 1
|
||||
#define SK_LED_TST 2
|
||||
|
||||
/* Counter and Timer constants, for a host clock of 62.5 MHz */
|
||||
#define SK_XMIT_DUR 0x002faf08UL /* 50 ms */
|
||||
#define SK_BLK_DUR 0x01dcd650UL /* 500 ms */
|
||||
|
||||
#define SK_DPOLL_DEF 0x00ee6b28UL /* 250 ms at 62.5 MHz */
|
||||
|
||||
#define SK_DPOLL_MAX 0x00ffffffUL /* 268 ms at 62.5 MHz */
|
||||
/* 215 ms at 78.12 MHz */
|
||||
|
||||
#define SK_FACT_62 100 /* is given in percent */
|
||||
#define SK_FACT_53 85 /* on GENESIS: 53.12 MHz */
|
||||
#define SK_FACT_78 125 /* on YUKON: 78.12 MHz */
|
||||
|
||||
/* Timeout values */
|
||||
#define SK_MAC_TO_53 72 /* MAC arbiter timeout */
|
||||
#define SK_PKT_TO_53 0x2000 /* Packet arbiter timeout */
|
||||
#define SK_PKT_TO_MAX 0xffff /* Maximum value */
|
||||
#define SK_RI_TO_53 36 /* RAM interface timeout */
|
||||
|
||||
#define SK_PHY_ACC_TO 600000 /* PHY access timeout */
|
||||
|
||||
/* RAM Buffer High Pause Threshold values */
|
||||
#define SK_RB_ULPP ( 8 * 1024) /* Upper Level in kB/8 */
|
||||
#define SK_RB_LLPP_S (10 * 1024) /* Lower Level for small Queues */
|
||||
#define SK_RB_LLPP_B (16 * 1024) /* Lower Level for big Queues */
|
||||
|
||||
#ifndef SK_BMU_RX_WM
|
||||
#define SK_BMU_RX_WM 0x600 /* BMU Rx Watermark */
|
||||
#endif
|
||||
#ifndef SK_BMU_TX_WM
|
||||
#define SK_BMU_TX_WM 0x600 /* BMU Tx Watermark */
|
||||
#endif
|
||||
|
||||
/* XMAC II Rx High Watermark */
|
||||
#define SK_XM_RX_HI_WM 0x05aa /* 1450 */
|
||||
|
||||
/* XMAC II Tx Threshold */
|
||||
#define SK_XM_THR_REDL 0x01fb /* .. for redundant link usage */
|
||||
#define SK_XM_THR_SL 0x01fb /* .. for single link adapters */
|
||||
#define SK_XM_THR_MULL 0x01fb /* .. for multiple link usage */
|
||||
#define SK_XM_THR_JUMBO 0x03fc /* .. for jumbo frame usage */
|
||||
|
||||
/* values for GIPortUsage */
|
||||
#define SK_RED_LINK 1 /* redundant link usage */
|
||||
#define SK_MUL_LINK 2 /* multiple link usage */
|
||||
#define SK_JUMBO_LINK 3 /* driver uses jumbo frames */
|
||||
|
||||
/* Minimum RAM Buffer Rx Queue Size */
|
||||
#define SK_MIN_RXQ_SIZE 16 /* 16 kB */
|
||||
|
||||
/* Minimum RAM Buffer Tx Queue Size */
|
||||
#define SK_MIN_TXQ_SIZE 16 /* 16 kB */
|
||||
|
||||
/* Queue Size units */
|
||||
#define QZ_UNITS 0x7
|
||||
#define QZ_STEP 8
|
||||
|
||||
/* Percentage of queue size from whole memory */
|
||||
/* 80 % for receive */
|
||||
#define RAM_QUOTA_RX 80L
|
||||
/* 0% for sync transfer */
|
||||
#define RAM_QUOTA_SYNC 0L
|
||||
/* the rest (20%) is taken for async transfer */
|
||||
|
||||
/* Get the rounded queue size in Bytes in 8k steps */
|
||||
#define ROUND_QUEUE_SIZE(SizeInBytes) \
|
||||
((((unsigned long) (SizeInBytes) + (QZ_STEP*1024L)-1) / 1024) & \
|
||||
~(QZ_STEP-1))
|
||||
|
||||
/* Get the rounded queue size in KBytes in 8k steps */
|
||||
#define ROUND_QUEUE_SIZE_KB(Kilobytes) \
|
||||
ROUND_QUEUE_SIZE((Kilobytes) * 1024L)
|
||||
|
||||
/* Types of RAM Buffer Queues */
|
||||
#define SK_RX_SRAM_Q 1 /* small receive queue */
|
||||
#define SK_RX_BRAM_Q 2 /* big receive queue */
|
||||
#define SK_TX_RAM_Q 3 /* small or big transmit queue */
|
||||
|
||||
/* parameter 'Dir' when calling SkGeStopPort() */
|
||||
#define SK_STOP_TX 1 /* Stops the transmit path, resets the XMAC */
|
||||
#define SK_STOP_RX 2 /* Stops the receive path */
|
||||
#define SK_STOP_ALL 3 /* Stops Rx and Tx path, resets the XMAC */
|
||||
|
||||
/* parameter 'RstMode' when calling SkGeStopPort() */
|
||||
#define SK_SOFT_RST 1 /* perform a software reset */
|
||||
#define SK_HARD_RST 2 /* perform a hardware reset */
|
||||
|
||||
/* Init Levels */
|
||||
#define SK_INIT_DATA 0 /* Init level 0: init data structures */
|
||||
#define SK_INIT_IO 1 /* Init level 1: init with IOs */
|
||||
#define SK_INIT_RUN 2 /* Init level 2: init for run time */
|
||||
|
||||
/* Link Mode Parameter */
|
||||
#define SK_LMODE_HALF 1 /* Half Duplex Mode */
|
||||
#define SK_LMODE_FULL 2 /* Full Duplex Mode */
|
||||
#define SK_LMODE_AUTOHALF 3 /* AutoHalf Duplex Mode */
|
||||
#define SK_LMODE_AUTOFULL 4 /* AutoFull Duplex Mode */
|
||||
#define SK_LMODE_AUTOBOTH 5 /* AutoBoth Duplex Mode */
|
||||
#define SK_LMODE_AUTOSENSE 6 /* configured mode auto sensing */
|
||||
#define SK_LMODE_INDETERMINATED 7 /* indeterminated */
|
||||
|
||||
/* Auto-negotiation timeout in 100ms granularity */
|
||||
#define SK_AND_MAX_TO 6 /* Wait 600 msec before link comes up */
|
||||
|
||||
/* Auto-negotiation error codes */
|
||||
#define SK_AND_OK 0 /* no error */
|
||||
#define SK_AND_OTHER 1 /* other error than below */
|
||||
#define SK_AND_DUP_CAP 2 /* Duplex capabilities error */
|
||||
|
||||
|
||||
/* Link Speed Capabilities */
|
||||
#define SK_LSPEED_CAP_AUTO (1<<0) /* Automatic resolution */
|
||||
#define SK_LSPEED_CAP_10MBPS (1<<1) /* 10 Mbps */
|
||||
#define SK_LSPEED_CAP_100MBPS (1<<2) /* 100 Mbps */
|
||||
#define SK_LSPEED_CAP_1000MBPS (1<<3) /* 1000 Mbps */
|
||||
#define SK_LSPEED_CAP_INDETERMINATED (1<<4) /* indeterminated */
|
||||
|
||||
/* Link Speed Parameter */
|
||||
#define SK_LSPEED_AUTO 1 /* Automatic resolution */
|
||||
#define SK_LSPEED_10MBPS 2 /* 10 Mbps */
|
||||
#define SK_LSPEED_100MBPS 3 /* 100 Mbps */
|
||||
#define SK_LSPEED_1000MBPS 4 /* 1000 Mbps */
|
||||
#define SK_LSPEED_INDETERMINATED 5 /* indeterminated */
|
||||
|
||||
/* Link Speed Current State */
|
||||
#define SK_LSPEED_STAT_UNKNOWN 1
|
||||
#define SK_LSPEED_STAT_10MBPS 2
|
||||
#define SK_LSPEED_STAT_100MBPS 3
|
||||
#define SK_LSPEED_STAT_1000MBPS 4
|
||||
#define SK_LSPEED_STAT_INDETERMINATED 5
|
||||
|
||||
|
||||
/* Link Capability Parameter */
|
||||
#define SK_LMODE_CAP_HALF (1<<0) /* Half Duplex Mode */
|
||||
#define SK_LMODE_CAP_FULL (1<<1) /* Full Duplex Mode */
|
||||
#define SK_LMODE_CAP_AUTOHALF (1<<2) /* AutoHalf Duplex Mode */
|
||||
#define SK_LMODE_CAP_AUTOFULL (1<<3) /* AutoFull Duplex Mode */
|
||||
#define SK_LMODE_CAP_INDETERMINATED (1<<4) /* indeterminated */
|
||||
|
||||
/* Link Mode Current State */
|
||||
#define SK_LMODE_STAT_UNKNOWN 1 /* Unknown Duplex Mode */
|
||||
#define SK_LMODE_STAT_HALF 2 /* Half Duplex Mode */
|
||||
#define SK_LMODE_STAT_FULL 3 /* Full Duplex Mode */
|
||||
#define SK_LMODE_STAT_AUTOHALF 4 /* Half Duplex Mode obtained by Auto-Neg */
|
||||
#define SK_LMODE_STAT_AUTOFULL 5 /* Full Duplex Mode obtained by Auto-Neg */
|
||||
#define SK_LMODE_STAT_INDETERMINATED 6 /* indeterminated */
|
||||
|
||||
/* Flow Control Mode Parameter (and capabilities) */
|
||||
#define SK_FLOW_MODE_NONE 1 /* No Flow-Control */
|
||||
#define SK_FLOW_MODE_LOC_SEND 2 /* Local station sends PAUSE */
|
||||
#define SK_FLOW_MODE_SYMMETRIC 3 /* Both stations may send PAUSE */
|
||||
#define SK_FLOW_MODE_SYM_OR_REM 4 /* Both stations may send PAUSE or
|
||||
* just the remote station may send PAUSE
|
||||
*/
|
||||
#define SK_FLOW_MODE_INDETERMINATED 5 /* indeterminated */
|
||||
|
||||
/* Flow Control Status Parameter */
|
||||
#define SK_FLOW_STAT_NONE 1 /* No Flow Control */
|
||||
#define SK_FLOW_STAT_REM_SEND 2 /* Remote Station sends PAUSE */
|
||||
#define SK_FLOW_STAT_LOC_SEND 3 /* Local station sends PAUSE */
|
||||
#define SK_FLOW_STAT_SYMMETRIC 4 /* Both station may send PAUSE */
|
||||
#define SK_FLOW_STAT_INDETERMINATED 5 /* indeterminated */
|
||||
|
||||
/* Master/Slave Mode Capabilities */
|
||||
#define SK_MS_CAP_AUTO (1<<0) /* Automatic resolution */
|
||||
#define SK_MS_CAP_MASTER (1<<1) /* This station is master */
|
||||
#define SK_MS_CAP_SLAVE (1<<2) /* This station is slave */
|
||||
#define SK_MS_CAP_INDETERMINATED (1<<3) /* indeterminated */
|
||||
|
||||
/* Set Master/Slave Mode Parameter (and capabilities) */
|
||||
#define SK_MS_MODE_AUTO 1 /* Automatic resolution */
|
||||
#define SK_MS_MODE_MASTER 2 /* This station is master */
|
||||
#define SK_MS_MODE_SLAVE 3 /* This station is slave */
|
||||
#define SK_MS_MODE_INDETERMINATED 4 /* indeterminated */
|
||||
|
||||
/* Master/Slave Status Parameter */
|
||||
#define SK_MS_STAT_UNSET 1 /* The M/S status is not set */
|
||||
#define SK_MS_STAT_MASTER 2 /* This station is master */
|
||||
#define SK_MS_STAT_SLAVE 3 /* This station is slave */
|
||||
#define SK_MS_STAT_FAULT 4 /* M/S resolution failed */
|
||||
#define SK_MS_STAT_INDETERMINATED 5 /* indeterminated */
|
||||
|
||||
/* parameter 'Mode' when calling SkXmSetRxCmd() */
|
||||
#define SK_STRIP_FCS_ON (1<<0) /* Enable FCS stripping of Rx frames */
|
||||
#define SK_STRIP_FCS_OFF (1<<1) /* Disable FCS stripping of Rx frames */
|
||||
#define SK_STRIP_PAD_ON (1<<2) /* Enable pad byte stripping of Rx fr */
|
||||
#define SK_STRIP_PAD_OFF (1<<3) /* Disable pad byte stripping of Rx fr */
|
||||
#define SK_LENERR_OK_ON (1<<4) /* Don't chk fr for in range len error */
|
||||
#define SK_LENERR_OK_OFF (1<<5) /* Check frames for in range len error */
|
||||
#define SK_BIG_PK_OK_ON (1<<6) /* Don't set Rx Error bit for big frames */
|
||||
#define SK_BIG_PK_OK_OFF (1<<7) /* Set Rx Error bit for big frames */
|
||||
#define SK_SELF_RX_ON (1<<8) /* Enable Rx of own packets */
|
||||
#define SK_SELF_RX_OFF (1<<9) /* Disable Rx of own packets */
|
||||
|
||||
/* parameter 'Para' when calling SkMacSetRxTxEn() */
|
||||
#define SK_MAC_LOOPB_ON (1<<0) /* Enable MAC Loopback Mode */
|
||||
#define SK_MAC_LOOPB_OFF (1<<1) /* Disable MAC Loopback Mode */
|
||||
#define SK_PHY_LOOPB_ON (1<<2) /* Enable PHY Loopback Mode */
|
||||
#define SK_PHY_LOOPB_OFF (1<<3) /* Disable PHY Loopback Mode */
|
||||
#define SK_PHY_FULLD_ON (1<<4) /* Enable GMII Full Duplex */
|
||||
#define SK_PHY_FULLD_OFF (1<<5) /* Disable GMII Full Duplex */
|
||||
|
||||
/* States of PState */
|
||||
#define SK_PRT_RESET 0 /* the port is reset */
|
||||
#define SK_PRT_STOP 1 /* the port is stopped (similar to SW reset) */
|
||||
#define SK_PRT_INIT 2 /* the port is initialized */
|
||||
#define SK_PRT_RUN 3 /* the port has an active link */
|
||||
|
||||
/* PHY power down modes */
|
||||
#define PHY_PM_OPERATIONAL_MODE 0 /* PHY operational mode */
|
||||
#define PHY_PM_DEEP_SLEEP 1 /* coma mode --> minimal power */
|
||||
#define PHY_PM_IEEE_POWER_DOWN 2 /* IEEE 22.2.4.1.5 compl. power down */
|
||||
#define PHY_PM_ENERGY_DETECT 3 /* energy detect */
|
||||
#define PHY_PM_ENERGY_DETECT_PLUS 4 /* energy detect plus */
|
||||
|
||||
/* Default receive frame limit for Workaround of XMAC Errata */
|
||||
#define SK_DEF_RX_WA_LIM SK_CONSTU64(100)
|
||||
|
||||
/* values for GILedBlinkCtrl (LED Blink Control) */
|
||||
#define SK_ACT_LED_BLINK (1<<0) /* Active LED blinking */
|
||||
#define SK_DUP_LED_NORMAL (1<<1) /* Duplex LED normal */
|
||||
#define SK_LED_LINK100_ON (1<<2) /* Link 100M LED on */
|
||||
|
||||
/* Link Partner Status */
|
||||
#define SK_LIPA_UNKNOWN 0 /* Link partner is in unknown state */
|
||||
#define SK_LIPA_MANUAL 1 /* Link partner is in detected manual state */
|
||||
#define SK_LIPA_AUTO 2 /* Link partner is in auto-negotiation state */
|
||||
|
||||
/* Maximum Restarts before restart is ignored (3Com WA) */
|
||||
#define SK_MAX_LRESTART 3 /* Max. 3 times the link is restarted */
|
||||
|
||||
/* Max. Auto-neg. timeouts before link detection in sense mode is reset */
|
||||
#define SK_MAX_ANEG_TO 10 /* Max. 10 times the sense mode is reset */
|
||||
|
||||
/* structures *****************************************************************/
|
||||
|
||||
/*
|
||||
* MAC specific functions
|
||||
*/
|
||||
typedef struct s_GeMacFunc {
|
||||
int (*pFnMacUpdateStats)(SK_AC *pAC, SK_IOC IoC, unsigned int Port);
|
||||
int (*pFnMacStatistic)(SK_AC *pAC, SK_IOC IoC, unsigned int Port,
|
||||
SK_U16 StatAddr, SK_U32 SK_FAR *pVal);
|
||||
int (*pFnMacResetCounter)(SK_AC *pAC, SK_IOC IoC, unsigned int Port);
|
||||
int (*pFnMacOverflow)(SK_AC *pAC, SK_IOC IoC, unsigned int Port,
|
||||
SK_U16 IStatus, SK_U64 SK_FAR *pVal);
|
||||
} SK_GEMACFUNC;
|
||||
|
||||
/*
|
||||
* Port Structure
|
||||
*/
|
||||
typedef struct s_GePort {
|
||||
#ifndef SK_DIAG
|
||||
SK_TIMER PWaTimer; /* Workaround Timer */
|
||||
SK_TIMER HalfDupChkTimer;
|
||||
#endif /* SK_DIAG */
|
||||
SK_U32 PPrevShorts; /* Previous Short Counter checking */
|
||||
SK_U32 PPrevFcs; /* Previous FCS Error Counter checking */
|
||||
SK_U64 PPrevRx; /* Previous RxOk Counter checking */
|
||||
SK_U64 PRxLim; /* Previous RxOk Counter checking */
|
||||
SK_U64 LastOctets; /* For half duplex hang check */
|
||||
int PLinkResCt; /* Link Restart Counter */
|
||||
int PAutoNegTimeOut;/* Auto-negotiation timeout current value */
|
||||
int PAutoNegTOCt; /* Auto-negotiation Timeout Counter */
|
||||
int PRxQSize; /* Port Rx Queue Size in kB */
|
||||
int PXSQSize; /* Port Synchronous Transmit Queue Size in kB */
|
||||
int PXAQSize; /* Port Asynchronous Transmit Queue Size in kB */
|
||||
SK_U32 PRxQRamStart; /* Receive Queue RAM Buffer Start Address */
|
||||
SK_U32 PRxQRamEnd; /* Receive Queue RAM Buffer End Address */
|
||||
SK_U32 PXsQRamStart; /* Sync Tx Queue RAM Buffer Start Address */
|
||||
SK_U32 PXsQRamEnd; /* Sync Tx Queue RAM Buffer End Address */
|
||||
SK_U32 PXaQRamStart; /* Async Tx Queue RAM Buffer Start Address */
|
||||
SK_U32 PXaQRamEnd; /* Async Tx Queue RAM Buffer End Address */
|
||||
SK_U32 PRxOverCnt; /* Receive Overflow Counter */
|
||||
int PRxQOff; /* Rx Queue Address Offset */
|
||||
int PXsQOff; /* Synchronous Tx Queue Address Offset */
|
||||
int PXaQOff; /* Asynchronous Tx Queue Address Offset */
|
||||
int PhyType; /* PHY used on this port */
|
||||
int PState; /* Port status (reset, stop, init, run) */
|
||||
SK_U16 PhyId1; /* PHY Id1 on this port */
|
||||
SK_U16 PhyAddr; /* MDIO/MDC PHY address */
|
||||
SK_U16 PIsave; /* Saved Interrupt status word */
|
||||
SK_U16 PSsave; /* Saved PHY status word */
|
||||
SK_U16 PGmANegAdv; /* Saved GPhy AutoNegAdvertisment register */
|
||||
SK_BOOL PHWLinkUp; /* The hardware Link is up (wiring) */
|
||||
SK_BOOL PLinkBroken; /* Is Link broken ? */
|
||||
SK_BOOL PCheckPar; /* Do we check for parity errors ? */
|
||||
SK_BOOL HalfDupTimerActive;
|
||||
SK_U8 PLinkCap; /* Link Capabilities */
|
||||
SK_U8 PLinkModeConf; /* Link Mode configured */
|
||||
SK_U8 PLinkMode; /* Link Mode currently used */
|
||||
SK_U8 PLinkModeStatus;/* Link Mode Status */
|
||||
SK_U8 PLinkSpeedCap; /* Link Speed Capabilities(10/100/1000 Mbps) */
|
||||
SK_U8 PLinkSpeed; /* configured Link Speed (10/100/1000 Mbps) */
|
||||
SK_U8 PLinkSpeedUsed; /* current Link Speed (10/100/1000 Mbps) */
|
||||
SK_U8 PFlowCtrlCap; /* Flow Control Capabilities */
|
||||
SK_U8 PFlowCtrlMode; /* Flow Control Mode */
|
||||
SK_U8 PFlowCtrlStatus;/* Flow Control Status */
|
||||
SK_U8 PMSCap; /* Master/Slave Capabilities */
|
||||
SK_U8 PMSMode; /* Master/Slave Mode */
|
||||
SK_U8 PMSStatus; /* Master/Slave Status */
|
||||
SK_BOOL PAutoNegFail; /* Auto-negotiation fail flag */
|
||||
SK_U8 PLipaAutoNeg; /* Auto-negotiation possible with Link Partner */
|
||||
SK_U8 PCableLen; /* Cable Length */
|
||||
SK_U8 PMdiPairLen[4]; /* MDI[0..3] Pair Length */
|
||||
SK_U8 PMdiPairSts[4]; /* MDI[0..3] Pair Diagnostic Status */
|
||||
SK_U8 PPhyPowerState; /* PHY current power state */
|
||||
int PMacColThres; /* MAC Collision Threshold */
|
||||
int PMacJamLen; /* MAC Jam length */
|
||||
int PMacJamIpgVal; /* MAC Jam IPG */
|
||||
int PMacJamIpgData; /* MAC IPG Jam to Data */
|
||||
int PMacIpgData; /* MAC Data IPG */
|
||||
SK_BOOL PMacLimit4; /* reset collision counter and backoff algorithm */
|
||||
} SK_GEPORT;
|
||||
|
||||
/*
|
||||
* Gigabit Ethernet Initialization Struct
|
||||
* (has to be included in the adapter context)
|
||||
*/
|
||||
typedef struct s_GeInit {
|
||||
int GIChipId; /* Chip Identification Number */
|
||||
int GIChipRev; /* Chip Revision Number */
|
||||
SK_U8 GIPciHwRev; /* PCI HW Revision Number */
|
||||
SK_BOOL GIGenesis; /* Genesis adapter ? */
|
||||
SK_BOOL GIYukon; /* YUKON-A1/Bx chip */
|
||||
SK_BOOL GIYukonLite; /* YUKON-Lite chip */
|
||||
SK_BOOL GICopperType; /* Copper Type adapter ? */
|
||||
SK_BOOL GIPciSlot64; /* 64-bit PCI Slot */
|
||||
SK_BOOL GIPciClock66; /* 66 MHz PCI Clock */
|
||||
SK_BOOL GIVauxAvail; /* VAUX available (YUKON) */
|
||||
SK_BOOL GIYukon32Bit; /* 32-Bit YUKON adapter */
|
||||
SK_U16 GILedBlinkCtrl; /* LED Blink Control */
|
||||
int GIMacsFound; /* Number of MACs found on this adapter */
|
||||
int GIMacType; /* MAC Type used on this adapter */
|
||||
int GIHstClkFact; /* Host Clock Factor (62.5 / HstClk * 100) */
|
||||
int GIPortUsage; /* Driver Port Usage */
|
||||
int GILevel; /* Initialization Level completed */
|
||||
int GIRamSize; /* The RAM size of the adapter in kB */
|
||||
int GIWolOffs; /* WOL Register Offset (HW-Bug in Rev. A) */
|
||||
SK_U32 GIRamOffs; /* RAM Address Offset for addr calculation */
|
||||
SK_U32 GIPollTimerVal; /* Descr. Poll Timer Init Val (HstClk ticks) */
|
||||
SK_U32 GIValIrqMask; /* Value for Interrupt Mask */
|
||||
SK_U32 GITimeStampCnt; /* Time Stamp High Counter (YUKON only) */
|
||||
SK_GEPORT GP[SK_MAX_MACS];/* Port Dependent Information */
|
||||
SK_GEMACFUNC GIFunc; /* MAC depedent functions */
|
||||
} SK_GEINIT;
|
||||
|
||||
/*
|
||||
* Error numbers and messages for skxmac2.c and skgeinit.c
|
||||
*/
|
||||
#define SKERR_HWI_E001 (SK_ERRBASE_HWINIT)
|
||||
#define SKERR_HWI_E001MSG "SkXmClrExactAddr() has got illegal parameters"
|
||||
#define SKERR_HWI_E002 (SKERR_HWI_E001+1)
|
||||
#define SKERR_HWI_E002MSG "SkGeInit(): Level 1 call missing"
|
||||
#define SKERR_HWI_E003 (SKERR_HWI_E002+1)
|
||||
#define SKERR_HWI_E003MSG "SkGeInit() called with illegal init Level"
|
||||
#define SKERR_HWI_E004 (SKERR_HWI_E003+1)
|
||||
#define SKERR_HWI_E004MSG "SkGeInitPort(): Queue Size illegal configured"
|
||||
#define SKERR_HWI_E005 (SKERR_HWI_E004+1)
|
||||
#define SKERR_HWI_E005MSG "SkGeInitPort(): cannot init running ports"
|
||||
#define SKERR_HWI_E006 (SKERR_HWI_E005+1)
|
||||
#define SKERR_HWI_E006MSG "SkGeMacInit(): PState does not match HW state"
|
||||
#define SKERR_HWI_E007 (SKERR_HWI_E006+1)
|
||||
#define SKERR_HWI_E007MSG "SkXmInitDupMd() called with invalid Dup Mode"
|
||||
#define SKERR_HWI_E008 (SKERR_HWI_E007+1)
|
||||
#define SKERR_HWI_E008MSG "SkXmSetRxCmd() called with invalid Mode"
|
||||
#define SKERR_HWI_E009 (SKERR_HWI_E008+1)
|
||||
#define SKERR_HWI_E009MSG "SkGeCfgSync() called although PXSQSize zero"
|
||||
#define SKERR_HWI_E010 (SKERR_HWI_E009+1)
|
||||
#define SKERR_HWI_E010MSG "SkGeCfgSync() called with invalid parameters"
|
||||
#define SKERR_HWI_E011 (SKERR_HWI_E010+1)
|
||||
#define SKERR_HWI_E011MSG "SkGeInitPort(): Receive Queue Size too small"
|
||||
#define SKERR_HWI_E012 (SKERR_HWI_E011+1)
|
||||
#define SKERR_HWI_E012MSG "SkGeInitPort(): invalid Queue Size specified"
|
||||
#define SKERR_HWI_E013 (SKERR_HWI_E012+1)
|
||||
#define SKERR_HWI_E013MSG "SkGeInitPort(): cfg changed for running queue"
|
||||
#define SKERR_HWI_E014 (SKERR_HWI_E013+1)
|
||||
#define SKERR_HWI_E014MSG "SkGeInitPort(): unknown GIPortUsage specified"
|
||||
#define SKERR_HWI_E015 (SKERR_HWI_E014+1)
|
||||
#define SKERR_HWI_E015MSG "Illegal Link mode parameter"
|
||||
#define SKERR_HWI_E016 (SKERR_HWI_E015+1)
|
||||
#define SKERR_HWI_E016MSG "Illegal Flow control mode parameter"
|
||||
#define SKERR_HWI_E017 (SKERR_HWI_E016+1)
|
||||
#define SKERR_HWI_E017MSG "Illegal value specified for GIPollTimerVal"
|
||||
#define SKERR_HWI_E018 (SKERR_HWI_E017+1)
|
||||
#define SKERR_HWI_E018MSG "FATAL: SkGeStopPort() does not terminate (Tx)"
|
||||
#define SKERR_HWI_E019 (SKERR_HWI_E018+1)
|
||||
#define SKERR_HWI_E019MSG "Illegal Speed parameter"
|
||||
#define SKERR_HWI_E020 (SKERR_HWI_E019+1)
|
||||
#define SKERR_HWI_E020MSG "Illegal Master/Slave parameter"
|
||||
#define SKERR_HWI_E021 (SKERR_HWI_E020+1)
|
||||
#define SKERR_HWI_E021MSG "MacUpdateStats(): cannot update statistic counter"
|
||||
#define SKERR_HWI_E022 (SKERR_HWI_E021+1)
|
||||
#define SKERR_HWI_E022MSG "MacStatistic(): illegal statistic base address"
|
||||
#define SKERR_HWI_E023 (SKERR_HWI_E022+1)
|
||||
#define SKERR_HWI_E023MSG "SkGeInitPort(): Transmit Queue Size too small"
|
||||
#define SKERR_HWI_E024 (SKERR_HWI_E023+1)
|
||||
#define SKERR_HWI_E024MSG "FATAL: SkGeStopPort() does not terminate (Rx)"
|
||||
#define SKERR_HWI_E025 (SKERR_HWI_E024+1)
|
||||
#define SKERR_HWI_E025MSG ""
|
||||
|
||||
/* function prototypes ********************************************************/
|
||||
|
||||
#ifndef SK_KR_PROTO
|
||||
|
||||
/*
|
||||
* public functions in skgeinit.c
|
||||
*/
|
||||
extern void SkGePollTxD(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Port,
|
||||
SK_BOOL PollTxD);
|
||||
|
||||
extern void SkGeYellowLED(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int State);
|
||||
|
||||
extern int SkGeCfgSync(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Port,
|
||||
SK_U32 IntTime,
|
||||
SK_U32 LimCount,
|
||||
int SyncMode);
|
||||
|
||||
extern void SkGeLoadLnkSyncCnt(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Port,
|
||||
SK_U32 CntVal);
|
||||
|
||||
extern void SkGeStopPort(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Port,
|
||||
int Dir,
|
||||
int RstMode);
|
||||
|
||||
extern int SkGeInit(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Level);
|
||||
|
||||
extern void SkGeDeInit(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC);
|
||||
|
||||
extern int SkGeInitPort(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Port);
|
||||
|
||||
extern void SkGeXmitLED(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Led,
|
||||
int Mode);
|
||||
|
||||
extern int SkGeInitAssignRamToQueues(
|
||||
SK_AC *pAC,
|
||||
int ActivePort,
|
||||
SK_BOOL DualNet);
|
||||
|
||||
/*
|
||||
* public functions in skxmac2.c
|
||||
*/
|
||||
extern void SkMacRxTxDisable(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Port);
|
||||
|
||||
extern void SkMacSoftRst(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Port);
|
||||
|
||||
extern void SkMacHardRst(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Port);
|
||||
|
||||
extern void SkXmInitMac(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Port);
|
||||
|
||||
extern void SkGmInitMac(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Port);
|
||||
|
||||
extern void SkMacInitPhy(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Port,
|
||||
SK_BOOL DoLoop);
|
||||
|
||||
extern void SkMacIrqDisable(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Port);
|
||||
|
||||
extern void SkMacFlushTxFifo(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Port);
|
||||
|
||||
extern void SkMacIrq(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Port);
|
||||
|
||||
extern int SkMacAutoNegDone(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Port);
|
||||
|
||||
extern void SkMacAutoNegLipaPhy(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Port,
|
||||
SK_U16 IStatus);
|
||||
|
||||
extern int SkMacRxTxEnable(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Port);
|
||||
|
||||
extern void SkMacPromiscMode(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Port,
|
||||
SK_BOOL Enable);
|
||||
|
||||
extern void SkMacHashing(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Port,
|
||||
SK_BOOL Enable);
|
||||
|
||||
extern void SkXmPhyRead(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Port,
|
||||
int Addr,
|
||||
SK_U16 SK_FAR *pVal);
|
||||
|
||||
extern void SkXmPhyWrite(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Port,
|
||||
int Addr,
|
||||
SK_U16 Val);
|
||||
|
||||
extern void SkGmPhyRead(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Port,
|
||||
int Addr,
|
||||
SK_U16 SK_FAR *pVal);
|
||||
|
||||
extern void SkGmPhyWrite(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Port,
|
||||
int Addr,
|
||||
SK_U16 Val);
|
||||
|
||||
extern void SkXmClrExactAddr(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Port,
|
||||
int StartNum,
|
||||
int StopNum);
|
||||
|
||||
extern void SkXmAutoNegLipaXmac(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Port,
|
||||
SK_U16 IStatus);
|
||||
|
||||
extern int SkXmUpdateStats(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
unsigned int Port);
|
||||
|
||||
extern int SkGmUpdateStats(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
unsigned int Port);
|
||||
|
||||
extern int SkXmMacStatistic(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
unsigned int Port,
|
||||
SK_U16 StatAddr,
|
||||
SK_U32 SK_FAR *pVal);
|
||||
|
||||
extern int SkGmMacStatistic(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
unsigned int Port,
|
||||
SK_U16 StatAddr,
|
||||
SK_U32 SK_FAR *pVal);
|
||||
|
||||
extern int SkXmResetCounter(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
unsigned int Port);
|
||||
|
||||
extern int SkGmResetCounter(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
unsigned int Port);
|
||||
|
||||
extern int SkXmOverflowStatus(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
unsigned int Port,
|
||||
SK_U16 IStatus,
|
||||
SK_U64 SK_FAR *pStatus);
|
||||
|
||||
extern int SkGmOverflowStatus(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
unsigned int Port,
|
||||
SK_U16 MacStatus,
|
||||
SK_U64 SK_FAR *pStatus);
|
||||
|
||||
extern int SkGmCableDiagStatus(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Port,
|
||||
SK_BOOL StartTest);
|
||||
|
||||
#ifdef SK_DIAG
|
||||
extern void SkGePhyRead(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Port,
|
||||
int Addr,
|
||||
SK_U16 *pVal);
|
||||
|
||||
extern void SkGePhyWrite(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Port,
|
||||
int Addr,
|
||||
SK_U16 Val);
|
||||
|
||||
extern void SkMacSetRxCmd(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Port,
|
||||
int Mode);
|
||||
extern void SkMacCrcGener(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Port,
|
||||
SK_BOOL Enable);
|
||||
extern void SkMacTimeStamp(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Port,
|
||||
SK_BOOL Enable);
|
||||
extern void SkXmSendCont(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Port,
|
||||
SK_BOOL Enable);
|
||||
#endif /* SK_DIAG */
|
||||
|
||||
#else /* SK_KR_PROTO */
|
||||
|
||||
/*
|
||||
* public functions in skgeinit.c
|
||||
*/
|
||||
extern void SkGePollTxD();
|
||||
extern void SkGeYellowLED();
|
||||
extern int SkGeCfgSync();
|
||||
extern void SkGeLoadLnkSyncCnt();
|
||||
extern void SkGeStopPort();
|
||||
extern int SkGeInit();
|
||||
extern void SkGeDeInit();
|
||||
extern int SkGeInitPort();
|
||||
extern void SkGeXmitLED();
|
||||
extern int SkGeInitAssignRamToQueues();
|
||||
|
||||
/*
|
||||
* public functions in skxmac2.c
|
||||
*/
|
||||
extern void SkMacRxTxDisable();
|
||||
extern void SkMacSoftRst();
|
||||
extern void SkMacHardRst();
|
||||
extern void SkMacInitPhy();
|
||||
extern int SkMacRxTxEnable();
|
||||
extern void SkMacPromiscMode();
|
||||
extern void SkMacHashing();
|
||||
extern void SkMacIrqDisable();
|
||||
extern void SkMacFlushTxFifo();
|
||||
extern void SkMacIrq();
|
||||
extern int SkMacAutoNegDone();
|
||||
extern void SkMacAutoNegLipaPhy();
|
||||
extern void SkXmInitMac();
|
||||
extern void SkXmPhyRead();
|
||||
extern void SkXmPhyWrite();
|
||||
extern void SkGmInitMac();
|
||||
extern void SkGmPhyRead();
|
||||
extern void SkGmPhyWrite();
|
||||
extern void SkXmClrExactAddr();
|
||||
extern void SkXmAutoNegLipaXmac();
|
||||
extern int SkXmUpdateStats();
|
||||
extern int SkGmUpdateStats();
|
||||
extern int SkXmMacStatistic();
|
||||
extern int SkGmMacStatistic();
|
||||
extern int SkXmResetCounter();
|
||||
extern int SkGmResetCounter();
|
||||
extern int SkXmOverflowStatus();
|
||||
extern int SkGmOverflowStatus();
|
||||
extern int SkGmCableDiagStatus();
|
||||
|
||||
#ifdef SK_DIAG
|
||||
extern void SkGePhyRead();
|
||||
extern void SkGePhyWrite();
|
||||
extern void SkMacSetRxCmd();
|
||||
extern void SkMacCrcGener();
|
||||
extern void SkMacTimeStamp();
|
||||
extern void SkXmSendCont();
|
||||
#endif /* SK_DIAG */
|
||||
|
||||
#endif /* SK_KR_PROTO */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* __INC_SKGEINIT_H_ */
|
|
@ -1,334 +0,0 @@
|
|||
/*****************************************************************************
|
||||
*
|
||||
* Name: skgepnm2.h
|
||||
* Project: GEnesis, PCI Gigabit Ethernet Adapter
|
||||
* Version: $Revision: 1.36 $
|
||||
* Date: $Date: 2003/05/23 12:45:13 $
|
||||
* Purpose: Defines for Private Network Management Interface
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* (C)Copyright 1998-2002 SysKonnect GmbH.
|
||||
* (C)Copyright 2002-2003 Marvell.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* The information in this file is provided "AS IS" without warranty.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _SKGEPNM2_H_
|
||||
#define _SKGEPNM2_H_
|
||||
|
||||
/*
|
||||
* General definitions
|
||||
*/
|
||||
#define SK_PNMI_CHIPSET_XMAC 1 /* XMAC11800FP */
|
||||
#define SK_PNMI_CHIPSET_YUKON 2 /* YUKON */
|
||||
|
||||
#define SK_PNMI_BUS_PCI 1 /* PCI bus*/
|
||||
|
||||
/*
|
||||
* Actions
|
||||
*/
|
||||
#define SK_PNMI_ACT_IDLE 1
|
||||
#define SK_PNMI_ACT_RESET 2
|
||||
#define SK_PNMI_ACT_SELFTEST 3
|
||||
#define SK_PNMI_ACT_RESETCNT 4
|
||||
|
||||
/*
|
||||
* VPD releated defines
|
||||
*/
|
||||
|
||||
#define SK_PNMI_VPD_RW 1
|
||||
#define SK_PNMI_VPD_RO 2
|
||||
|
||||
#define SK_PNMI_VPD_OK 0
|
||||
#define SK_PNMI_VPD_NOTFOUND 1
|
||||
#define SK_PNMI_VPD_CUT 2
|
||||
#define SK_PNMI_VPD_TIMEOUT 3
|
||||
#define SK_PNMI_VPD_FULL 4
|
||||
#define SK_PNMI_VPD_NOWRITE 5
|
||||
#define SK_PNMI_VPD_FATAL 6
|
||||
|
||||
#define SK_PNMI_VPD_IGNORE 0
|
||||
#define SK_PNMI_VPD_CREATE 1
|
||||
#define SK_PNMI_VPD_DELETE 2
|
||||
|
||||
|
||||
/*
|
||||
* RLMT related defines
|
||||
*/
|
||||
#define SK_PNMI_DEF_RLMT_CHG_THRES 240 /* 4 changes per minute */
|
||||
|
||||
|
||||
/*
|
||||
* VCT internal status values
|
||||
*/
|
||||
#define SK_PNMI_VCT_PENDING 32
|
||||
#define SK_PNMI_VCT_TEST_DONE 64
|
||||
#define SK_PNMI_VCT_LINK 128
|
||||
|
||||
/*
|
||||
* Internal table definitions
|
||||
*/
|
||||
#define SK_PNMI_GET 0
|
||||
#define SK_PNMI_PRESET 1
|
||||
#define SK_PNMI_SET 2
|
||||
|
||||
#define SK_PNMI_RO 0
|
||||
#define SK_PNMI_RW 1
|
||||
#define SK_PNMI_WO 2
|
||||
|
||||
typedef struct s_OidTabEntry {
|
||||
SK_U32 Id;
|
||||
SK_U32 InstanceNo;
|
||||
unsigned int StructSize;
|
||||
unsigned int Offset;
|
||||
int Access;
|
||||
int (* Func)(SK_AC *pAc, SK_IOC pIo, int action,
|
||||
SK_U32 Id, char* pBuf, unsigned int* pLen,
|
||||
SK_U32 Instance, unsigned int TableIndex,
|
||||
SK_U32 NetNumber);
|
||||
SK_U16 Param;
|
||||
} SK_PNMI_TAB_ENTRY;
|
||||
|
||||
|
||||
/*
|
||||
* Trap lengths
|
||||
*/
|
||||
#define SK_PNMI_TRAP_SIMPLE_LEN 17
|
||||
#define SK_PNMI_TRAP_SENSOR_LEN_BASE 46
|
||||
#define SK_PNMI_TRAP_RLMT_CHANGE_LEN 23
|
||||
#define SK_PNMI_TRAP_RLMT_PORT_LEN 23
|
||||
|
||||
/*
|
||||
* Number of MAC types supported
|
||||
*/
|
||||
#define SK_PNMI_MAC_TYPES (SK_MAC_GMAC + 1)
|
||||
|
||||
/*
|
||||
* MAC statistic data list (overall set for MAC types used)
|
||||
*/
|
||||
enum SK_MACSTATS {
|
||||
SK_PNMI_HTX = 0,
|
||||
SK_PNMI_HTX_OCTET,
|
||||
SK_PNMI_HTX_OCTETHIGH = SK_PNMI_HTX_OCTET,
|
||||
SK_PNMI_HTX_OCTETLOW,
|
||||
SK_PNMI_HTX_BROADCAST,
|
||||
SK_PNMI_HTX_MULTICAST,
|
||||
SK_PNMI_HTX_UNICAST,
|
||||
SK_PNMI_HTX_BURST,
|
||||
SK_PNMI_HTX_PMACC,
|
||||
SK_PNMI_HTX_MACC,
|
||||
SK_PNMI_HTX_COL,
|
||||
SK_PNMI_HTX_SINGLE_COL,
|
||||
SK_PNMI_HTX_MULTI_COL,
|
||||
SK_PNMI_HTX_EXCESS_COL,
|
||||
SK_PNMI_HTX_LATE_COL,
|
||||
SK_PNMI_HTX_DEFFERAL,
|
||||
SK_PNMI_HTX_EXCESS_DEF,
|
||||
SK_PNMI_HTX_UNDERRUN,
|
||||
SK_PNMI_HTX_CARRIER,
|
||||
SK_PNMI_HTX_UTILUNDER,
|
||||
SK_PNMI_HTX_UTILOVER,
|
||||
SK_PNMI_HTX_64,
|
||||
SK_PNMI_HTX_127,
|
||||
SK_PNMI_HTX_255,
|
||||
SK_PNMI_HTX_511,
|
||||
SK_PNMI_HTX_1023,
|
||||
SK_PNMI_HTX_MAX,
|
||||
SK_PNMI_HTX_LONGFRAMES,
|
||||
SK_PNMI_HTX_SYNC,
|
||||
SK_PNMI_HTX_SYNC_OCTET,
|
||||
SK_PNMI_HTX_RESERVED,
|
||||
|
||||
SK_PNMI_HRX,
|
||||
SK_PNMI_HRX_OCTET,
|
||||
SK_PNMI_HRX_OCTETHIGH = SK_PNMI_HRX_OCTET,
|
||||
SK_PNMI_HRX_OCTETLOW,
|
||||
SK_PNMI_HRX_BADOCTET,
|
||||
SK_PNMI_HRX_BADOCTETHIGH = SK_PNMI_HRX_BADOCTET,
|
||||
SK_PNMI_HRX_BADOCTETLOW,
|
||||
SK_PNMI_HRX_BROADCAST,
|
||||
SK_PNMI_HRX_MULTICAST,
|
||||
SK_PNMI_HRX_UNICAST,
|
||||
SK_PNMI_HRX_PMACC,
|
||||
SK_PNMI_HRX_MACC,
|
||||
SK_PNMI_HRX_PMACC_ERR,
|
||||
SK_PNMI_HRX_MACC_UNKWN,
|
||||
SK_PNMI_HRX_BURST,
|
||||
SK_PNMI_HRX_MISSED,
|
||||
SK_PNMI_HRX_FRAMING,
|
||||
SK_PNMI_HRX_UNDERSIZE,
|
||||
SK_PNMI_HRX_OVERFLOW,
|
||||
SK_PNMI_HRX_JABBER,
|
||||
SK_PNMI_HRX_CARRIER,
|
||||
SK_PNMI_HRX_IRLENGTH,
|
||||
SK_PNMI_HRX_SYMBOL,
|
||||
SK_PNMI_HRX_SHORTS,
|
||||
SK_PNMI_HRX_RUNT,
|
||||
SK_PNMI_HRX_TOO_LONG,
|
||||
SK_PNMI_HRX_FCS,
|
||||
SK_PNMI_HRX_CEXT,
|
||||
SK_PNMI_HRX_UTILUNDER,
|
||||
SK_PNMI_HRX_UTILOVER,
|
||||
SK_PNMI_HRX_64,
|
||||
SK_PNMI_HRX_127,
|
||||
SK_PNMI_HRX_255,
|
||||
SK_PNMI_HRX_511,
|
||||
SK_PNMI_HRX_1023,
|
||||
SK_PNMI_HRX_MAX,
|
||||
SK_PNMI_HRX_LONGFRAMES,
|
||||
|
||||
SK_PNMI_HRX_RESERVED,
|
||||
|
||||
SK_PNMI_MAX_IDX /* NOTE: Ensure SK_PNMI_CNT_NO is set to this value */
|
||||
};
|
||||
|
||||
/*
|
||||
* MAC specific data
|
||||
*/
|
||||
typedef struct s_PnmiStatAddr {
|
||||
SK_U16 Reg; /* MAC register containing the value */
|
||||
SK_BOOL GetOffset; /* TRUE: Offset managed by PNMI (call GetStatVal())*/
|
||||
} SK_PNMI_STATADDR;
|
||||
|
||||
|
||||
/*
|
||||
* SK_PNMI_STRUCT_DATA copy offset evaluation macros
|
||||
*/
|
||||
#define SK_PNMI_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_STRUCT_DATA *)0)->e))
|
||||
#define SK_PNMI_MAI_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_STRUCT_DATA *)0)->e))
|
||||
#define SK_PNMI_VPD_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_VPD *)0)->e))
|
||||
#define SK_PNMI_SEN_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_SENSOR *)0)->e))
|
||||
#define SK_PNMI_CHK_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_CHECKSUM *)0)->e))
|
||||
#define SK_PNMI_STA_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_STAT *)0)->e))
|
||||
#define SK_PNMI_CNF_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_CONF *)0)->e))
|
||||
#define SK_PNMI_RLM_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_RLMT *)0)->e))
|
||||
#define SK_PNMI_MON_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_RLMT_MONITOR *)0)->e))
|
||||
#define SK_PNMI_TRP_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_TRAP *)0)->e))
|
||||
|
||||
#define SK_PNMI_SET_STAT(b,s,o) {SK_U32 Val32; char *pVal; \
|
||||
Val32 = (s); \
|
||||
pVal = (char *)(b) + ((SK_U32)(SK_UPTR) \
|
||||
&(((SK_PNMI_STRUCT_DATA *)0)-> \
|
||||
ReturnStatus.ErrorStatus)); \
|
||||
SK_PNMI_STORE_U32(pVal, Val32); \
|
||||
Val32 = (o); \
|
||||
pVal = (char *)(b) + ((SK_U32)(SK_UPTR) \
|
||||
&(((SK_PNMI_STRUCT_DATA *)0)-> \
|
||||
ReturnStatus.ErrorOffset)); \
|
||||
SK_PNMI_STORE_U32(pVal, Val32);}
|
||||
|
||||
/*
|
||||
* Time macros
|
||||
*/
|
||||
#ifndef SK_PNMI_HUNDREDS_SEC
|
||||
#if SK_TICKS_PER_SEC == 100
|
||||
#define SK_PNMI_HUNDREDS_SEC(t) (t)
|
||||
#else
|
||||
#define SK_PNMI_HUNDREDS_SEC(t) (((t) * 100) / (SK_TICKS_PER_SEC))
|
||||
#endif /* !SK_TICKS_PER_SEC */
|
||||
#endif /* !SK_PNMI_HUNDREDS_SEC */
|
||||
|
||||
/*
|
||||
* Macros to work around alignment problems
|
||||
*/
|
||||
#ifndef SK_PNMI_STORE_U16
|
||||
#define SK_PNMI_STORE_U16(p,v) {*(char *)(p) = *((char *)&(v)); \
|
||||
*((char *)(p) + 1) = \
|
||||
*(((char *)&(v)) + 1);}
|
||||
#endif
|
||||
|
||||
#ifndef SK_PNMI_STORE_U32
|
||||
#define SK_PNMI_STORE_U32(p,v) {*(char *)(p) = *((char *)&(v)); \
|
||||
*((char *)(p) + 1) = \
|
||||
*(((char *)&(v)) + 1); \
|
||||
*((char *)(p) + 2) = \
|
||||
*(((char *)&(v)) + 2); \
|
||||
*((char *)(p) + 3) = \
|
||||
*(((char *)&(v)) + 3);}
|
||||
#endif
|
||||
|
||||
#ifndef SK_PNMI_STORE_U64
|
||||
#define SK_PNMI_STORE_U64(p,v) {*(char *)(p) = *((char *)&(v)); \
|
||||
*((char *)(p) + 1) = \
|
||||
*(((char *)&(v)) + 1); \
|
||||
*((char *)(p) + 2) = \
|
||||
*(((char *)&(v)) + 2); \
|
||||
*((char *)(p) + 3) = \
|
||||
*(((char *)&(v)) + 3); \
|
||||
*((char *)(p) + 4) = \
|
||||
*(((char *)&(v)) + 4); \
|
||||
*((char *)(p) + 5) = \
|
||||
*(((char *)&(v)) + 5); \
|
||||
*((char *)(p) + 6) = \
|
||||
*(((char *)&(v)) + 6); \
|
||||
*((char *)(p) + 7) = \
|
||||
*(((char *)&(v)) + 7);}
|
||||
#endif
|
||||
|
||||
#ifndef SK_PNMI_READ_U16
|
||||
#define SK_PNMI_READ_U16(p,v) {*((char *)&(v)) = *(char *)(p); \
|
||||
*(((char *)&(v)) + 1) = \
|
||||
*((char *)(p) + 1);}
|
||||
#endif
|
||||
|
||||
#ifndef SK_PNMI_READ_U32
|
||||
#define SK_PNMI_READ_U32(p,v) {*((char *)&(v)) = *(char *)(p); \
|
||||
*(((char *)&(v)) + 1) = \
|
||||
*((char *)(p) + 1); \
|
||||
*(((char *)&(v)) + 2) = \
|
||||
*((char *)(p) + 2); \
|
||||
*(((char *)&(v)) + 3) = \
|
||||
*((char *)(p) + 3);}
|
||||
#endif
|
||||
|
||||
#ifndef SK_PNMI_READ_U64
|
||||
#define SK_PNMI_READ_U64(p,v) {*((char *)&(v)) = *(char *)(p); \
|
||||
*(((char *)&(v)) + 1) = \
|
||||
*((char *)(p) + 1); \
|
||||
*(((char *)&(v)) + 2) = \
|
||||
*((char *)(p) + 2); \
|
||||
*(((char *)&(v)) + 3) = \
|
||||
*((char *)(p) + 3); \
|
||||
*(((char *)&(v)) + 4) = \
|
||||
*((char *)(p) + 4); \
|
||||
*(((char *)&(v)) + 5) = \
|
||||
*((char *)(p) + 5); \
|
||||
*(((char *)&(v)) + 6) = \
|
||||
*((char *)(p) + 6); \
|
||||
*(((char *)&(v)) + 7) = \
|
||||
*((char *)(p) + 7);}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Macros for Debug
|
||||
*/
|
||||
#ifdef DEBUG
|
||||
|
||||
#define SK_PNMI_CHECKFLAGS(vSt) {if (pAC->Pnmi.MacUpdatedFlag > 0 || \
|
||||
pAC->Pnmi.RlmtUpdatedFlag > 0 || \
|
||||
pAC->Pnmi.SirqUpdatedFlag > 0) { \
|
||||
SK_DBG_MSG(pAC, \
|
||||
SK_DBGMOD_PNMI, \
|
||||
SK_DBGCAT_CTRL, \
|
||||
("PNMI: ERR: %s MacUFlag=%d, RlmtUFlag=%d, SirqUFlag=%d\n", \
|
||||
vSt, \
|
||||
pAC->Pnmi.MacUpdatedFlag, \
|
||||
pAC->Pnmi.RlmtUpdatedFlag, \
|
||||
pAC->Pnmi.SirqUpdatedFlag))}}
|
||||
|
||||
#else /* !DEBUG */
|
||||
|
||||
#define SK_PNMI_CHECKFLAGS(vSt) /* Nothing */
|
||||
|
||||
#endif /* !DEBUG */
|
||||
|
||||
#endif /* _SKGEPNM2_H_ */
|
|
@ -1,962 +0,0 @@
|
|||
/*****************************************************************************
|
||||
*
|
||||
* Name: skgepnmi.h
|
||||
* Project: GEnesis, PCI Gigabit Ethernet Adapter
|
||||
* Version: $Revision: 1.62 $
|
||||
* Date: $Date: 2003/08/15 12:31:52 $
|
||||
* Purpose: Defines for Private Network Management Interface
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* (C)Copyright 1998-2002 SysKonnect GmbH.
|
||||
* (C)Copyright 2002-2003 Marvell.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* The information in this file is provided "AS IS" without warranty.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _SKGEPNMI_H_
|
||||
#define _SKGEPNMI_H_
|
||||
|
||||
/*
|
||||
* Include dependencies
|
||||
*/
|
||||
#include "h/sktypes.h"
|
||||
#include "h/skerror.h"
|
||||
#include "h/sktimer.h"
|
||||
#include "h/ski2c.h"
|
||||
#include "h/skaddr.h"
|
||||
#include "h/skrlmt.h"
|
||||
#include "h/skvpd.h"
|
||||
|
||||
/*
|
||||
* Management Database Version
|
||||
*/
|
||||
#define SK_PNMI_MDB_VERSION 0x00030001 /* 3.1 */
|
||||
|
||||
|
||||
/*
|
||||
* Event definitions
|
||||
*/
|
||||
#define SK_PNMI_EVT_SIRQ_OVERFLOW 1 /* Counter overflow */
|
||||
#define SK_PNMI_EVT_SEN_WAR_LOW 2 /* Lower war thres exceeded */
|
||||
#define SK_PNMI_EVT_SEN_WAR_UPP 3 /* Upper war thres exceeded */
|
||||
#define SK_PNMI_EVT_SEN_ERR_LOW 4 /* Lower err thres exceeded */
|
||||
#define SK_PNMI_EVT_SEN_ERR_UPP 5 /* Upper err thres exceeded */
|
||||
#define SK_PNMI_EVT_CHG_EST_TIMER 6 /* Timer event for RLMT Chg */
|
||||
#define SK_PNMI_EVT_UTILIZATION_TIMER 7 /* Timer event for Utiliza. */
|
||||
#define SK_PNMI_EVT_CLEAR_COUNTER 8 /* Clear statistic counters */
|
||||
#define SK_PNMI_EVT_XMAC_RESET 9 /* XMAC will be reset */
|
||||
|
||||
#define SK_PNMI_EVT_RLMT_PORT_UP 10 /* Port came logically up */
|
||||
#define SK_PNMI_EVT_RLMT_PORT_DOWN 11 /* Port went logically down */
|
||||
#define SK_PNMI_EVT_RLMT_SEGMENTATION 13 /* Two SP root bridges found */
|
||||
#define SK_PNMI_EVT_RLMT_ACTIVE_DOWN 14 /* Port went logically down */
|
||||
#define SK_PNMI_EVT_RLMT_ACTIVE_UP 15 /* Port came logically up */
|
||||
#define SK_PNMI_EVT_RLMT_SET_NETS 16 /* 1. Parameter is number of nets
|
||||
1 = single net; 2 = dual net */
|
||||
#define SK_PNMI_EVT_VCT_RESET 17 /* VCT port reset timer event started with SET. */
|
||||
|
||||
|
||||
/*
|
||||
* Return values
|
||||
*/
|
||||
#define SK_PNMI_ERR_OK 0
|
||||
#define SK_PNMI_ERR_GENERAL 1
|
||||
#define SK_PNMI_ERR_TOO_SHORT 2
|
||||
#define SK_PNMI_ERR_BAD_VALUE 3
|
||||
#define SK_PNMI_ERR_READ_ONLY 4
|
||||
#define SK_PNMI_ERR_UNKNOWN_OID 5
|
||||
#define SK_PNMI_ERR_UNKNOWN_INST 6
|
||||
#define SK_PNMI_ERR_UNKNOWN_NET 7
|
||||
#define SK_PNMI_ERR_NOT_SUPPORTED 10
|
||||
|
||||
|
||||
/*
|
||||
* Return values of driver reset function SK_DRIVER_RESET() and
|
||||
* driver event function SK_DRIVER_EVENT()
|
||||
*/
|
||||
#define SK_PNMI_ERR_OK 0
|
||||
#define SK_PNMI_ERR_FAIL 1
|
||||
|
||||
|
||||
/*
|
||||
* Return values of driver test function SK_DRIVER_SELFTEST()
|
||||
*/
|
||||
#define SK_PNMI_TST_UNKNOWN (1 << 0)
|
||||
#define SK_PNMI_TST_TRANCEIVER (1 << 1)
|
||||
#define SK_PNMI_TST_ASIC (1 << 2)
|
||||
#define SK_PNMI_TST_SENSOR (1 << 3)
|
||||
#define SK_PNMI_TST_POWERMGMT (1 << 4)
|
||||
#define SK_PNMI_TST_PCI (1 << 5)
|
||||
#define SK_PNMI_TST_MAC (1 << 6)
|
||||
|
||||
|
||||
/*
|
||||
* RLMT specific definitions
|
||||
*/
|
||||
#define SK_PNMI_RLMT_STATUS_STANDBY 1
|
||||
#define SK_PNMI_RLMT_STATUS_ACTIVE 2
|
||||
#define SK_PNMI_RLMT_STATUS_ERROR 3
|
||||
|
||||
#define SK_PNMI_RLMT_LSTAT_PHY_DOWN 1
|
||||
#define SK_PNMI_RLMT_LSTAT_AUTONEG 2
|
||||
#define SK_PNMI_RLMT_LSTAT_LOG_DOWN 3
|
||||
#define SK_PNMI_RLMT_LSTAT_LOG_UP 4
|
||||
#define SK_PNMI_RLMT_LSTAT_INDETERMINATED 5
|
||||
|
||||
#define SK_PNMI_RLMT_MODE_CHK_LINK (SK_RLMT_CHECK_LINK)
|
||||
#define SK_PNMI_RLMT_MODE_CHK_RX (SK_RLMT_CHECK_LOC_LINK)
|
||||
#define SK_PNMI_RLMT_MODE_CHK_SPT (SK_RLMT_CHECK_SEG)
|
||||
/* #define SK_PNMI_RLMT_MODE_CHK_EX */
|
||||
|
||||
/*
|
||||
* OID definition
|
||||
*/
|
||||
#ifndef _NDIS_ /* Check, whether NDIS already included OIDs */
|
||||
|
||||
#define OID_GEN_XMIT_OK 0x00020101
|
||||
#define OID_GEN_RCV_OK 0x00020102
|
||||
#define OID_GEN_XMIT_ERROR 0x00020103
|
||||
#define OID_GEN_RCV_ERROR 0x00020104
|
||||
#define OID_GEN_RCV_NO_BUFFER 0x00020105
|
||||
|
||||
/* #define OID_GEN_DIRECTED_BYTES_XMIT 0x00020201 */
|
||||
#define OID_GEN_DIRECTED_FRAMES_XMIT 0x00020202
|
||||
/* #define OID_GEN_MULTICAST_BYTES_XMIT 0x00020203 */
|
||||
#define OID_GEN_MULTICAST_FRAMES_XMIT 0x00020204
|
||||
/* #define OID_GEN_BROADCAST_BYTES_XMIT 0x00020205 */
|
||||
#define OID_GEN_BROADCAST_FRAMES_XMIT 0x00020206
|
||||
/* #define OID_GEN_DIRECTED_BYTES_RCV 0x00020207 */
|
||||
#define OID_GEN_DIRECTED_FRAMES_RCV 0x00020208
|
||||
/* #define OID_GEN_MULTICAST_BYTES_RCV 0x00020209 */
|
||||
#define OID_GEN_MULTICAST_FRAMES_RCV 0x0002020A
|
||||
/* #define OID_GEN_BROADCAST_BYTES_RCV 0x0002020B */
|
||||
#define OID_GEN_BROADCAST_FRAMES_RCV 0x0002020C
|
||||
#define OID_GEN_RCV_CRC_ERROR 0x0002020D
|
||||
#define OID_GEN_TRANSMIT_QUEUE_LENGTH 0x0002020E
|
||||
|
||||
#define OID_802_3_PERMANENT_ADDRESS 0x01010101
|
||||
#define OID_802_3_CURRENT_ADDRESS 0x01010102
|
||||
/* #define OID_802_3_MULTICAST_LIST 0x01010103 */
|
||||
/* #define OID_802_3_MAXIMUM_LIST_SIZE 0x01010104 */
|
||||
/* #define OID_802_3_MAC_OPTIONS 0x01010105 */
|
||||
|
||||
#define OID_802_3_RCV_ERROR_ALIGNMENT 0x01020101
|
||||
#define OID_802_3_XMIT_ONE_COLLISION 0x01020102
|
||||
#define OID_802_3_XMIT_MORE_COLLISIONS 0x01020103
|
||||
#define OID_802_3_XMIT_DEFERRED 0x01020201
|
||||
#define OID_802_3_XMIT_MAX_COLLISIONS 0x01020202
|
||||
#define OID_802_3_RCV_OVERRUN 0x01020203
|
||||
#define OID_802_3_XMIT_UNDERRUN 0x01020204
|
||||
#define OID_802_3_XMIT_TIMES_CRS_LOST 0x01020206
|
||||
#define OID_802_3_XMIT_LATE_COLLISIONS 0x01020207
|
||||
|
||||
/*
|
||||
* PnP and PM OIDs
|
||||
*/
|
||||
#ifdef SK_POWER_MGMT
|
||||
#define OID_PNP_CAPABILITIES 0xFD010100
|
||||
#define OID_PNP_SET_POWER 0xFD010101
|
||||
#define OID_PNP_QUERY_POWER 0xFD010102
|
||||
#define OID_PNP_ADD_WAKE_UP_PATTERN 0xFD010103
|
||||
#define OID_PNP_REMOVE_WAKE_UP_PATTERN 0xFD010104
|
||||
#define OID_PNP_ENABLE_WAKE_UP 0xFD010106
|
||||
#endif /* SK_POWER_MGMT */
|
||||
|
||||
#endif /* _NDIS_ */
|
||||
|
||||
#define OID_SKGE_MDB_VERSION 0xFF010100
|
||||
#define OID_SKGE_SUPPORTED_LIST 0xFF010101
|
||||
#define OID_SKGE_VPD_FREE_BYTES 0xFF010102
|
||||
#define OID_SKGE_VPD_ENTRIES_LIST 0xFF010103
|
||||
#define OID_SKGE_VPD_ENTRIES_NUMBER 0xFF010104
|
||||
#define OID_SKGE_VPD_KEY 0xFF010105
|
||||
#define OID_SKGE_VPD_VALUE 0xFF010106
|
||||
#define OID_SKGE_VPD_ACCESS 0xFF010107
|
||||
#define OID_SKGE_VPD_ACTION 0xFF010108
|
||||
|
||||
#define OID_SKGE_PORT_NUMBER 0xFF010110
|
||||
#define OID_SKGE_DEVICE_TYPE 0xFF010111
|
||||
#define OID_SKGE_DRIVER_DESCR 0xFF010112
|
||||
#define OID_SKGE_DRIVER_VERSION 0xFF010113
|
||||
#define OID_SKGE_HW_DESCR 0xFF010114
|
||||
#define OID_SKGE_HW_VERSION 0xFF010115
|
||||
#define OID_SKGE_CHIPSET 0xFF010116
|
||||
#define OID_SKGE_ACTION 0xFF010117
|
||||
#define OID_SKGE_RESULT 0xFF010118
|
||||
#define OID_SKGE_BUS_TYPE 0xFF010119
|
||||
#define OID_SKGE_BUS_SPEED 0xFF01011A
|
||||
#define OID_SKGE_BUS_WIDTH 0xFF01011B
|
||||
/* 0xFF01011C unused */
|
||||
#define OID_SKGE_DIAG_ACTION 0xFF01011D
|
||||
#define OID_SKGE_DIAG_RESULT 0xFF01011E
|
||||
#define OID_SKGE_MTU 0xFF01011F
|
||||
#define OID_SKGE_PHYS_CUR_ADDR 0xFF010120
|
||||
#define OID_SKGE_PHYS_FAC_ADDR 0xFF010121
|
||||
#define OID_SKGE_PMD 0xFF010122
|
||||
#define OID_SKGE_CONNECTOR 0xFF010123
|
||||
#define OID_SKGE_LINK_CAP 0xFF010124
|
||||
#define OID_SKGE_LINK_MODE 0xFF010125
|
||||
#define OID_SKGE_LINK_MODE_STATUS 0xFF010126
|
||||
#define OID_SKGE_LINK_STATUS 0xFF010127
|
||||
#define OID_SKGE_FLOWCTRL_CAP 0xFF010128
|
||||
#define OID_SKGE_FLOWCTRL_MODE 0xFF010129
|
||||
#define OID_SKGE_FLOWCTRL_STATUS 0xFF01012A
|
||||
#define OID_SKGE_PHY_OPERATION_CAP 0xFF01012B
|
||||
#define OID_SKGE_PHY_OPERATION_MODE 0xFF01012C
|
||||
#define OID_SKGE_PHY_OPERATION_STATUS 0xFF01012D
|
||||
#define OID_SKGE_MULTICAST_LIST 0xFF01012E
|
||||
#define OID_SKGE_CURRENT_PACKET_FILTER 0xFF01012F
|
||||
|
||||
#define OID_SKGE_TRAP 0xFF010130
|
||||
#define OID_SKGE_TRAP_NUMBER 0xFF010131
|
||||
|
||||
#define OID_SKGE_RLMT_MODE 0xFF010140
|
||||
#define OID_SKGE_RLMT_PORT_NUMBER 0xFF010141
|
||||
#define OID_SKGE_RLMT_PORT_ACTIVE 0xFF010142
|
||||
#define OID_SKGE_RLMT_PORT_PREFERRED 0xFF010143
|
||||
#define OID_SKGE_INTERMEDIATE_SUPPORT 0xFF010160
|
||||
|
||||
#define OID_SKGE_SPEED_CAP 0xFF010170
|
||||
#define OID_SKGE_SPEED_MODE 0xFF010171
|
||||
#define OID_SKGE_SPEED_STATUS 0xFF010172
|
||||
|
||||
#define OID_SKGE_BOARDLEVEL 0xFF010180
|
||||
|
||||
#define OID_SKGE_SENSOR_NUMBER 0xFF020100
|
||||
#define OID_SKGE_SENSOR_INDEX 0xFF020101
|
||||
#define OID_SKGE_SENSOR_DESCR 0xFF020102
|
||||
#define OID_SKGE_SENSOR_TYPE 0xFF020103
|
||||
#define OID_SKGE_SENSOR_VALUE 0xFF020104
|
||||
#define OID_SKGE_SENSOR_WAR_THRES_LOW 0xFF020105
|
||||
#define OID_SKGE_SENSOR_WAR_THRES_UPP 0xFF020106
|
||||
#define OID_SKGE_SENSOR_ERR_THRES_LOW 0xFF020107
|
||||
#define OID_SKGE_SENSOR_ERR_THRES_UPP 0xFF020108
|
||||
#define OID_SKGE_SENSOR_STATUS 0xFF020109
|
||||
#define OID_SKGE_SENSOR_WAR_CTS 0xFF02010A
|
||||
#define OID_SKGE_SENSOR_ERR_CTS 0xFF02010B
|
||||
#define OID_SKGE_SENSOR_WAR_TIME 0xFF02010C
|
||||
#define OID_SKGE_SENSOR_ERR_TIME 0xFF02010D
|
||||
|
||||
#define OID_SKGE_CHKSM_NUMBER 0xFF020110
|
||||
#define OID_SKGE_CHKSM_RX_OK_CTS 0xFF020111
|
||||
#define OID_SKGE_CHKSM_RX_UNABLE_CTS 0xFF020112
|
||||
#define OID_SKGE_CHKSM_RX_ERR_CTS 0xFF020113
|
||||
#define OID_SKGE_CHKSM_TX_OK_CTS 0xFF020114
|
||||
#define OID_SKGE_CHKSM_TX_UNABLE_CTS 0xFF020115
|
||||
|
||||
#define OID_SKGE_STAT_TX 0xFF020120
|
||||
#define OID_SKGE_STAT_TX_OCTETS 0xFF020121
|
||||
#define OID_SKGE_STAT_TX_BROADCAST 0xFF020122
|
||||
#define OID_SKGE_STAT_TX_MULTICAST 0xFF020123
|
||||
#define OID_SKGE_STAT_TX_UNICAST 0xFF020124
|
||||
#define OID_SKGE_STAT_TX_LONGFRAMES 0xFF020125
|
||||
#define OID_SKGE_STAT_TX_BURST 0xFF020126
|
||||
#define OID_SKGE_STAT_TX_PFLOWC 0xFF020127
|
||||
#define OID_SKGE_STAT_TX_FLOWC 0xFF020128
|
||||
#define OID_SKGE_STAT_TX_SINGLE_COL 0xFF020129
|
||||
#define OID_SKGE_STAT_TX_MULTI_COL 0xFF02012A
|
||||
#define OID_SKGE_STAT_TX_EXCESS_COL 0xFF02012B
|
||||
#define OID_SKGE_STAT_TX_LATE_COL 0xFF02012C
|
||||
#define OID_SKGE_STAT_TX_DEFFERAL 0xFF02012D
|
||||
#define OID_SKGE_STAT_TX_EXCESS_DEF 0xFF02012E
|
||||
#define OID_SKGE_STAT_TX_UNDERRUN 0xFF02012F
|
||||
#define OID_SKGE_STAT_TX_CARRIER 0xFF020130
|
||||
/* #define OID_SKGE_STAT_TX_UTIL 0xFF020131 */
|
||||
#define OID_SKGE_STAT_TX_64 0xFF020132
|
||||
#define OID_SKGE_STAT_TX_127 0xFF020133
|
||||
#define OID_SKGE_STAT_TX_255 0xFF020134
|
||||
#define OID_SKGE_STAT_TX_511 0xFF020135
|
||||
#define OID_SKGE_STAT_TX_1023 0xFF020136
|
||||
#define OID_SKGE_STAT_TX_MAX 0xFF020137
|
||||
#define OID_SKGE_STAT_TX_SYNC 0xFF020138
|
||||
#define OID_SKGE_STAT_TX_SYNC_OCTETS 0xFF020139
|
||||
#define OID_SKGE_STAT_RX 0xFF02013A
|
||||
#define OID_SKGE_STAT_RX_OCTETS 0xFF02013B
|
||||
#define OID_SKGE_STAT_RX_BROADCAST 0xFF02013C
|
||||
#define OID_SKGE_STAT_RX_MULTICAST 0xFF02013D
|
||||
#define OID_SKGE_STAT_RX_UNICAST 0xFF02013E
|
||||
#define OID_SKGE_STAT_RX_PFLOWC 0xFF02013F
|
||||
#define OID_SKGE_STAT_RX_FLOWC 0xFF020140
|
||||
#define OID_SKGE_STAT_RX_PFLOWC_ERR 0xFF020141
|
||||
#define OID_SKGE_STAT_RX_FLOWC_UNKWN 0xFF020142
|
||||
#define OID_SKGE_STAT_RX_BURST 0xFF020143
|
||||
#define OID_SKGE_STAT_RX_MISSED 0xFF020144
|
||||
#define OID_SKGE_STAT_RX_FRAMING 0xFF020145
|
||||
#define OID_SKGE_STAT_RX_OVERFLOW 0xFF020146
|
||||
#define OID_SKGE_STAT_RX_JABBER 0xFF020147
|
||||
#define OID_SKGE_STAT_RX_CARRIER 0xFF020148
|
||||
#define OID_SKGE_STAT_RX_IR_LENGTH 0xFF020149
|
||||
#define OID_SKGE_STAT_RX_SYMBOL 0xFF02014A
|
||||
#define OID_SKGE_STAT_RX_SHORTS 0xFF02014B
|
||||
#define OID_SKGE_STAT_RX_RUNT 0xFF02014C
|
||||
#define OID_SKGE_STAT_RX_CEXT 0xFF02014D
|
||||
#define OID_SKGE_STAT_RX_TOO_LONG 0xFF02014E
|
||||
#define OID_SKGE_STAT_RX_FCS 0xFF02014F
|
||||
/* #define OID_SKGE_STAT_RX_UTIL 0xFF020150 */
|
||||
#define OID_SKGE_STAT_RX_64 0xFF020151
|
||||
#define OID_SKGE_STAT_RX_127 0xFF020152
|
||||
#define OID_SKGE_STAT_RX_255 0xFF020153
|
||||
#define OID_SKGE_STAT_RX_511 0xFF020154
|
||||
#define OID_SKGE_STAT_RX_1023 0xFF020155
|
||||
#define OID_SKGE_STAT_RX_MAX 0xFF020156
|
||||
#define OID_SKGE_STAT_RX_LONGFRAMES 0xFF020157
|
||||
|
||||
#define OID_SKGE_RLMT_CHANGE_CTS 0xFF020160
|
||||
#define OID_SKGE_RLMT_CHANGE_TIME 0xFF020161
|
||||
#define OID_SKGE_RLMT_CHANGE_ESTIM 0xFF020162
|
||||
#define OID_SKGE_RLMT_CHANGE_THRES 0xFF020163
|
||||
|
||||
#define OID_SKGE_RLMT_PORT_INDEX 0xFF020164
|
||||
#define OID_SKGE_RLMT_STATUS 0xFF020165
|
||||
#define OID_SKGE_RLMT_TX_HELLO_CTS 0xFF020166
|
||||
#define OID_SKGE_RLMT_RX_HELLO_CTS 0xFF020167
|
||||
#define OID_SKGE_RLMT_TX_SP_REQ_CTS 0xFF020168
|
||||
#define OID_SKGE_RLMT_RX_SP_CTS 0xFF020169
|
||||
|
||||
#define OID_SKGE_RLMT_MONITOR_NUMBER 0xFF010150
|
||||
#define OID_SKGE_RLMT_MONITOR_INDEX 0xFF010151
|
||||
#define OID_SKGE_RLMT_MONITOR_ADDR 0xFF010152
|
||||
#define OID_SKGE_RLMT_MONITOR_ERRS 0xFF010153
|
||||
#define OID_SKGE_RLMT_MONITOR_TIMESTAMP 0xFF010154
|
||||
#define OID_SKGE_RLMT_MONITOR_ADMIN 0xFF010155
|
||||
|
||||
#define OID_SKGE_TX_SW_QUEUE_LEN 0xFF020170
|
||||
#define OID_SKGE_TX_SW_QUEUE_MAX 0xFF020171
|
||||
#define OID_SKGE_TX_RETRY 0xFF020172
|
||||
#define OID_SKGE_RX_INTR_CTS 0xFF020173
|
||||
#define OID_SKGE_TX_INTR_CTS 0xFF020174
|
||||
#define OID_SKGE_RX_NO_BUF_CTS 0xFF020175
|
||||
#define OID_SKGE_TX_NO_BUF_CTS 0xFF020176
|
||||
#define OID_SKGE_TX_USED_DESCR_NO 0xFF020177
|
||||
#define OID_SKGE_RX_DELIVERED_CTS 0xFF020178
|
||||
#define OID_SKGE_RX_OCTETS_DELIV_CTS 0xFF020179
|
||||
#define OID_SKGE_RX_HW_ERROR_CTS 0xFF02017A
|
||||
#define OID_SKGE_TX_HW_ERROR_CTS 0xFF02017B
|
||||
#define OID_SKGE_IN_ERRORS_CTS 0xFF02017C
|
||||
#define OID_SKGE_OUT_ERROR_CTS 0xFF02017D
|
||||
#define OID_SKGE_ERR_RECOVERY_CTS 0xFF02017E
|
||||
#define OID_SKGE_SYSUPTIME 0xFF02017F
|
||||
|
||||
#define OID_SKGE_ALL_DATA 0xFF020190
|
||||
|
||||
/* Defines for VCT. */
|
||||
#define OID_SKGE_VCT_GET 0xFF020200
|
||||
#define OID_SKGE_VCT_SET 0xFF020201
|
||||
#define OID_SKGE_VCT_STATUS 0xFF020202
|
||||
|
||||
#ifdef SK_DIAG_SUPPORT
|
||||
/* Defines for driver DIAG mode. */
|
||||
#define OID_SKGE_DIAG_MODE 0xFF020204
|
||||
#endif /* SK_DIAG_SUPPORT */
|
||||
|
||||
/* New OIDs */
|
||||
#define OID_SKGE_DRIVER_RELDATE 0xFF020210
|
||||
#define OID_SKGE_DRIVER_FILENAME 0xFF020211
|
||||
#define OID_SKGE_CHIPID 0xFF020212
|
||||
#define OID_SKGE_RAMSIZE 0xFF020213
|
||||
#define OID_SKGE_VAUXAVAIL 0xFF020214
|
||||
#define OID_SKGE_PHY_TYPE 0xFF020215
|
||||
#define OID_SKGE_PHY_LP_MODE 0xFF020216
|
||||
|
||||
/* VCT struct to store a backup copy of VCT data after a port reset. */
|
||||
typedef struct s_PnmiVct {
|
||||
SK_U8 VctStatus;
|
||||
SK_U8 PCableLen;
|
||||
SK_U32 PMdiPairLen[4];
|
||||
SK_U8 PMdiPairSts[4];
|
||||
} SK_PNMI_VCT;
|
||||
|
||||
|
||||
/* VCT status values (to be given to CPA via OID_SKGE_VCT_STATUS). */
|
||||
#define SK_PNMI_VCT_NONE 0
|
||||
#define SK_PNMI_VCT_OLD_VCT_DATA 1
|
||||
#define SK_PNMI_VCT_NEW_VCT_DATA 2
|
||||
#define SK_PNMI_VCT_OLD_DSP_DATA 4
|
||||
#define SK_PNMI_VCT_NEW_DSP_DATA 8
|
||||
#define SK_PNMI_VCT_RUNNING 16
|
||||
|
||||
|
||||
/* VCT cable test status. */
|
||||
#define SK_PNMI_VCT_NORMAL_CABLE 0
|
||||
#define SK_PNMI_VCT_SHORT_CABLE 1
|
||||
#define SK_PNMI_VCT_OPEN_CABLE 2
|
||||
#define SK_PNMI_VCT_TEST_FAIL 3
|
||||
#define SK_PNMI_VCT_IMPEDANCE_MISMATCH 4
|
||||
|
||||
#define OID_SKGE_TRAP_SEN_WAR_LOW 500
|
||||
#define OID_SKGE_TRAP_SEN_WAR_UPP 501
|
||||
#define OID_SKGE_TRAP_SEN_ERR_LOW 502
|
||||
#define OID_SKGE_TRAP_SEN_ERR_UPP 503
|
||||
#define OID_SKGE_TRAP_RLMT_CHANGE_THRES 520
|
||||
#define OID_SKGE_TRAP_RLMT_CHANGE_PORT 521
|
||||
#define OID_SKGE_TRAP_RLMT_PORT_DOWN 522
|
||||
#define OID_SKGE_TRAP_RLMT_PORT_UP 523
|
||||
#define OID_SKGE_TRAP_RLMT_SEGMENTATION 524
|
||||
|
||||
#ifdef SK_DIAG_SUPPORT
|
||||
/* Defines for driver DIAG mode. */
|
||||
#define SK_DIAG_ATTACHED 2
|
||||
#define SK_DIAG_RUNNING 1
|
||||
#define SK_DIAG_IDLE 0
|
||||
#endif /* SK_DIAG_SUPPORT */
|
||||
|
||||
/*
|
||||
* Generic PNMI IOCTL subcommand definitions.
|
||||
*/
|
||||
#define SK_GET_SINGLE_VAR 1
|
||||
#define SK_SET_SINGLE_VAR 2
|
||||
#define SK_PRESET_SINGLE_VAR 3
|
||||
#define SK_GET_FULL_MIB 4
|
||||
#define SK_SET_FULL_MIB 5
|
||||
#define SK_PRESET_FULL_MIB 6
|
||||
|
||||
|
||||
/*
|
||||
* Define error numbers and messages for syslog
|
||||
*/
|
||||
#define SK_PNMI_ERR001 (SK_ERRBASE_PNMI + 1)
|
||||
#define SK_PNMI_ERR001MSG "SkPnmiGetStruct: Unknown OID"
|
||||
#define SK_PNMI_ERR002 (SK_ERRBASE_PNMI + 2)
|
||||
#define SK_PNMI_ERR002MSG "SkPnmiGetStruct: Cannot read VPD keys"
|
||||
#define SK_PNMI_ERR003 (SK_ERRBASE_PNMI + 3)
|
||||
#define SK_PNMI_ERR003MSG "OidStruct: Called with wrong OID"
|
||||
#define SK_PNMI_ERR004 (SK_ERRBASE_PNMI + 4)
|
||||
#define SK_PNMI_ERR004MSG "OidStruct: Called with wrong action"
|
||||
#define SK_PNMI_ERR005 (SK_ERRBASE_PNMI + 5)
|
||||
#define SK_PNMI_ERR005MSG "Perform: Cannot reset driver"
|
||||
#define SK_PNMI_ERR006 (SK_ERRBASE_PNMI + 6)
|
||||
#define SK_PNMI_ERR006MSG "Perform: Unknown OID action command"
|
||||
#define SK_PNMI_ERR007 (SK_ERRBASE_PNMI + 7)
|
||||
#define SK_PNMI_ERR007MSG "General: Driver description not initialized"
|
||||
#define SK_PNMI_ERR008 (SK_ERRBASE_PNMI + 8)
|
||||
#define SK_PNMI_ERR008MSG "Addr: Tried to get unknown OID"
|
||||
#define SK_PNMI_ERR009 (SK_ERRBASE_PNMI + 9)
|
||||
#define SK_PNMI_ERR009MSG "Addr: Unknown OID"
|
||||
#define SK_PNMI_ERR010 (SK_ERRBASE_PNMI + 10)
|
||||
#define SK_PNMI_ERR010MSG "CsumStat: Unknown OID"
|
||||
#define SK_PNMI_ERR011 (SK_ERRBASE_PNMI + 11)
|
||||
#define SK_PNMI_ERR011MSG "SensorStat: Sensor descr string too long"
|
||||
#define SK_PNMI_ERR012 (SK_ERRBASE_PNMI + 12)
|
||||
#define SK_PNMI_ERR012MSG "SensorStat: Unknown OID"
|
||||
#define SK_PNMI_ERR013 (SK_ERRBASE_PNMI + 13)
|
||||
#define SK_PNMI_ERR013MSG ""
|
||||
#define SK_PNMI_ERR014 (SK_ERRBASE_PNMI + 14)
|
||||
#define SK_PNMI_ERR014MSG "Vpd: Cannot read VPD keys"
|
||||
#define SK_PNMI_ERR015 (SK_ERRBASE_PNMI + 15)
|
||||
#define SK_PNMI_ERR015MSG "Vpd: Internal array for VPD keys to small"
|
||||
#define SK_PNMI_ERR016 (SK_ERRBASE_PNMI + 16)
|
||||
#define SK_PNMI_ERR016MSG "Vpd: Key string too long"
|
||||
#define SK_PNMI_ERR017 (SK_ERRBASE_PNMI + 17)
|
||||
#define SK_PNMI_ERR017MSG "Vpd: Invalid VPD status pointer"
|
||||
#define SK_PNMI_ERR018 (SK_ERRBASE_PNMI + 18)
|
||||
#define SK_PNMI_ERR018MSG "Vpd: VPD data not valid"
|
||||
#define SK_PNMI_ERR019 (SK_ERRBASE_PNMI + 19)
|
||||
#define SK_PNMI_ERR019MSG "Vpd: VPD entries list string too long"
|
||||
#define SK_PNMI_ERR021 (SK_ERRBASE_PNMI + 21)
|
||||
#define SK_PNMI_ERR021MSG "Vpd: VPD data string too long"
|
||||
#define SK_PNMI_ERR022 (SK_ERRBASE_PNMI + 22)
|
||||
#define SK_PNMI_ERR022MSG "Vpd: VPD data string too long should be errored before"
|
||||
#define SK_PNMI_ERR023 (SK_ERRBASE_PNMI + 23)
|
||||
#define SK_PNMI_ERR023MSG "Vpd: Unknown OID in get action"
|
||||
#define SK_PNMI_ERR024 (SK_ERRBASE_PNMI + 24)
|
||||
#define SK_PNMI_ERR024MSG "Vpd: Unknown OID in preset/set action"
|
||||
#define SK_PNMI_ERR025 (SK_ERRBASE_PNMI + 25)
|
||||
#define SK_PNMI_ERR025MSG "Vpd: Cannot write VPD after modify entry"
|
||||
#define SK_PNMI_ERR026 (SK_ERRBASE_PNMI + 26)
|
||||
#define SK_PNMI_ERR026MSG "Vpd: Cannot update VPD"
|
||||
#define SK_PNMI_ERR027 (SK_ERRBASE_PNMI + 27)
|
||||
#define SK_PNMI_ERR027MSG "Vpd: Cannot delete VPD entry"
|
||||
#define SK_PNMI_ERR028 (SK_ERRBASE_PNMI + 28)
|
||||
#define SK_PNMI_ERR028MSG "Vpd: Cannot update VPD after delete entry"
|
||||
#define SK_PNMI_ERR029 (SK_ERRBASE_PNMI + 29)
|
||||
#define SK_PNMI_ERR029MSG "General: Driver description string too long"
|
||||
#define SK_PNMI_ERR030 (SK_ERRBASE_PNMI + 30)
|
||||
#define SK_PNMI_ERR030MSG "General: Driver version not initialized"
|
||||
#define SK_PNMI_ERR031 (SK_ERRBASE_PNMI + 31)
|
||||
#define SK_PNMI_ERR031MSG "General: Driver version string too long"
|
||||
#define SK_PNMI_ERR032 (SK_ERRBASE_PNMI + 32)
|
||||
#define SK_PNMI_ERR032MSG "General: Cannot read VPD Name for HW descr"
|
||||
#define SK_PNMI_ERR033 (SK_ERRBASE_PNMI + 33)
|
||||
#define SK_PNMI_ERR033MSG "General: HW description string too long"
|
||||
#define SK_PNMI_ERR034 (SK_ERRBASE_PNMI + 34)
|
||||
#define SK_PNMI_ERR034MSG "General: Unknown OID"
|
||||
#define SK_PNMI_ERR035 (SK_ERRBASE_PNMI + 35)
|
||||
#define SK_PNMI_ERR035MSG "Rlmt: Unknown OID"
|
||||
#define SK_PNMI_ERR036 (SK_ERRBASE_PNMI + 36)
|
||||
#define SK_PNMI_ERR036MSG ""
|
||||
#define SK_PNMI_ERR037 (SK_ERRBASE_PNMI + 37)
|
||||
#define SK_PNMI_ERR037MSG "Rlmt: SK_RLMT_MODE_CHANGE event return not 0"
|
||||
#define SK_PNMI_ERR038 (SK_ERRBASE_PNMI + 38)
|
||||
#define SK_PNMI_ERR038MSG "Rlmt: SK_RLMT_PREFPORT_CHANGE event return not 0"
|
||||
#define SK_PNMI_ERR039 (SK_ERRBASE_PNMI + 39)
|
||||
#define SK_PNMI_ERR039MSG "RlmtStat: Unknown OID"
|
||||
#define SK_PNMI_ERR040 (SK_ERRBASE_PNMI + 40)
|
||||
#define SK_PNMI_ERR040MSG "PowerManagement: Unknown OID"
|
||||
#define SK_PNMI_ERR041 (SK_ERRBASE_PNMI + 41)
|
||||
#define SK_PNMI_ERR041MSG "MacPrivateConf: Unknown OID"
|
||||
#define SK_PNMI_ERR042 (SK_ERRBASE_PNMI + 42)
|
||||
#define SK_PNMI_ERR042MSG "MacPrivateConf: SK_HWEV_SET_ROLE returned not 0"
|
||||
#define SK_PNMI_ERR043 (SK_ERRBASE_PNMI + 43)
|
||||
#define SK_PNMI_ERR043MSG "MacPrivateConf: SK_HWEV_SET_LMODE returned not 0"
|
||||
#define SK_PNMI_ERR044 (SK_ERRBASE_PNMI + 44)
|
||||
#define SK_PNMI_ERR044MSG "MacPrivateConf: SK_HWEV_SET_FLOWMODE returned not 0"
|
||||
#define SK_PNMI_ERR045 (SK_ERRBASE_PNMI + 45)
|
||||
#define SK_PNMI_ERR045MSG "MacPrivateConf: SK_HWEV_SET_SPEED returned not 0"
|
||||
#define SK_PNMI_ERR046 (SK_ERRBASE_PNMI + 46)
|
||||
#define SK_PNMI_ERR046MSG "Monitor: Unknown OID"
|
||||
#define SK_PNMI_ERR047 (SK_ERRBASE_PNMI + 47)
|
||||
#define SK_PNMI_ERR047MSG "SirqUpdate: Event function returns not 0"
|
||||
#define SK_PNMI_ERR048 (SK_ERRBASE_PNMI + 48)
|
||||
#define SK_PNMI_ERR048MSG "RlmtUpdate: Event function returns not 0"
|
||||
#define SK_PNMI_ERR049 (SK_ERRBASE_PNMI + 49)
|
||||
#define SK_PNMI_ERR049MSG "SkPnmiInit: Invalid size of 'CounterOffset' struct!!"
|
||||
#define SK_PNMI_ERR050 (SK_ERRBASE_PNMI + 50)
|
||||
#define SK_PNMI_ERR050MSG "SkPnmiInit: Invalid size of 'StatAddr' table!!"
|
||||
#define SK_PNMI_ERR051 (SK_ERRBASE_PNMI + 51)
|
||||
#define SK_PNMI_ERR051MSG "SkPnmiEvent: Port switch suspicious"
|
||||
#define SK_PNMI_ERR052 (SK_ERRBASE_PNMI + 52)
|
||||
#define SK_PNMI_ERR052MSG ""
|
||||
#define SK_PNMI_ERR053 (SK_ERRBASE_PNMI + 53)
|
||||
#define SK_PNMI_ERR053MSG "General: Driver release date not initialized"
|
||||
#define SK_PNMI_ERR054 (SK_ERRBASE_PNMI + 54)
|
||||
#define SK_PNMI_ERR054MSG "General: Driver release date string too long"
|
||||
#define SK_PNMI_ERR055 (SK_ERRBASE_PNMI + 55)
|
||||
#define SK_PNMI_ERR055MSG "General: Driver file name not initialized"
|
||||
#define SK_PNMI_ERR056 (SK_ERRBASE_PNMI + 56)
|
||||
#define SK_PNMI_ERR056MSG "General: Driver file name string too long"
|
||||
|
||||
/*
|
||||
* Management counter macros called by the driver
|
||||
*/
|
||||
#define SK_PNMI_SET_DRIVER_DESCR(pAC,v) ((pAC)->Pnmi.pDriverDescription = \
|
||||
(char *)(v))
|
||||
|
||||
#define SK_PNMI_SET_DRIVER_VER(pAC,v) ((pAC)->Pnmi.pDriverVersion = \
|
||||
(char *)(v))
|
||||
|
||||
#define SK_PNMI_SET_DRIVER_RELDATE(pAC,v) ((pAC)->Pnmi.pDriverReleaseDate = \
|
||||
(char *)(v))
|
||||
|
||||
#define SK_PNMI_SET_DRIVER_FILENAME(pAC,v) ((pAC)->Pnmi.pDriverFileName = \
|
||||
(char *)(v))
|
||||
|
||||
#define SK_PNMI_CNT_TX_QUEUE_LEN(pAC,v,p) \
|
||||
{ \
|
||||
(pAC)->Pnmi.Port[p].TxSwQueueLen = (SK_U64)(v); \
|
||||
if ((pAC)->Pnmi.Port[p].TxSwQueueLen > (pAC)->Pnmi.Port[p].TxSwQueueMax) { \
|
||||
(pAC)->Pnmi.Port[p].TxSwQueueMax = (pAC)->Pnmi.Port[p].TxSwQueueLen; \
|
||||
} \
|
||||
}
|
||||
#define SK_PNMI_CNT_TX_RETRY(pAC,p) (((pAC)->Pnmi.Port[p].TxRetryCts)++)
|
||||
#define SK_PNMI_CNT_RX_INTR(pAC,p) (((pAC)->Pnmi.Port[p].RxIntrCts)++)
|
||||
#define SK_PNMI_CNT_TX_INTR(pAC,p) (((pAC)->Pnmi.Port[p].TxIntrCts)++)
|
||||
#define SK_PNMI_CNT_NO_RX_BUF(pAC,p) (((pAC)->Pnmi.Port[p].RxNoBufCts)++)
|
||||
#define SK_PNMI_CNT_NO_TX_BUF(pAC,p) (((pAC)->Pnmi.Port[p].TxNoBufCts)++)
|
||||
#define SK_PNMI_CNT_USED_TX_DESCR(pAC,v,p) \
|
||||
((pAC)->Pnmi.Port[p].TxUsedDescrNo=(SK_U64)(v));
|
||||
#define SK_PNMI_CNT_RX_OCTETS_DELIVERED(pAC,v,p) \
|
||||
{ \
|
||||
((pAC)->Pnmi.Port[p].RxDeliveredCts)++; \
|
||||
(pAC)->Pnmi.Port[p].RxOctetsDeliveredCts += (SK_U64)(v); \
|
||||
}
|
||||
#define SK_PNMI_CNT_ERR_RECOVERY(pAC,p) (((pAC)->Pnmi.Port[p].ErrRecoveryCts)++);
|
||||
|
||||
#define SK_PNMI_CNT_SYNC_OCTETS(pAC,p,v) \
|
||||
{ \
|
||||
if ((p) < SK_MAX_MACS) { \
|
||||
((pAC)->Pnmi.Port[p].StatSyncCts)++; \
|
||||
(pAC)->Pnmi.Port[p].StatSyncOctetsCts += (SK_U64)(v); \
|
||||
} \
|
||||
}
|
||||
|
||||
#define SK_PNMI_CNT_RX_LONGFRAMES(pAC,p) \
|
||||
{ \
|
||||
if ((p) < SK_MAX_MACS) { \
|
||||
((pAC)->Pnmi.Port[p].StatRxLongFrameCts++); \
|
||||
} \
|
||||
}
|
||||
|
||||
#define SK_PNMI_CNT_RX_FRAMETOOLONG(pAC,p) \
|
||||
{ \
|
||||
if ((p) < SK_MAX_MACS) { \
|
||||
((pAC)->Pnmi.Port[p].StatRxFrameTooLongCts++); \
|
||||
} \
|
||||
}
|
||||
|
||||
#define SK_PNMI_CNT_RX_PMACC_ERR(pAC,p) \
|
||||
{ \
|
||||
if ((p) < SK_MAX_MACS) { \
|
||||
((pAC)->Pnmi.Port[p].StatRxPMaccErr++); \
|
||||
} \
|
||||
}
|
||||
|
||||
/*
|
||||
* Conversion Macros
|
||||
*/
|
||||
#define SK_PNMI_PORT_INST2LOG(i) ((unsigned int)(i) - 1)
|
||||
#define SK_PNMI_PORT_LOG2INST(l) ((unsigned int)(l) + 1)
|
||||
#define SK_PNMI_PORT_PHYS2LOG(p) ((unsigned int)(p) + 1)
|
||||
#define SK_PNMI_PORT_LOG2PHYS(pAC,l) ((unsigned int)(l) - 1)
|
||||
#define SK_PNMI_PORT_PHYS2INST(pAC,p) \
|
||||
(pAC->Pnmi.DualNetActiveFlag ? 2 : ((unsigned int)(p) + 2))
|
||||
#define SK_PNMI_PORT_INST2PHYS(pAC,i) ((unsigned int)(i) - 2)
|
||||
|
||||
/*
|
||||
* Structure definition for SkPnmiGetStruct and SkPnmiSetStruct
|
||||
*/
|
||||
#define SK_PNMI_VPD_KEY_SIZE 5
|
||||
#define SK_PNMI_VPD_BUFSIZE (VPD_SIZE)
|
||||
#define SK_PNMI_VPD_ENTRIES (VPD_SIZE / 4)
|
||||
#define SK_PNMI_VPD_DATALEN 128 /* Number of data bytes */
|
||||
|
||||
#define SK_PNMI_MULTICAST_LISTLEN 64
|
||||
#define SK_PNMI_SENSOR_ENTRIES (SK_MAX_SENSORS)
|
||||
#define SK_PNMI_CHECKSUM_ENTRIES 3
|
||||
#define SK_PNMI_MAC_ENTRIES (SK_MAX_MACS + 1)
|
||||
#define SK_PNMI_MONITOR_ENTRIES 20
|
||||
#define SK_PNMI_TRAP_ENTRIES 10
|
||||
#define SK_PNMI_TRAPLEN 128
|
||||
#define SK_PNMI_STRINGLEN1 80
|
||||
#define SK_PNMI_STRINGLEN2 25
|
||||
#define SK_PNMI_TRAP_QUEUE_LEN 512
|
||||
|
||||
typedef struct s_PnmiVpd {
|
||||
char VpdKey[SK_PNMI_VPD_KEY_SIZE];
|
||||
char VpdValue[SK_PNMI_VPD_DATALEN];
|
||||
SK_U8 VpdAccess;
|
||||
SK_U8 VpdAction;
|
||||
} SK_PNMI_VPD;
|
||||
|
||||
typedef struct s_PnmiSensor {
|
||||
SK_U8 SensorIndex;
|
||||
char SensorDescr[SK_PNMI_STRINGLEN2];
|
||||
SK_U8 SensorType;
|
||||
SK_U32 SensorValue;
|
||||
SK_U32 SensorWarningThresholdLow;
|
||||
SK_U32 SensorWarningThresholdHigh;
|
||||
SK_U32 SensorErrorThresholdLow;
|
||||
SK_U32 SensorErrorThresholdHigh;
|
||||
SK_U8 SensorStatus;
|
||||
SK_U64 SensorWarningCts;
|
||||
SK_U64 SensorErrorCts;
|
||||
SK_U64 SensorWarningTimestamp;
|
||||
SK_U64 SensorErrorTimestamp;
|
||||
} SK_PNMI_SENSOR;
|
||||
|
||||
typedef struct s_PnmiChecksum {
|
||||
SK_U64 ChecksumRxOkCts;
|
||||
SK_U64 ChecksumRxUnableCts;
|
||||
SK_U64 ChecksumRxErrCts;
|
||||
SK_U64 ChecksumTxOkCts;
|
||||
SK_U64 ChecksumTxUnableCts;
|
||||
} SK_PNMI_CHECKSUM;
|
||||
|
||||
typedef struct s_PnmiStat {
|
||||
SK_U64 StatTxOkCts;
|
||||
SK_U64 StatTxOctetsOkCts;
|
||||
SK_U64 StatTxBroadcastOkCts;
|
||||
SK_U64 StatTxMulticastOkCts;
|
||||
SK_U64 StatTxUnicastOkCts;
|
||||
SK_U64 StatTxLongFramesCts;
|
||||
SK_U64 StatTxBurstCts;
|
||||
SK_U64 StatTxPauseMacCtrlCts;
|
||||
SK_U64 StatTxMacCtrlCts;
|
||||
SK_U64 StatTxSingleCollisionCts;
|
||||
SK_U64 StatTxMultipleCollisionCts;
|
||||
SK_U64 StatTxExcessiveCollisionCts;
|
||||
SK_U64 StatTxLateCollisionCts;
|
||||
SK_U64 StatTxDeferralCts;
|
||||
SK_U64 StatTxExcessiveDeferralCts;
|
||||
SK_U64 StatTxFifoUnderrunCts;
|
||||
SK_U64 StatTxCarrierCts;
|
||||
SK_U64 Dummy1; /* StatTxUtilization */
|
||||
SK_U64 StatTx64Cts;
|
||||
SK_U64 StatTx127Cts;
|
||||
SK_U64 StatTx255Cts;
|
||||
SK_U64 StatTx511Cts;
|
||||
SK_U64 StatTx1023Cts;
|
||||
SK_U64 StatTxMaxCts;
|
||||
SK_U64 StatTxSyncCts;
|
||||
SK_U64 StatTxSyncOctetsCts;
|
||||
SK_U64 StatRxOkCts;
|
||||
SK_U64 StatRxOctetsOkCts;
|
||||
SK_U64 StatRxBroadcastOkCts;
|
||||
SK_U64 StatRxMulticastOkCts;
|
||||
SK_U64 StatRxUnicastOkCts;
|
||||
SK_U64 StatRxLongFramesCts;
|
||||
SK_U64 StatRxPauseMacCtrlCts;
|
||||
SK_U64 StatRxMacCtrlCts;
|
||||
SK_U64 StatRxPauseMacCtrlErrorCts;
|
||||
SK_U64 StatRxMacCtrlUnknownCts;
|
||||
SK_U64 StatRxBurstCts;
|
||||
SK_U64 StatRxMissedCts;
|
||||
SK_U64 StatRxFramingCts;
|
||||
SK_U64 StatRxFifoOverflowCts;
|
||||
SK_U64 StatRxJabberCts;
|
||||
SK_U64 StatRxCarrierCts;
|
||||
SK_U64 StatRxIRLengthCts;
|
||||
SK_U64 StatRxSymbolCts;
|
||||
SK_U64 StatRxShortsCts;
|
||||
SK_U64 StatRxRuntCts;
|
||||
SK_U64 StatRxCextCts;
|
||||
SK_U64 StatRxTooLongCts;
|
||||
SK_U64 StatRxFcsCts;
|
||||
SK_U64 Dummy2; /* StatRxUtilization */
|
||||
SK_U64 StatRx64Cts;
|
||||
SK_U64 StatRx127Cts;
|
||||
SK_U64 StatRx255Cts;
|
||||
SK_U64 StatRx511Cts;
|
||||
SK_U64 StatRx1023Cts;
|
||||
SK_U64 StatRxMaxCts;
|
||||
} SK_PNMI_STAT;
|
||||
|
||||
typedef struct s_PnmiConf {
|
||||
char ConfMacCurrentAddr[6];
|
||||
char ConfMacFactoryAddr[6];
|
||||
SK_U8 ConfPMD;
|
||||
SK_U8 ConfConnector;
|
||||
SK_U32 ConfPhyType;
|
||||
SK_U32 ConfPhyMode;
|
||||
SK_U8 ConfLinkCapability;
|
||||
SK_U8 ConfLinkMode;
|
||||
SK_U8 ConfLinkModeStatus;
|
||||
SK_U8 ConfLinkStatus;
|
||||
SK_U8 ConfFlowCtrlCapability;
|
||||
SK_U8 ConfFlowCtrlMode;
|
||||
SK_U8 ConfFlowCtrlStatus;
|
||||
SK_U8 ConfPhyOperationCapability;
|
||||
SK_U8 ConfPhyOperationMode;
|
||||
SK_U8 ConfPhyOperationStatus;
|
||||
SK_U8 ConfSpeedCapability;
|
||||
SK_U8 ConfSpeedMode;
|
||||
SK_U8 ConfSpeedStatus;
|
||||
} SK_PNMI_CONF;
|
||||
|
||||
typedef struct s_PnmiRlmt {
|
||||
SK_U32 RlmtIndex;
|
||||
SK_U32 RlmtStatus;
|
||||
SK_U64 RlmtTxHelloCts;
|
||||
SK_U64 RlmtRxHelloCts;
|
||||
SK_U64 RlmtTxSpHelloReqCts;
|
||||
SK_U64 RlmtRxSpHelloCts;
|
||||
} SK_PNMI_RLMT;
|
||||
|
||||
typedef struct s_PnmiRlmtMonitor {
|
||||
SK_U32 RlmtMonitorIndex;
|
||||
char RlmtMonitorAddr[6];
|
||||
SK_U64 RlmtMonitorErrorCts;
|
||||
SK_U64 RlmtMonitorTimestamp;
|
||||
SK_U8 RlmtMonitorAdmin;
|
||||
} SK_PNMI_RLMT_MONITOR;
|
||||
|
||||
typedef struct s_PnmiRequestStatus {
|
||||
SK_U32 ErrorStatus;
|
||||
SK_U32 ErrorOffset;
|
||||
} SK_PNMI_REQUEST_STATUS;
|
||||
|
||||
typedef struct s_PnmiStrucData {
|
||||
SK_U32 MgmtDBVersion;
|
||||
SK_PNMI_REQUEST_STATUS ReturnStatus;
|
||||
SK_U32 VpdFreeBytes;
|
||||
char VpdEntriesList[SK_PNMI_VPD_ENTRIES * SK_PNMI_VPD_KEY_SIZE];
|
||||
SK_U32 VpdEntriesNumber;
|
||||
SK_PNMI_VPD Vpd[SK_PNMI_VPD_ENTRIES];
|
||||
SK_U32 PortNumber;
|
||||
SK_U32 DeviceType;
|
||||
char DriverDescr[SK_PNMI_STRINGLEN1];
|
||||
char DriverVersion[SK_PNMI_STRINGLEN2];
|
||||
char DriverReleaseDate[SK_PNMI_STRINGLEN1];
|
||||
char DriverFileName[SK_PNMI_STRINGLEN1];
|
||||
char HwDescr[SK_PNMI_STRINGLEN1];
|
||||
char HwVersion[SK_PNMI_STRINGLEN2];
|
||||
SK_U16 Chipset;
|
||||
SK_U32 ChipId;
|
||||
SK_U8 VauxAvail;
|
||||
SK_U32 RamSize;
|
||||
SK_U32 MtuSize;
|
||||
SK_U32 Action;
|
||||
SK_U32 TestResult;
|
||||
SK_U8 BusType;
|
||||
SK_U8 BusSpeed;
|
||||
SK_U8 BusWidth;
|
||||
SK_U8 SensorNumber;
|
||||
SK_PNMI_SENSOR Sensor[SK_PNMI_SENSOR_ENTRIES];
|
||||
SK_U8 ChecksumNumber;
|
||||
SK_PNMI_CHECKSUM Checksum[SK_PNMI_CHECKSUM_ENTRIES];
|
||||
SK_PNMI_STAT Stat[SK_PNMI_MAC_ENTRIES];
|
||||
SK_PNMI_CONF Conf[SK_PNMI_MAC_ENTRIES];
|
||||
SK_U8 RlmtMode;
|
||||
SK_U32 RlmtPortNumber;
|
||||
SK_U8 RlmtPortActive;
|
||||
SK_U8 RlmtPortPreferred;
|
||||
SK_U64 RlmtChangeCts;
|
||||
SK_U64 RlmtChangeTime;
|
||||
SK_U64 RlmtChangeEstimate;
|
||||
SK_U64 RlmtChangeThreshold;
|
||||
SK_PNMI_RLMT Rlmt[SK_MAX_MACS];
|
||||
SK_U32 RlmtMonitorNumber;
|
||||
SK_PNMI_RLMT_MONITOR RlmtMonitor[SK_PNMI_MONITOR_ENTRIES];
|
||||
SK_U32 TrapNumber;
|
||||
SK_U8 Trap[SK_PNMI_TRAP_QUEUE_LEN];
|
||||
SK_U64 TxSwQueueLen;
|
||||
SK_U64 TxSwQueueMax;
|
||||
SK_U64 TxRetryCts;
|
||||
SK_U64 RxIntrCts;
|
||||
SK_U64 TxIntrCts;
|
||||
SK_U64 RxNoBufCts;
|
||||
SK_U64 TxNoBufCts;
|
||||
SK_U64 TxUsedDescrNo;
|
||||
SK_U64 RxDeliveredCts;
|
||||
SK_U64 RxOctetsDeliveredCts;
|
||||
SK_U64 RxHwErrorsCts;
|
||||
SK_U64 TxHwErrorsCts;
|
||||
SK_U64 InErrorsCts;
|
||||
SK_U64 OutErrorsCts;
|
||||
SK_U64 ErrRecoveryCts;
|
||||
SK_U64 SysUpTime;
|
||||
} SK_PNMI_STRUCT_DATA;
|
||||
|
||||
#define SK_PNMI_STRUCT_SIZE (sizeof(SK_PNMI_STRUCT_DATA))
|
||||
#define SK_PNMI_MIN_STRUCT_SIZE ((unsigned int)(SK_UPTR)\
|
||||
&(((SK_PNMI_STRUCT_DATA *)0)->VpdFreeBytes))
|
||||
/*
|
||||
* ReturnStatus field
|
||||
* must be located
|
||||
* before VpdFreeBytes
|
||||
*/
|
||||
|
||||
/*
|
||||
* Various definitions
|
||||
*/
|
||||
#define SK_PNMI_MAX_PROTOS 3
|
||||
|
||||
#define SK_PNMI_CNT_NO 66 /* Must have the value of the enum
|
||||
* SK_PNMI_MAX_IDX. Define SK_PNMI_CHECK
|
||||
* for check while init phase 1
|
||||
*/
|
||||
|
||||
/*
|
||||
* Estimate data structure
|
||||
*/
|
||||
typedef struct s_PnmiEstimate {
|
||||
unsigned int EstValueIndex;
|
||||
SK_U64 EstValue[7];
|
||||
SK_U64 Estimate;
|
||||
SK_TIMER EstTimer;
|
||||
} SK_PNMI_ESTIMATE;
|
||||
|
||||
|
||||
/*
|
||||
* VCT timer data structure
|
||||
*/
|
||||
typedef struct s_VctTimer {
|
||||
SK_TIMER VctTimer;
|
||||
} SK_PNMI_VCT_TIMER;
|
||||
|
||||
|
||||
/*
|
||||
* PNMI specific adapter context structure
|
||||
*/
|
||||
typedef struct s_PnmiPort {
|
||||
SK_U64 StatSyncCts;
|
||||
SK_U64 StatSyncOctetsCts;
|
||||
SK_U64 StatRxLongFrameCts;
|
||||
SK_U64 StatRxFrameTooLongCts;
|
||||
SK_U64 StatRxPMaccErr;
|
||||
SK_U64 TxSwQueueLen;
|
||||
SK_U64 TxSwQueueMax;
|
||||
SK_U64 TxRetryCts;
|
||||
SK_U64 RxIntrCts;
|
||||
SK_U64 TxIntrCts;
|
||||
SK_U64 RxNoBufCts;
|
||||
SK_U64 TxNoBufCts;
|
||||
SK_U64 TxUsedDescrNo;
|
||||
SK_U64 RxDeliveredCts;
|
||||
SK_U64 RxOctetsDeliveredCts;
|
||||
SK_U64 RxHwErrorsCts;
|
||||
SK_U64 TxHwErrorsCts;
|
||||
SK_U64 InErrorsCts;
|
||||
SK_U64 OutErrorsCts;
|
||||
SK_U64 ErrRecoveryCts;
|
||||
SK_U64 RxShortZeroMark;
|
||||
SK_U64 CounterOffset[SK_PNMI_CNT_NO];
|
||||
SK_U32 CounterHigh[SK_PNMI_CNT_NO];
|
||||
SK_BOOL ActiveFlag;
|
||||
SK_U8 Align[3];
|
||||
} SK_PNMI_PORT;
|
||||
|
||||
|
||||
typedef struct s_PnmiData {
|
||||
SK_PNMI_PORT Port [SK_MAX_MACS];
|
||||
SK_PNMI_PORT BufPort [SK_MAX_MACS]; /* 2002-09-13 pweber */
|
||||
SK_U64 VirtualCounterOffset[SK_PNMI_CNT_NO];
|
||||
SK_U32 TestResult;
|
||||
char HwVersion[10];
|
||||
SK_U16 Align01;
|
||||
|
||||
char *pDriverDescription;
|
||||
char *pDriverVersion;
|
||||
char *pDriverReleaseDate;
|
||||
char *pDriverFileName;
|
||||
|
||||
int MacUpdatedFlag;
|
||||
int RlmtUpdatedFlag;
|
||||
int SirqUpdatedFlag;
|
||||
|
||||
SK_U64 RlmtChangeCts;
|
||||
SK_U64 RlmtChangeTime;
|
||||
SK_PNMI_ESTIMATE RlmtChangeEstimate;
|
||||
SK_U64 RlmtChangeThreshold;
|
||||
|
||||
SK_U64 StartUpTime;
|
||||
SK_U32 DeviceType;
|
||||
char PciBusSpeed;
|
||||
char PciBusWidth;
|
||||
char Chipset;
|
||||
char PMD;
|
||||
char Connector;
|
||||
SK_BOOL DualNetActiveFlag;
|
||||
SK_U16 Align02;
|
||||
|
||||
char TrapBuf[SK_PNMI_TRAP_QUEUE_LEN];
|
||||
unsigned int TrapBufFree;
|
||||
unsigned int TrapQueueBeg;
|
||||
unsigned int TrapQueueEnd;
|
||||
unsigned int TrapBufPad;
|
||||
unsigned int TrapUnique;
|
||||
SK_U8 VctStatus[SK_MAX_MACS];
|
||||
SK_PNMI_VCT VctBackup[SK_MAX_MACS];
|
||||
SK_PNMI_VCT_TIMER VctTimeout[SK_MAX_MACS];
|
||||
#ifdef SK_DIAG_SUPPORT
|
||||
SK_U32 DiagAttached;
|
||||
#endif /* SK_DIAG_SUPPORT */
|
||||
} SK_PNMI;
|
||||
|
||||
|
||||
/*
|
||||
* Function prototypes
|
||||
*/
|
||||
extern int SkPnmiInit(SK_AC *pAC, SK_IOC IoC, int Level);
|
||||
extern int SkPnmiSetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void* pBuf,
|
||||
unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex);
|
||||
extern int SkPnmiGetStruct(SK_AC *pAC, SK_IOC IoC, void* pBuf,
|
||||
unsigned int *pLen, SK_U32 NetIndex);
|
||||
extern int SkPnmiPreSetStruct(SK_AC *pAC, SK_IOC IoC, void* pBuf,
|
||||
unsigned int *pLen, SK_U32 NetIndex);
|
||||
extern int SkPnmiSetStruct(SK_AC *pAC, SK_IOC IoC, void* pBuf,
|
||||
unsigned int *pLen, SK_U32 NetIndex);
|
||||
extern int SkPnmiEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event,
|
||||
SK_EVPARA Param);
|
||||
extern int SkPnmiGenIoctl(SK_AC *pAC, SK_IOC IoC, void * pBuf,
|
||||
unsigned int * pLen, SK_U32 NetIndex);
|
||||
|
||||
#endif
|
|
@ -1,110 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Name: skgesirq.h
|
||||
* Project: Gigabit Ethernet Adapters, Common Modules
|
||||
* Version: $Revision: 1.30 $
|
||||
* Date: $Date: 2003/07/04 12:34:13 $
|
||||
* Purpose: SK specific Gigabit Ethernet special IRQ functions
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* (C)Copyright 1998-2002 SysKonnect.
|
||||
* (C)Copyright 2002-2003 Marvell.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* The information in this file is provided "AS IS" without warranty.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _INC_SKGESIRQ_H_
|
||||
#define _INC_SKGESIRQ_H_
|
||||
|
||||
/* Define return codes of SkGePortCheckUp and CheckShort */
|
||||
#define SK_HW_PS_NONE 0 /* No action needed */
|
||||
#define SK_HW_PS_RESTART 1 /* Restart needed */
|
||||
#define SK_HW_PS_LINK 2 /* Link Up actions needed */
|
||||
|
||||
/*
|
||||
* Define the Event the special IRQ/INI module can handle
|
||||
*/
|
||||
#define SK_HWEV_WATIM 1 /* Timeout for WA Errata #2 XMAC */
|
||||
#define SK_HWEV_PORT_START 2 /* Port Start Event by RLMT */
|
||||
#define SK_HWEV_PORT_STOP 3 /* Port Stop Event by RLMT */
|
||||
#define SK_HWEV_CLEAR_STAT 4 /* Clear Statistics by PNMI */
|
||||
#define SK_HWEV_UPDATE_STAT 5 /* Update Statistics by PNMI */
|
||||
#define SK_HWEV_SET_LMODE 6 /* Set Link Mode by PNMI */
|
||||
#define SK_HWEV_SET_FLOWMODE 7 /* Set Flow Control Mode by PNMI */
|
||||
#define SK_HWEV_SET_ROLE 8 /* Set Master/Slave (Role) by PNMI */
|
||||
#define SK_HWEV_SET_SPEED 9 /* Set Link Speed by PNMI */
|
||||
#define SK_HWEV_HALFDUP_CHK 10 /* Half Duplex Hangup Workaround */
|
||||
|
||||
#define SK_WA_ACT_TIME (5000000UL) /* 5 sec */
|
||||
#define SK_WA_INA_TIME (100000UL) /* 100 msec */
|
||||
|
||||
#define SK_HALFDUP_CHK_TIME (10000UL) /* 10 msec */
|
||||
|
||||
/*
|
||||
* Define the error numbers and messages
|
||||
*/
|
||||
#define SKERR_SIRQ_E001 (SK_ERRBASE_SIRQ+0)
|
||||
#define SKERR_SIRQ_E001MSG "Unknown event"
|
||||
#define SKERR_SIRQ_E002 (SKERR_SIRQ_E001+1)
|
||||
#define SKERR_SIRQ_E002MSG "Packet timeout RX1"
|
||||
#define SKERR_SIRQ_E003 (SKERR_SIRQ_E002+1)
|
||||
#define SKERR_SIRQ_E003MSG "Packet timeout RX2"
|
||||
#define SKERR_SIRQ_E004 (SKERR_SIRQ_E003+1)
|
||||
#define SKERR_SIRQ_E004MSG "MAC 1 not correctly initialized"
|
||||
#define SKERR_SIRQ_E005 (SKERR_SIRQ_E004+1)
|
||||
#define SKERR_SIRQ_E005MSG "MAC 2 not correctly initialized"
|
||||
#define SKERR_SIRQ_E006 (SKERR_SIRQ_E005+1)
|
||||
#define SKERR_SIRQ_E006MSG "CHECK failure R1"
|
||||
#define SKERR_SIRQ_E007 (SKERR_SIRQ_E006+1)
|
||||
#define SKERR_SIRQ_E007MSG "CHECK failure R2"
|
||||
#define SKERR_SIRQ_E008 (SKERR_SIRQ_E007+1)
|
||||
#define SKERR_SIRQ_E008MSG "CHECK failure XS1"
|
||||
#define SKERR_SIRQ_E009 (SKERR_SIRQ_E008+1)
|
||||
#define SKERR_SIRQ_E009MSG "CHECK failure XA1"
|
||||
#define SKERR_SIRQ_E010 (SKERR_SIRQ_E009+1)
|
||||
#define SKERR_SIRQ_E010MSG "CHECK failure XS2"
|
||||
#define SKERR_SIRQ_E011 (SKERR_SIRQ_E010+1)
|
||||
#define SKERR_SIRQ_E011MSG "CHECK failure XA2"
|
||||
#define SKERR_SIRQ_E012 (SKERR_SIRQ_E011+1)
|
||||
#define SKERR_SIRQ_E012MSG "unexpected IRQ Master error"
|
||||
#define SKERR_SIRQ_E013 (SKERR_SIRQ_E012+1)
|
||||
#define SKERR_SIRQ_E013MSG "unexpected IRQ Status error"
|
||||
#define SKERR_SIRQ_E014 (SKERR_SIRQ_E013+1)
|
||||
#define SKERR_SIRQ_E014MSG "Parity error on RAM (read)"
|
||||
#define SKERR_SIRQ_E015 (SKERR_SIRQ_E014+1)
|
||||
#define SKERR_SIRQ_E015MSG "Parity error on RAM (write)"
|
||||
#define SKERR_SIRQ_E016 (SKERR_SIRQ_E015+1)
|
||||
#define SKERR_SIRQ_E016MSG "Parity error MAC 1"
|
||||
#define SKERR_SIRQ_E017 (SKERR_SIRQ_E016+1)
|
||||
#define SKERR_SIRQ_E017MSG "Parity error MAC 2"
|
||||
#define SKERR_SIRQ_E018 (SKERR_SIRQ_E017+1)
|
||||
#define SKERR_SIRQ_E018MSG "Parity error RX 1"
|
||||
#define SKERR_SIRQ_E019 (SKERR_SIRQ_E018+1)
|
||||
#define SKERR_SIRQ_E019MSG "Parity error RX 2"
|
||||
#define SKERR_SIRQ_E020 (SKERR_SIRQ_E019+1)
|
||||
#define SKERR_SIRQ_E020MSG "MAC transmit FIFO underrun"
|
||||
#define SKERR_SIRQ_E021 (SKERR_SIRQ_E020+1)
|
||||
#define SKERR_SIRQ_E021MSG "Spurious TWSI interrupt"
|
||||
#define SKERR_SIRQ_E022 (SKERR_SIRQ_E021+1)
|
||||
#define SKERR_SIRQ_E022MSG "Cable pair swap error"
|
||||
#define SKERR_SIRQ_E023 (SKERR_SIRQ_E022+1)
|
||||
#define SKERR_SIRQ_E023MSG "Auto-negotiation error"
|
||||
#define SKERR_SIRQ_E024 (SKERR_SIRQ_E023+1)
|
||||
#define SKERR_SIRQ_E024MSG "FIFO overflow error"
|
||||
#define SKERR_SIRQ_E025 (SKERR_SIRQ_E024+1)
|
||||
#define SKERR_SIRQ_E025MSG "2 Pair Downshift detected"
|
||||
|
||||
extern void SkGeSirqIsr(SK_AC *pAC, SK_IOC IoC, SK_U32 Istatus);
|
||||
extern int SkGeSirqEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Para);
|
||||
extern void SkHWLinkDown(SK_AC *pAC, SK_IOC IoC, int Port);
|
||||
|
||||
#endif /* _INC_SKGESIRQ_H_ */
|
|
@ -1,174 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Name: ski2c.h
|
||||
* Project: Gigabit Ethernet Adapters, TWSI-Module
|
||||
* Version: $Revision: 1.35 $
|
||||
* Date: $Date: 2003/10/20 09:06:30 $
|
||||
* Purpose: Defines to access Voltage and Temperature Sensor
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* (C)Copyright 1998-2002 SysKonnect.
|
||||
* (C)Copyright 2002-2003 Marvell.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* The information in this file is provided "AS IS" without warranty.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*
|
||||
* SKI2C.H contains all I2C specific defines
|
||||
*/
|
||||
|
||||
#ifndef _SKI2C_H_
|
||||
#define _SKI2C_H_
|
||||
|
||||
typedef struct s_Sensor SK_SENSOR;
|
||||
|
||||
#include "h/skgei2c.h"
|
||||
|
||||
/*
|
||||
* Define the I2C events.
|
||||
*/
|
||||
#define SK_I2CEV_IRQ 1 /* IRQ happened Event */
|
||||
#define SK_I2CEV_TIM 2 /* Timeout event */
|
||||
#define SK_I2CEV_CLEAR 3 /* Clear MIB Values */
|
||||
|
||||
/*
|
||||
* Define READ and WRITE Constants.
|
||||
*/
|
||||
#define I2C_READ 0
|
||||
#define I2C_WRITE 1
|
||||
#define I2C_BURST 1
|
||||
#define I2C_SINGLE 0
|
||||
|
||||
#define SKERR_I2C_E001 (SK_ERRBASE_I2C+0)
|
||||
#define SKERR_I2C_E001MSG "Sensor index unknown"
|
||||
#define SKERR_I2C_E002 (SKERR_I2C_E001+1)
|
||||
#define SKERR_I2C_E002MSG "TWSI: transfer does not complete"
|
||||
#define SKERR_I2C_E003 (SKERR_I2C_E002+1)
|
||||
#define SKERR_I2C_E003MSG "LM80: NAK on device send"
|
||||
#define SKERR_I2C_E004 (SKERR_I2C_E003+1)
|
||||
#define SKERR_I2C_E004MSG "LM80: NAK on register send"
|
||||
#define SKERR_I2C_E005 (SKERR_I2C_E004+1)
|
||||
#define SKERR_I2C_E005MSG "LM80: NAK on device (2) send"
|
||||
#define SKERR_I2C_E006 (SKERR_I2C_E005+1)
|
||||
#define SKERR_I2C_E006MSG "Unknown event"
|
||||
#define SKERR_I2C_E007 (SKERR_I2C_E006+1)
|
||||
#define SKERR_I2C_E007MSG "LM80 read out of state"
|
||||
#define SKERR_I2C_E008 (SKERR_I2C_E007+1)
|
||||
#define SKERR_I2C_E008MSG "Unexpected sensor read completed"
|
||||
#define SKERR_I2C_E009 (SKERR_I2C_E008+1)
|
||||
#define SKERR_I2C_E009MSG "WARNING: temperature sensor out of range"
|
||||
#define SKERR_I2C_E010 (SKERR_I2C_E009+1)
|
||||
#define SKERR_I2C_E010MSG "WARNING: voltage sensor out of range"
|
||||
#define SKERR_I2C_E011 (SKERR_I2C_E010+1)
|
||||
#define SKERR_I2C_E011MSG "ERROR: temperature sensor out of range"
|
||||
#define SKERR_I2C_E012 (SKERR_I2C_E011+1)
|
||||
#define SKERR_I2C_E012MSG "ERROR: voltage sensor out of range"
|
||||
#define SKERR_I2C_E013 (SKERR_I2C_E012+1)
|
||||
#define SKERR_I2C_E013MSG "ERROR: couldn't init sensor"
|
||||
#define SKERR_I2C_E014 (SKERR_I2C_E013+1)
|
||||
#define SKERR_I2C_E014MSG "WARNING: fan sensor out of range"
|
||||
#define SKERR_I2C_E015 (SKERR_I2C_E014+1)
|
||||
#define SKERR_I2C_E015MSG "ERROR: fan sensor out of range"
|
||||
#define SKERR_I2C_E016 (SKERR_I2C_E015+1)
|
||||
#define SKERR_I2C_E016MSG "TWSI: active transfer does not complete"
|
||||
|
||||
/*
|
||||
* Define Timeout values
|
||||
*/
|
||||
#define SK_I2C_TIM_LONG 2000000L /* 2 seconds */
|
||||
#define SK_I2C_TIM_SHORT 100000L /* 100 milliseconds */
|
||||
#define SK_I2C_TIM_WATCH 1000000L /* 1 second */
|
||||
|
||||
/*
|
||||
* Define trap and error log hold times
|
||||
*/
|
||||
#ifndef SK_SEN_ERR_TR_HOLD
|
||||
#define SK_SEN_ERR_TR_HOLD (4*SK_TICKS_PER_SEC)
|
||||
#endif
|
||||
#ifndef SK_SEN_ERR_LOG_HOLD
|
||||
#define SK_SEN_ERR_LOG_HOLD (60*SK_TICKS_PER_SEC)
|
||||
#endif
|
||||
#ifndef SK_SEN_WARN_TR_HOLD
|
||||
#define SK_SEN_WARN_TR_HOLD (15*SK_TICKS_PER_SEC)
|
||||
#endif
|
||||
#ifndef SK_SEN_WARN_LOG_HOLD
|
||||
#define SK_SEN_WARN_LOG_HOLD (15*60*SK_TICKS_PER_SEC)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Defines for SenType
|
||||
*/
|
||||
#define SK_SEN_UNKNOWN 0
|
||||
#define SK_SEN_TEMP 1
|
||||
#define SK_SEN_VOLT 2
|
||||
#define SK_SEN_FAN 3
|
||||
|
||||
/*
|
||||
* Define for the SenErrorFlag
|
||||
*/
|
||||
#define SK_SEN_ERR_NOT_PRESENT 0 /* Error Flag: Sensor not present */
|
||||
#define SK_SEN_ERR_OK 1 /* Error Flag: O.K. */
|
||||
#define SK_SEN_ERR_WARN 2 /* Error Flag: Warning */
|
||||
#define SK_SEN_ERR_ERR 3 /* Error Flag: Error */
|
||||
#define SK_SEN_ERR_FAULTY 4 /* Error Flag: Faulty */
|
||||
|
||||
/*
|
||||
* Define the Sensor struct
|
||||
*/
|
||||
struct s_Sensor {
|
||||
char *SenDesc; /* Description */
|
||||
int SenType; /* Voltage or Temperature */
|
||||
SK_I32 SenValue; /* Current value of the sensor */
|
||||
SK_I32 SenThreErrHigh; /* High error Threshhold of this sensor */
|
||||
SK_I32 SenThreWarnHigh; /* High warning Threshhold of this sensor */
|
||||
SK_I32 SenThreErrLow; /* Lower error Threshold of the sensor */
|
||||
SK_I32 SenThreWarnLow; /* Lower warning Threshold of the sensor */
|
||||
int SenErrFlag; /* Sensor indicated an error */
|
||||
SK_BOOL SenInit; /* Is sensor initialized ? */
|
||||
SK_U64 SenErrCts; /* Error trap counter */
|
||||
SK_U64 SenWarnCts; /* Warning trap counter */
|
||||
SK_U64 SenBegErrTS; /* Begin error timestamp */
|
||||
SK_U64 SenBegWarnTS; /* Begin warning timestamp */
|
||||
SK_U64 SenLastErrTrapTS; /* Last error trap timestamp */
|
||||
SK_U64 SenLastErrLogTS; /* Last error log timestamp */
|
||||
SK_U64 SenLastWarnTrapTS; /* Last warning trap timestamp */
|
||||
SK_U64 SenLastWarnLogTS; /* Last warning log timestamp */
|
||||
int SenState; /* Sensor State (see HW specific include) */
|
||||
int (*SenRead)(SK_AC *pAC, SK_IOC IoC, struct s_Sensor *pSen);
|
||||
/* Sensors read function */
|
||||
SK_U16 SenReg; /* Register Address for this sensor */
|
||||
SK_U8 SenDev; /* Device Selection for this sensor */
|
||||
};
|
||||
|
||||
typedef struct s_I2c {
|
||||
SK_SENSOR SenTable[SK_MAX_SENSORS]; /* Sensor Table */
|
||||
int CurrSens; /* Which sensor is currently queried */
|
||||
int MaxSens; /* Max. number of sensors */
|
||||
int TimerMode; /* Use the timer also to watch the state machine */
|
||||
int InitLevel; /* Initialized Level */
|
||||
#ifndef SK_DIAG
|
||||
int DummyReads; /* Number of non-checked dummy reads */
|
||||
SK_TIMER SenTimer; /* Sensors timer */
|
||||
#endif /* !SK_DIAG */
|
||||
} SK_I2C;
|
||||
|
||||
extern int SkI2cInit(SK_AC *pAC, SK_IOC IoC, int Level);
|
||||
#ifdef SK_DIAG
|
||||
extern SK_U32 SkI2cRead(SK_AC *pAC, SK_IOC IoC, int Dev, int Size, int Reg,
|
||||
int Burst);
|
||||
#else /* !SK_DIAG */
|
||||
extern int SkI2cEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Para);
|
||||
extern void SkI2cWaitIrq(SK_AC *pAC, SK_IOC IoC);
|
||||
extern void SkI2cIsr(SK_AC *pAC, SK_IOC IoC);
|
||||
#endif /* !SK_DIAG */
|
||||
#endif /* n_SKI2C_H */
|
||||
|
|
@ -1,94 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Name: skqueue.h
|
||||
* Project: Gigabit Ethernet Adapters, Event Scheduler Module
|
||||
* Version: $Revision: 1.16 $
|
||||
* Date: $Date: 2003/09/16 12:50:32 $
|
||||
* Purpose: Defines for the Event queue
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* (C)Copyright 1998-2002 SysKonnect GmbH.
|
||||
* (C)Copyright 2002-2003 Marvell.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* The information in this file is provided "AS IS" without warranty.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*
|
||||
* SKQUEUE.H contains all defines and types for the event queue
|
||||
*/
|
||||
|
||||
#ifndef _SKQUEUE_H_
|
||||
#define _SKQUEUE_H_
|
||||
|
||||
|
||||
/*
|
||||
* define the event classes to be served
|
||||
*/
|
||||
#define SKGE_DRV 1 /* Driver Event Class */
|
||||
#define SKGE_RLMT 2 /* RLMT Event Class */
|
||||
#define SKGE_I2C 3 /* I2C Event Class */
|
||||
#define SKGE_PNMI 4 /* PNMI Event Class */
|
||||
#define SKGE_CSUM 5 /* Checksum Event Class */
|
||||
#define SKGE_HWAC 6 /* Hardware Access Event Class */
|
||||
|
||||
#define SKGE_SWT 9 /* Software Timer Event Class */
|
||||
#define SKGE_LACP 10 /* LACP Aggregation Event Class */
|
||||
#define SKGE_RSF 11 /* RSF Aggregation Event Class */
|
||||
#define SKGE_MARKER 12 /* MARKER Aggregation Event Class */
|
||||
#define SKGE_FD 13 /* FD Distributor Event Class */
|
||||
|
||||
/*
|
||||
* define event queue as circular buffer
|
||||
*/
|
||||
#define SK_MAX_EVENT 64
|
||||
|
||||
/*
|
||||
* Parameter union for the Para stuff
|
||||
*/
|
||||
typedef union u_EvPara {
|
||||
void *pParaPtr; /* Parameter Pointer */
|
||||
SK_U64 Para64; /* Parameter 64bit version */
|
||||
SK_U32 Para32[2]; /* Parameter Array of 32bit parameters */
|
||||
} SK_EVPARA;
|
||||
|
||||
/*
|
||||
* Event Queue
|
||||
* skqueue.c
|
||||
* events are class/value pairs
|
||||
* class is addressee, e.g. RLMT, PNMI etc.
|
||||
* value is command, e.g. line state change, ring op change etc.
|
||||
*/
|
||||
typedef struct s_EventElem {
|
||||
SK_U32 Class; /* Event class */
|
||||
SK_U32 Event; /* Event value */
|
||||
SK_EVPARA Para; /* Event parameter */
|
||||
} SK_EVENTELEM;
|
||||
|
||||
typedef struct s_Queue {
|
||||
SK_EVENTELEM EvQueue[SK_MAX_EVENT];
|
||||
SK_EVENTELEM *EvPut;
|
||||
SK_EVENTELEM *EvGet;
|
||||
} SK_QUEUE;
|
||||
|
||||
extern void SkEventInit(SK_AC *pAC, SK_IOC Ioc, int Level);
|
||||
extern void SkEventQueue(SK_AC *pAC, SK_U32 Class, SK_U32 Event,
|
||||
SK_EVPARA Para);
|
||||
extern int SkEventDispatcher(SK_AC *pAC, SK_IOC Ioc);
|
||||
|
||||
|
||||
/* Define Error Numbers and messages */
|
||||
#define SKERR_Q_E001 (SK_ERRBASE_QUEUE+0)
|
||||
#define SKERR_Q_E001MSG "Event queue overflow"
|
||||
#define SKERR_Q_E002 (SKERR_Q_E001+1)
|
||||
#define SKERR_Q_E002MSG "Undefined event class"
|
||||
#endif /* _SKQUEUE_H_ */
|
||||
|
|
@ -1,438 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Name: skrlmt.h
|
||||
* Project: GEnesis, PCI Gigabit Ethernet Adapter
|
||||
* Version: $Revision: 1.37 $
|
||||
* Date: $Date: 2003/04/15 09:43:43 $
|
||||
* Purpose: Header file for Redundant Link ManagemenT.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* (C)Copyright 1998-2002 SysKonnect GmbH.
|
||||
* (C)Copyright 2002-2003 Marvell.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* The information in this file is provided "AS IS" without warranty.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Description:
|
||||
*
|
||||
* This is the header file for Redundant Link ManagemenT.
|
||||
*
|
||||
* Include File Hierarchy:
|
||||
*
|
||||
* "skdrv1st.h"
|
||||
* ...
|
||||
* "sktypes.h"
|
||||
* "skqueue.h"
|
||||
* "skaddr.h"
|
||||
* "skrlmt.h"
|
||||
* ...
|
||||
* "skdrv2nd.h"
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __INC_SKRLMT_H
|
||||
#define __INC_SKRLMT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* cplusplus */
|
||||
|
||||
/* defines ********************************************************************/
|
||||
|
||||
#define SK_RLMT_NET_DOWN_TEMP 1 /* NET_DOWN due to last port down. */
|
||||
#define SK_RLMT_NET_DOWN_FINAL 2 /* NET_DOWN due to RLMT_STOP. */
|
||||
|
||||
/* ----- Default queue sizes - must be multiples of 8 KB ----- */
|
||||
|
||||
/* Less than 8 KB free in RX queue => pause frames. */
|
||||
#define SK_RLMT_STANDBY_QRXSIZE 128 /* Size of rx standby queue in KB. */
|
||||
#define SK_RLMT_STANDBY_QXASIZE 32 /* Size of async standby queue in KB. */
|
||||
#define SK_RLMT_STANDBY_QXSSIZE 0 /* Size of sync standby queue in KB. */
|
||||
|
||||
#define SK_RLMT_MAX_TX_BUF_SIZE 60 /* Maximum RLMT transmit size. */
|
||||
|
||||
/* ----- PORT states ----- */
|
||||
|
||||
#define SK_RLMT_PS_INIT 0 /* Port state: Init. */
|
||||
#define SK_RLMT_PS_LINK_DOWN 1 /* Port state: Link down. */
|
||||
#define SK_RLMT_PS_DOWN 2 /* Port state: Port down. */
|
||||
#define SK_RLMT_PS_GOING_UP 3 /* Port state: Going up. */
|
||||
#define SK_RLMT_PS_UP 4 /* Port state: Up. */
|
||||
|
||||
/* ----- RLMT states ----- */
|
||||
|
||||
#define SK_RLMT_RS_INIT 0 /* RLMT state: Init. */
|
||||
#define SK_RLMT_RS_NET_DOWN 1 /* RLMT state: Net down. */
|
||||
#define SK_RLMT_RS_NET_UP 2 /* RLMT state: Net up. */
|
||||
|
||||
/* ----- PORT events ----- */
|
||||
|
||||
#define SK_RLMT_LINK_UP 1001 /* Link came up. */
|
||||
#define SK_RLMT_LINK_DOWN 1002 /* Link went down. */
|
||||
#define SK_RLMT_PORT_ADDR 1003 /* Port address changed. */
|
||||
|
||||
/* ----- RLMT events ----- */
|
||||
|
||||
#define SK_RLMT_START 2001 /* Start RLMT. */
|
||||
#define SK_RLMT_STOP 2002 /* Stop RLMT. */
|
||||
#define SK_RLMT_PACKET_RECEIVED 2003 /* Packet was received for RLMT. */
|
||||
#define SK_RLMT_STATS_CLEAR 2004 /* Clear statistics. */
|
||||
#define SK_RLMT_STATS_UPDATE 2005 /* Update statistics. */
|
||||
#define SK_RLMT_PREFPORT_CHANGE 2006 /* Change preferred port. */
|
||||
#define SK_RLMT_MODE_CHANGE 2007 /* New RlmtMode. */
|
||||
#define SK_RLMT_SET_NETS 2008 /* Number of Nets (1 or 2). */
|
||||
|
||||
/* ----- RLMT mode bits ----- */
|
||||
|
||||
/*
|
||||
* CAUTION: These defines are private to RLMT.
|
||||
* Please use the RLMT mode defines below.
|
||||
*/
|
||||
|
||||
#define SK_RLMT_CHECK_LINK 1 /* Check Link. */
|
||||
#define SK_RLMT_CHECK_LOC_LINK 2 /* Check other link on same adapter. */
|
||||
#define SK_RLMT_CHECK_SEG 4 /* Check segmentation. */
|
||||
|
||||
#ifndef RLMT_CHECK_REMOTE
|
||||
#define SK_RLMT_CHECK_OTHERS SK_RLMT_CHECK_LOC_LINK
|
||||
#else /* RLMT_CHECK_REMOTE */
|
||||
#define SK_RLMT_CHECK_REM_LINK 8 /* Check link(s) on other adapter(s). */
|
||||
#define SK_RLMT_MAX_REMOTE_PORTS_CHECKED 3
|
||||
#define SK_RLMT_CHECK_OTHERS \
|
||||
(SK_RLMT_CHECK_LOC_LINK | SK_RLMT_CHECK_REM_LINK)
|
||||
#endif /* RLMT_CHECK_REMOTE */
|
||||
|
||||
#ifndef SK_RLMT_ENABLE_TRANSPARENT
|
||||
#define SK_RLMT_TRANSPARENT 0 /* RLMT transparent - inactive. */
|
||||
#else /* SK_RLMT_ENABLE_TRANSPARENT */
|
||||
#define SK_RLMT_TRANSPARENT 128 /* RLMT transparent. */
|
||||
#endif /* SK_RLMT_ENABLE_TRANSPARENT */
|
||||
|
||||
/* ----- RLMT modes ----- */
|
||||
|
||||
/* Check Link State. */
|
||||
#define SK_RLMT_MODE_CLS (SK_RLMT_CHECK_LINK)
|
||||
|
||||
/* Check Local Ports: check other links on the same adapter. */
|
||||
#define SK_RLMT_MODE_CLP (SK_RLMT_CHECK_LINK | SK_RLMT_CHECK_LOC_LINK)
|
||||
|
||||
/* Check Local Ports and Segmentation Status. */
|
||||
#define SK_RLMT_MODE_CLPSS \
|
||||
(SK_RLMT_CHECK_LINK | SK_RLMT_CHECK_LOC_LINK | SK_RLMT_CHECK_SEG)
|
||||
|
||||
#ifdef RLMT_CHECK_REMOTE
|
||||
/* Check Local and Remote Ports: check links (local or remote). */
|
||||
Name of define TBD!
|
||||
#define SK_RLMT_MODE_CRP \
|
||||
(SK_RLMT_CHECK_LINK | SK_RLMT_CHECK_LOC_LINK | SK_RLMT_CHECK_REM_LINK)
|
||||
|
||||
/* Check Local and Remote Ports and Segmentation Status. */
|
||||
Name of define TBD!
|
||||
#define SK_RLMT_MODE_CRPSS \
|
||||
(SK_RLMT_CHECK_LINK | SK_RLMT_CHECK_LOC_LINK | \
|
||||
SK_RLMT_CHECK_REM_LINK | SK_RLMT_CHECK_SEG)
|
||||
#endif /* RLMT_CHECK_REMOTE */
|
||||
|
||||
/* ----- RLMT lookahead result bits ----- */
|
||||
|
||||
#define SK_RLMT_RX_RLMT 1 /* Give packet to RLMT. */
|
||||
#define SK_RLMT_RX_PROTOCOL 2 /* Give packet to protocol. */
|
||||
|
||||
/* Macros */
|
||||
|
||||
#if 0
|
||||
SK_AC *pAC /* adapter context */
|
||||
SK_U32 PortNum /* receiving port */
|
||||
unsigned PktLen /* received packet's length */
|
||||
SK_BOOL IsBc /* Flag: packet is broadcast */
|
||||
unsigned *pOffset /* offs. of bytes to present to SK_RLMT_LOOKAHEAD */
|
||||
unsigned *pNumBytes /* #Bytes to present to SK_RLMT_LOOKAHEAD */
|
||||
#endif /* 0 */
|
||||
|
||||
#define SK_RLMT_PRE_LOOKAHEAD(pAC,PortNum,PktLen,IsBc,pOffset,pNumBytes) { \
|
||||
SK_AC *_pAC; \
|
||||
SK_U32 _PortNum; \
|
||||
_pAC = (pAC); \
|
||||
_PortNum = (SK_U32)(PortNum); \
|
||||
/* _pAC->Rlmt.Port[_PortNum].PacketsRx++; */ \
|
||||
_pAC->Rlmt.Port[_PortNum].PacketsPerTimeSlot++; \
|
||||
if (_pAC->Rlmt.RlmtOff) { \
|
||||
*(pNumBytes) = 0; \
|
||||
} \
|
||||
else {\
|
||||
if ((_pAC->Rlmt.Port[_PortNum].Net->RlmtMode & SK_RLMT_TRANSPARENT) != 0) { \
|
||||
*(pNumBytes) = 0; \
|
||||
} \
|
||||
else if (IsBc) { \
|
||||
if (_pAC->Rlmt.Port[_PortNum].Net->RlmtMode != SK_RLMT_MODE_CLS) { \
|
||||
*(pNumBytes) = 6; \
|
||||
*(pOffset) = 6; \
|
||||
} \
|
||||
else { \
|
||||
*(pNumBytes) = 0; \
|
||||
} \
|
||||
} \
|
||||
else { \
|
||||
if ((PktLen) > SK_RLMT_MAX_TX_BUF_SIZE) { \
|
||||
/* _pAC->Rlmt.Port[_PortNum].DataPacketsPerTimeSlot++; */ \
|
||||
*(pNumBytes) = 0; \
|
||||
} \
|
||||
else { \
|
||||
*(pNumBytes) = 6; \
|
||||
*(pOffset) = 0; \
|
||||
} \
|
||||
} \
|
||||
} \
|
||||
}
|
||||
|
||||
#if 0
|
||||
SK_AC *pAC /* adapter context */
|
||||
SK_U32 PortNum /* receiving port */
|
||||
SK_U8 *pLaPacket, /* received packet's data (points to pOffset) */
|
||||
SK_BOOL IsBc /* Flag: packet is broadcast */
|
||||
SK_BOOL IsMc /* Flag: packet is multicast */
|
||||
unsigned *pForRlmt /* Result: bits SK_RLMT_RX_RLMT, SK_RLMT_RX_PROTOCOL */
|
||||
SK_RLMT_LOOKAHEAD() expects *pNumBytes from
|
||||
packet offset *pOffset (s.a.) at *pLaPacket.
|
||||
|
||||
If you use SK_RLMT_LOOKAHEAD in a path where you already know if the packet is
|
||||
BC, MC, or UC, you should use constants for IsBc and IsMc, so that your compiler
|
||||
can trash unneeded parts of the if construction.
|
||||
#endif /* 0 */
|
||||
|
||||
#define SK_RLMT_LOOKAHEAD(pAC,PortNum,pLaPacket,IsBc,IsMc,pForRlmt) { \
|
||||
SK_AC *_pAC; \
|
||||
SK_U32 _PortNum; \
|
||||
SK_U8 *_pLaPacket; \
|
||||
_pAC = (pAC); \
|
||||
_PortNum = (SK_U32)(PortNum); \
|
||||
_pLaPacket = (SK_U8 *)(pLaPacket); \
|
||||
if (IsBc) {\
|
||||
if (!SK_ADDR_EQUAL(_pLaPacket, _pAC->Addr.Net[_pAC->Rlmt.Port[ \
|
||||
_PortNum].Net->NetNumber].CurrentMacAddress.a)) { \
|
||||
_pAC->Rlmt.Port[_PortNum].BcTimeStamp = SkOsGetTime(_pAC); \
|
||||
_pAC->Rlmt.CheckSwitch = SK_TRUE; \
|
||||
} \
|
||||
/* _pAC->Rlmt.Port[_PortNum].DataPacketsPerTimeSlot++; */ \
|
||||
*(pForRlmt) = SK_RLMT_RX_PROTOCOL; \
|
||||
} \
|
||||
else if (IsMc) { \
|
||||
if (SK_ADDR_EQUAL(_pLaPacket, BridgeMcAddr.a)) { \
|
||||
_pAC->Rlmt.Port[_PortNum].BpduPacketsPerTimeSlot++; \
|
||||
if (_pAC->Rlmt.Port[_PortNum].Net->RlmtMode & SK_RLMT_CHECK_SEG) { \
|
||||
*(pForRlmt) = SK_RLMT_RX_RLMT | SK_RLMT_RX_PROTOCOL; \
|
||||
} \
|
||||
else { \
|
||||
*(pForRlmt) = SK_RLMT_RX_PROTOCOL; \
|
||||
} \
|
||||
} \
|
||||
else if (SK_ADDR_EQUAL(_pLaPacket, SkRlmtMcAddr.a)) { \
|
||||
*(pForRlmt) = SK_RLMT_RX_RLMT; \
|
||||
} \
|
||||
else { \
|
||||
/* _pAC->Rlmt.Port[_PortNum].DataPacketsPerTimeSlot++; */ \
|
||||
*(pForRlmt) = SK_RLMT_RX_PROTOCOL; \
|
||||
} \
|
||||
} \
|
||||
else { \
|
||||
if (SK_ADDR_EQUAL( \
|
||||
_pLaPacket, \
|
||||
_pAC->Addr.Port[_PortNum].CurrentMacAddress.a)) { \
|
||||
*(pForRlmt) = SK_RLMT_RX_RLMT; \
|
||||
} \
|
||||
else { \
|
||||
/* _pAC->Rlmt.Port[_PortNum].DataPacketsPerTimeSlot++; */ \
|
||||
*(pForRlmt) = SK_RLMT_RX_PROTOCOL; \
|
||||
} \
|
||||
} \
|
||||
}
|
||||
|
||||
#ifdef SK_RLMT_FAST_LOOKAHEAD
|
||||
Error: SK_RLMT_FAST_LOOKAHEAD no longer used. Use new macros for lookahead.
|
||||
#endif /* SK_RLMT_FAST_LOOKAHEAD */
|
||||
#ifdef SK_RLMT_SLOW_LOOKAHEAD
|
||||
Error: SK_RLMT_SLOW_LOOKAHEAD no longer used. Use new macros for lookahead.
|
||||
#endif /* SK_RLMT_SLOW_LOOKAHEAD */
|
||||
|
||||
/* typedefs *******************************************************************/
|
||||
|
||||
#ifdef SK_RLMT_MBUF_PRIVATE
|
||||
typedef struct s_RlmtMbuf {
|
||||
some content
|
||||
} SK_RLMT_MBUF;
|
||||
#endif /* SK_RLMT_MBUF_PRIVATE */
|
||||
|
||||
|
||||
#ifdef SK_LA_INFO
|
||||
typedef struct s_Rlmt_PacketInfo {
|
||||
unsigned PacketLength; /* Length of packet. */
|
||||
unsigned PacketType; /* Directed/Multicast/Broadcast. */
|
||||
} SK_RLMT_PINFO;
|
||||
#endif /* SK_LA_INFO */
|
||||
|
||||
|
||||
typedef struct s_RootId {
|
||||
SK_U8 Id[8]; /* Root Bridge Id. */
|
||||
} SK_RLMT_ROOT_ID;
|
||||
|
||||
|
||||
typedef struct s_port {
|
||||
SK_MAC_ADDR CheckAddr;
|
||||
SK_BOOL SuspectTx;
|
||||
} SK_PORT_CHECK;
|
||||
|
||||
|
||||
typedef struct s_RlmtNet SK_RLMT_NET;
|
||||
|
||||
|
||||
typedef struct s_RlmtPort {
|
||||
|
||||
/* ----- Public part (read-only) ----- */
|
||||
|
||||
SK_U8 PortState; /* Current state of this port. */
|
||||
|
||||
/* For PNMI */
|
||||
SK_BOOL LinkDown;
|
||||
SK_BOOL PortDown;
|
||||
SK_U8 Align01;
|
||||
|
||||
SK_U32 PortNumber; /* Number of port on adapter. */
|
||||
SK_RLMT_NET * Net; /* Net port belongs to. */
|
||||
|
||||
SK_U64 TxHelloCts;
|
||||
SK_U64 RxHelloCts;
|
||||
SK_U64 TxSpHelloReqCts;
|
||||
SK_U64 RxSpHelloCts;
|
||||
|
||||
/* ----- Private part ----- */
|
||||
|
||||
/* SK_U64 PacketsRx; */ /* Total packets received. */
|
||||
SK_U32 PacketsPerTimeSlot; /* Packets rxed between TOs. */
|
||||
/* SK_U32 DataPacketsPerTimeSlot; */ /* Data packets ... */
|
||||
SK_U32 BpduPacketsPerTimeSlot; /* BPDU packets rxed in TS. */
|
||||
SK_U64 BcTimeStamp; /* Time of last BC receive. */
|
||||
SK_U64 GuTimeStamp; /* Time of entering GOING_UP. */
|
||||
|
||||
SK_TIMER UpTimer; /* Timer struct Link/Port up. */
|
||||
SK_TIMER DownRxTimer; /* Timer struct down rx. */
|
||||
SK_TIMER DownTxTimer; /* Timer struct down tx. */
|
||||
|
||||
SK_U32 CheckingState; /* Checking State. */
|
||||
|
||||
SK_ADDR_PORT * AddrPort;
|
||||
|
||||
SK_U8 Random[4]; /* Random value. */
|
||||
unsigned PortsChecked; /* #ports checked. */
|
||||
unsigned PortsSuspect; /* #ports checked that are s. */
|
||||
SK_PORT_CHECK PortCheck[1];
|
||||
/* SK_PORT_CHECK PortCheck[SK_MAX_MACS - 1]; */
|
||||
|
||||
SK_BOOL PortStarted; /* Port is started. */
|
||||
SK_BOOL PortNoRx; /* NoRx for >= 1 time slot. */
|
||||
SK_BOOL RootIdSet;
|
||||
SK_RLMT_ROOT_ID Root; /* Root Bridge Id. */
|
||||
} SK_RLMT_PORT;
|
||||
|
||||
|
||||
struct s_RlmtNet {
|
||||
|
||||
/* ----- Public part (read-only) ----- */
|
||||
|
||||
SK_U32 NetNumber; /* Number of net. */
|
||||
|
||||
SK_RLMT_PORT * Port[SK_MAX_MACS]; /* Ports that belong to this net. */
|
||||
SK_U32 NumPorts; /* Number of ports. */
|
||||
SK_U32 PrefPort; /* Preferred port. */
|
||||
|
||||
/* For PNMI */
|
||||
|
||||
SK_U32 ChgBcPrio; /* Change Priority of last broadcast received */
|
||||
SK_U32 RlmtMode; /* Check ... */
|
||||
SK_U32 ActivePort; /* Active port. */
|
||||
SK_U32 Preference; /* 0xFFFFFFFF: Automatic. */
|
||||
|
||||
SK_U8 RlmtState; /* Current RLMT state. */
|
||||
|
||||
/* ----- Private part ----- */
|
||||
SK_BOOL RootIdSet;
|
||||
SK_U16 Align01;
|
||||
|
||||
int LinksUp; /* #Links up. */
|
||||
int PortsUp; /* #Ports up. */
|
||||
SK_U32 TimeoutValue; /* RLMT timeout value. */
|
||||
|
||||
SK_U32 CheckingState; /* Checking State. */
|
||||
SK_RLMT_ROOT_ID Root; /* Root Bridge Id. */
|
||||
|
||||
SK_TIMER LocTimer; /* Timer struct. */
|
||||
SK_TIMER SegTimer; /* Timer struct. */
|
||||
};
|
||||
|
||||
|
||||
typedef struct s_Rlmt {
|
||||
|
||||
/* ----- Public part (read-only) ----- */
|
||||
|
||||
SK_U32 NumNets; /* Number of nets. */
|
||||
SK_U32 NetsStarted; /* Number of nets started. */
|
||||
SK_RLMT_NET Net[SK_MAX_NETS]; /* Array of available nets. */
|
||||
SK_RLMT_PORT Port[SK_MAX_MACS]; /* Array of available ports. */
|
||||
|
||||
/* ----- Private part ----- */
|
||||
SK_BOOL CheckSwitch;
|
||||
SK_BOOL RlmtOff; /* set to zero if the Mac addresses
|
||||
are equal or the second one
|
||||
is zero */
|
||||
SK_U16 Align01;
|
||||
|
||||
} SK_RLMT;
|
||||
|
||||
|
||||
extern SK_MAC_ADDR BridgeMcAddr;
|
||||
extern SK_MAC_ADDR SkRlmtMcAddr;
|
||||
|
||||
/* function prototypes ********************************************************/
|
||||
|
||||
|
||||
#ifndef SK_KR_PROTO
|
||||
|
||||
/* Functions provided by SkRlmt */
|
||||
|
||||
/* ANSI/C++ compliant function prototypes */
|
||||
|
||||
extern void SkRlmtInit(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int Level);
|
||||
|
||||
extern int SkRlmtEvent(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
SK_U32 Event,
|
||||
SK_EVPARA Para);
|
||||
|
||||
#else /* defined(SK_KR_PROTO) */
|
||||
|
||||
/* Non-ANSI/C++ compliant function prototypes */
|
||||
|
||||
#error KR-style function prototypes are not yet provided.
|
||||
|
||||
#endif /* defined(SK_KR_PROTO)) */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* __INC_SKRLMT_H */
|
|
@ -1,63 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Name: sktimer.h
|
||||
* Project: Gigabit Ethernet Adapters, Event Scheduler Module
|
||||
* Version: $Revision: 1.11 $
|
||||
* Date: $Date: 2003/09/16 12:58:18 $
|
||||
* Purpose: Defines for the timer functions
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* (C)Copyright 1998-2002 SysKonnect GmbH.
|
||||
* (C)Copyright 2002-2003 Marvell.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* The information in this file is provided "AS IS" without warranty.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*
|
||||
* SKTIMER.H contains all defines and types for the timer functions
|
||||
*/
|
||||
|
||||
#ifndef _SKTIMER_H_
|
||||
#define _SKTIMER_H_
|
||||
|
||||
#include "h/skqueue.h"
|
||||
|
||||
/*
|
||||
* SK timer
|
||||
* - needed wherever a timer is used. Put this in your data structure
|
||||
* wherever you want.
|
||||
*/
|
||||
typedef struct s_Timer SK_TIMER;
|
||||
|
||||
struct s_Timer {
|
||||
SK_TIMER *TmNext; /* linked list */
|
||||
SK_U32 TmClass; /* Timer Event class */
|
||||
SK_U32 TmEvent; /* Timer Event value */
|
||||
SK_EVPARA TmPara; /* Timer Event parameter */
|
||||
SK_U32 TmDelta; /* delta time */
|
||||
int TmActive; /* flag: active/inactive */
|
||||
};
|
||||
|
||||
/*
|
||||
* Timer control struct.
|
||||
* - use in Adapters context name pAC->Tim
|
||||
*/
|
||||
typedef struct s_TimCtrl {
|
||||
SK_TIMER *StQueue; /* Head of Timer queue */
|
||||
} SK_TIMCTRL;
|
||||
|
||||
extern void SkTimerInit(SK_AC *pAC, SK_IOC Ioc, int Level);
|
||||
extern void SkTimerStop(SK_AC *pAC, SK_IOC Ioc, SK_TIMER *pTimer);
|
||||
extern void SkTimerStart(SK_AC *pAC, SK_IOC Ioc, SK_TIMER *pTimer,
|
||||
SK_U32 Time, SK_U32 Class, SK_U32 Event, SK_EVPARA Para);
|
||||
extern void SkTimerDone(SK_AC *pAC, SK_IOC Ioc);
|
||||
#endif /* _SKTIMER_H_ */
|
|
@ -1,69 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Name: sktypes.h
|
||||
* Project: GEnesis, PCI Gigabit Ethernet Adapter
|
||||
* Version: $Revision: 1.2 $
|
||||
* Date: $Date: 2003/10/07 08:16:51 $
|
||||
* Purpose: Define data types for Linux
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* (C)Copyright 1998-2002 SysKonnect GmbH.
|
||||
* (C)Copyright 2002-2003 Marvell.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* The information in this file is provided "AS IS" without warranty.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Description:
|
||||
*
|
||||
* In this file, all data types that are needed by the common modules
|
||||
* are mapped to Linux data types.
|
||||
*
|
||||
*
|
||||
* Include File Hierarchy:
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __INC_SKTYPES_H
|
||||
#define __INC_SKTYPES_H
|
||||
|
||||
|
||||
/* defines *******************************************************************/
|
||||
|
||||
/*
|
||||
* Data types with a specific size. 'I' = signed, 'U' = unsigned.
|
||||
*/
|
||||
#define SK_I8 s8
|
||||
#define SK_U8 u8
|
||||
#define SK_I16 s16
|
||||
#define SK_U16 u16
|
||||
#define SK_I32 s32
|
||||
#define SK_U32 u32
|
||||
#define SK_I64 s64
|
||||
#define SK_U64 u64
|
||||
|
||||
#define SK_UPTR ulong /* casting pointer <-> integral */
|
||||
|
||||
/*
|
||||
* Boolean type.
|
||||
*/
|
||||
#define SK_BOOL SK_U8
|
||||
#define SK_FALSE 0
|
||||
#define SK_TRUE (!SK_FALSE)
|
||||
|
||||
/* typedefs *******************************************************************/
|
||||
|
||||
/* function prototypes ********************************************************/
|
||||
|
||||
#endif /* __INC_SKTYPES_H */
|
|
@ -1,38 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Name: version.h
|
||||
* Project: GEnesis, PCI Gigabit Ethernet Adapter
|
||||
* Version: $Revision: 1.5 $
|
||||
* Date: $Date: 2003/10/07 08:16:51 $
|
||||
* Purpose: SK specific Error log support
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* (C)Copyright 1998-2002 SysKonnect GmbH.
|
||||
* (C)Copyright 2002-2003 Marvell.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* The information in this file is provided "AS IS" without warranty.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef lint
|
||||
static const char SysKonnectFileId[] = "@(#) (C) SysKonnect GmbH.";
|
||||
static const char SysKonnectBuildNumber[] =
|
||||
"@(#)SK-BUILD: 6.23 PL: 01";
|
||||
#endif /* !defined(lint) */
|
||||
|
||||
#define BOOT_STRING "sk98lin: Network Device Driver v6.23\n" \
|
||||
"(C)Copyright 1999-2004 Marvell(R)."
|
||||
|
||||
#define VER_STRING "6.23"
|
||||
#define DRIVER_FILE_NAME "sk98lin"
|
||||
#define DRIVER_REL_DATE "Feb-13-2004"
|
||||
|
||||
|
|
@ -1,248 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Name: skvpd.h
|
||||
* Project: GEnesis, PCI Gigabit Ethernet Adapter
|
||||
* Version: $Revision: 1.15 $
|
||||
* Date: $Date: 2003/01/13 10:39:38 $
|
||||
* Purpose: Defines and Macros for VPD handling
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* (C)Copyright 1998-2003 SysKonnect GmbH.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* The information in this file is provided "AS IS" without warranty.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*
|
||||
* skvpd.h contains Diagnostic specific defines for VPD handling
|
||||
*/
|
||||
|
||||
#ifndef __INC_SKVPD_H_
|
||||
#define __INC_SKVPD_H_
|
||||
|
||||
/*
|
||||
* Define Resource Type Identifiers and VPD keywords
|
||||
*/
|
||||
#define RES_ID 0x82 /* Resource Type ID String (Product Name) */
|
||||
#define RES_VPD_R 0x90 /* start of VPD read only area */
|
||||
#define RES_VPD_W 0x91 /* start of VPD read/write area */
|
||||
#define RES_END 0x78 /* Resource Type End Tag */
|
||||
|
||||
#ifndef VPD_NAME
|
||||
#define VPD_NAME "Name" /* Product Name, VPD name of RES_ID */
|
||||
#endif /* VPD_NAME */
|
||||
#define VPD_PN "PN" /* Adapter Part Number */
|
||||
#define VPD_EC "EC" /* Adapter Engineering Level */
|
||||
#define VPD_MN "MN" /* Manufacture ID */
|
||||
#define VPD_SN "SN" /* Serial Number */
|
||||
#define VPD_CP "CP" /* Extended Capability */
|
||||
#define VPD_RV "RV" /* Checksum and Reserved */
|
||||
#define VPD_YA "YA" /* Asset Tag Identifier */
|
||||
#define VPD_VL "VL" /* First Error Log Message (SK specific) */
|
||||
#define VPD_VF "VF" /* Second Error Log Message (SK specific) */
|
||||
#define VPD_RW "RW" /* Remaining Read / Write Area */
|
||||
|
||||
/* 'type' values for vpd_setup_para() */
|
||||
#define VPD_RO_KEY 1 /* RO keys are "PN", "EC", "MN", "SN", "RV" */
|
||||
#define VPD_RW_KEY 2 /* RW keys are "Yx", "Vx", and "RW" */
|
||||
|
||||
/* 'op' values for vpd_setup_para() */
|
||||
#define ADD_KEY 1 /* add the key at the pos "RV" or "RW" */
|
||||
#define OWR_KEY 2 /* overwrite key if already exists */
|
||||
|
||||
/*
|
||||
* Define READ and WRITE Constants.
|
||||
*/
|
||||
|
||||
#define VPD_DEV_ID_GENESIS 0x4300
|
||||
|
||||
#define VPD_SIZE_YUKON 256
|
||||
#define VPD_SIZE_GENESIS 512
|
||||
#define VPD_SIZE 512
|
||||
#define VPD_READ 0x0000
|
||||
#define VPD_WRITE 0x8000
|
||||
|
||||
#define VPD_STOP(pAC,IoC) VPD_OUT16(pAC,IoC,PCI_VPD_ADR_REG,VPD_WRITE)
|
||||
|
||||
#define VPD_GET_RES_LEN(p) ((unsigned int) \
|
||||
(* (SK_U8 *)&(p)[1]) |\
|
||||
((* (SK_U8 *)&(p)[2]) << 8))
|
||||
#define VPD_GET_VPD_LEN(p) ((unsigned int)(* (SK_U8 *)&(p)[2]))
|
||||
#define VPD_GET_VAL(p) ((char *)&(p)[3])
|
||||
|
||||
#define VPD_MAX_LEN 50
|
||||
|
||||
/* VPD status */
|
||||
/* bit 7..1 reserved */
|
||||
#define VPD_VALID (1<<0) /* VPD data buffer, vpd_free_ro, */
|
||||
/* and vpd_free_rw valid */
|
||||
|
||||
/*
|
||||
* VPD structs
|
||||
*/
|
||||
typedef struct s_vpd_status {
|
||||
unsigned short Align01; /* Alignment */
|
||||
unsigned short vpd_status; /* VPD status, description see above */
|
||||
int vpd_free_ro; /* unused bytes in read only area */
|
||||
int vpd_free_rw; /* bytes available in read/write area */
|
||||
} SK_VPD_STATUS;
|
||||
|
||||
typedef struct s_vpd {
|
||||
SK_VPD_STATUS v; /* VPD status structure */
|
||||
char vpd_buf[VPD_SIZE]; /* VPD buffer */
|
||||
int rom_size; /* VPD ROM Size from PCI_OUR_REG_2 */
|
||||
int vpd_size; /* saved VPD-size */
|
||||
} SK_VPD;
|
||||
|
||||
typedef struct s_vpd_para {
|
||||
unsigned int p_len; /* parameter length */
|
||||
char *p_val; /* points to the value */
|
||||
} SK_VPD_PARA;
|
||||
|
||||
/*
|
||||
* structure of Large Resource Type Identifiers
|
||||
*/
|
||||
|
||||
/* was removed because of alignment problems */
|
||||
|
||||
/*
|
||||
* structure of VPD keywords
|
||||
*/
|
||||
typedef struct s_vpd_key {
|
||||
char p_key[2]; /* 2 bytes ID string */
|
||||
unsigned char p_len; /* 1 byte length */
|
||||
char p_val; /* start of the value string */
|
||||
} SK_VPD_KEY;
|
||||
|
||||
|
||||
/*
|
||||
* System specific VPD macros
|
||||
*/
|
||||
#ifndef SKDIAG
|
||||
#ifndef VPD_DO_IO
|
||||
#define VPD_OUT8(pAC,IoC,Addr,Val) (void)SkPciWriteCfgByte(pAC,Addr,Val)
|
||||
#define VPD_OUT16(pAC,IoC,Addr,Val) (void)SkPciWriteCfgWord(pAC,Addr,Val)
|
||||
#define VPD_IN8(pAC,IoC,Addr,pVal) (void)SkPciReadCfgByte(pAC,Addr,pVal)
|
||||
#define VPD_IN16(pAC,IoC,Addr,pVal) (void)SkPciReadCfgWord(pAC,Addr,pVal)
|
||||
#define VPD_IN32(pAC,IoC,Addr,pVal) (void)SkPciReadCfgDWord(pAC,Addr,pVal)
|
||||
#else /* VPD_DO_IO */
|
||||
#define VPD_OUT8(pAC,IoC,Addr,Val) SK_OUT8(IoC,PCI_C(Addr),Val)
|
||||
#define VPD_OUT16(pAC,IoC,Addr,Val) SK_OUT16(IoC,PCI_C(Addr),Val)
|
||||
#define VPD_IN8(pAC,IoC,Addr,pVal) SK_IN8(IoC,PCI_C(Addr),pVal)
|
||||
#define VPD_IN16(pAC,IoC,Addr,pVal) SK_IN16(IoC,PCI_C(Addr),pVal)
|
||||
#define VPD_IN32(pAC,IoC,Addr,pVal) SK_IN32(IoC,PCI_C(Addr),pVal)
|
||||
#endif /* VPD_DO_IO */
|
||||
#else /* SKDIAG */
|
||||
#define VPD_OUT8(pAC,Ioc,Addr,Val) { \
|
||||
if ((pAC)->DgT.DgUseCfgCycle) \
|
||||
SkPciWriteCfgByte(pAC,Addr,Val); \
|
||||
else \
|
||||
SK_OUT8(pAC,PCI_C(Addr),Val); \
|
||||
}
|
||||
#define VPD_OUT16(pAC,Ioc,Addr,Val) { \
|
||||
if ((pAC)->DgT.DgUseCfgCycle) \
|
||||
SkPciWriteCfgWord(pAC,Addr,Val); \
|
||||
else \
|
||||
SK_OUT16(pAC,PCI_C(Addr),Val); \
|
||||
}
|
||||
#define VPD_IN8(pAC,Ioc,Addr,pVal) { \
|
||||
if ((pAC)->DgT.DgUseCfgCycle) \
|
||||
SkPciReadCfgByte(pAC,Addr,pVal); \
|
||||
else \
|
||||
SK_IN8(pAC,PCI_C(Addr),pVal); \
|
||||
}
|
||||
#define VPD_IN16(pAC,Ioc,Addr,pVal) { \
|
||||
if ((pAC)->DgT.DgUseCfgCycle) \
|
||||
SkPciReadCfgWord(pAC,Addr,pVal); \
|
||||
else \
|
||||
SK_IN16(pAC,PCI_C(Addr),pVal); \
|
||||
}
|
||||
#define VPD_IN32(pAC,Ioc,Addr,pVal) { \
|
||||
if ((pAC)->DgT.DgUseCfgCycle) \
|
||||
SkPciReadCfgDWord(pAC,Addr,pVal); \
|
||||
else \
|
||||
SK_IN32(pAC,PCI_C(Addr),pVal); \
|
||||
}
|
||||
#endif /* nSKDIAG */
|
||||
|
||||
/* function prototypes ********************************************************/
|
||||
|
||||
#ifndef SK_KR_PROTO
|
||||
#ifdef SKDIAG
|
||||
extern SK_U32 VpdReadDWord(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
int addr);
|
||||
#endif /* SKDIAG */
|
||||
|
||||
extern SK_VPD_STATUS *VpdStat(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC);
|
||||
|
||||
extern int VpdKeys(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
char *buf,
|
||||
int *len,
|
||||
int *elements);
|
||||
|
||||
extern int VpdRead(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
const char *key,
|
||||
char *buf,
|
||||
int *len);
|
||||
|
||||
extern SK_BOOL VpdMayWrite(
|
||||
char *key);
|
||||
|
||||
extern int VpdWrite(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
const char *key,
|
||||
const char *buf);
|
||||
|
||||
extern int VpdDelete(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
char *key);
|
||||
|
||||
extern int VpdUpdate(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC);
|
||||
|
||||
#ifdef SKDIAG
|
||||
extern int VpdReadBlock(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
char *buf,
|
||||
int addr,
|
||||
int len);
|
||||
|
||||
extern int VpdWriteBlock(
|
||||
SK_AC *pAC,
|
||||
SK_IOC IoC,
|
||||
char *buf,
|
||||
int addr,
|
||||
int len);
|
||||
#endif /* SKDIAG */
|
||||
#else /* SK_KR_PROTO */
|
||||
extern SK_U32 VpdReadDWord();
|
||||
extern SK_VPD_STATUS *VpdStat();
|
||||
extern int VpdKeys();
|
||||
extern int VpdRead();
|
||||
extern SK_BOOL VpdMayWrite();
|
||||
extern int VpdWrite();
|
||||
extern int VpdDelete();
|
||||
extern int VpdUpdate();
|
||||
#endif /* SK_KR_PROTO */
|
||||
|
||||
#endif /* __INC_SKVPD_H_ */
|
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
@ -1,742 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Name: skdim.c
|
||||
* Project: GEnesis, PCI Gigabit Ethernet Adapter
|
||||
* Version: $Revision: 1.5 $
|
||||
* Date: $Date: 2003/11/28 12:55:40 $
|
||||
* Purpose: All functions to maintain interrupt moderation
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* (C)Copyright 1998-2002 SysKonnect GmbH.
|
||||
* (C)Copyright 2002-2003 Marvell.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* The information in this file is provided "AS IS" without warranty.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Description:
|
||||
*
|
||||
* This module is intended to manage the dynamic interrupt moderation on both
|
||||
* GEnesis and Yukon adapters.
|
||||
*
|
||||
* Include File Hierarchy:
|
||||
*
|
||||
* "skdrv1st.h"
|
||||
* "skdrv2nd.h"
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef lint
|
||||
static const char SysKonnectFileId[] =
|
||||
"@(#) $Id: skdim.c,v 1.5 2003/11/28 12:55:40 rroesler Exp $ (C) SysKonnect.";
|
||||
#endif
|
||||
|
||||
#define __SKADDR_C
|
||||
|
||||
#ifdef __cplusplus
|
||||
#error C++ is not yet supported.
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
**
|
||||
** Includes
|
||||
**
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef __INC_SKDRV1ST_H
|
||||
#include "h/skdrv1st.h"
|
||||
#endif
|
||||
|
||||
#ifndef __INC_SKDRV2ND_H
|
||||
#include "h/skdrv2nd.h"
|
||||
#endif
|
||||
|
||||
#include <linux/kernel_stat.h>
|
||||
|
||||
/*******************************************************************************
|
||||
**
|
||||
** Defines
|
||||
**
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
**
|
||||
** Typedefs
|
||||
**
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
**
|
||||
** Local function prototypes
|
||||
**
|
||||
*******************************************************************************/
|
||||
|
||||
static unsigned int GetCurrentSystemLoad(SK_AC *pAC);
|
||||
static SK_U64 GetIsrCalls(SK_AC *pAC);
|
||||
static SK_BOOL IsIntModEnabled(SK_AC *pAC);
|
||||
static void SetCurrIntCtr(SK_AC *pAC);
|
||||
static void EnableIntMod(SK_AC *pAC);
|
||||
static void DisableIntMod(SK_AC *pAC);
|
||||
static void ResizeDimTimerDuration(SK_AC *pAC);
|
||||
static void DisplaySelectedModerationType(SK_AC *pAC);
|
||||
static void DisplaySelectedModerationMask(SK_AC *pAC);
|
||||
static void DisplayDescrRatio(SK_AC *pAC);
|
||||
|
||||
/*******************************************************************************
|
||||
**
|
||||
** Global variables
|
||||
**
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
**
|
||||
** Local variables
|
||||
**
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
**
|
||||
** Global functions
|
||||
**
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
** Function : SkDimModerate
|
||||
** Description : Called in every ISR to check if moderation is to be applied
|
||||
** or not for the current number of interrupts
|
||||
** Programmer : Ralph Roesler
|
||||
** Last Modified: 22-mar-03
|
||||
** Returns : void (!)
|
||||
** Notes : -
|
||||
*******************************************************************************/
|
||||
|
||||
void
|
||||
SkDimModerate(SK_AC *pAC) {
|
||||
unsigned int CurrSysLoad = 0; /* expressed in percent */
|
||||
unsigned int LoadIncrease = 0; /* expressed in percent */
|
||||
SK_U64 ThresholdInts = 0;
|
||||
SK_U64 IsrCallsPerSec = 0;
|
||||
|
||||
#define M_DIMINFO pAC->DynIrqModInfo
|
||||
|
||||
if (!IsIntModEnabled(pAC)) {
|
||||
if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
|
||||
CurrSysLoad = GetCurrentSystemLoad(pAC);
|
||||
if (CurrSysLoad > 75) {
|
||||
/*
|
||||
** More than 75% total system load! Enable the moderation
|
||||
** to shield the system against too many interrupts.
|
||||
*/
|
||||
EnableIntMod(pAC);
|
||||
} else if (CurrSysLoad > M_DIMINFO.PrevSysLoad) {
|
||||
LoadIncrease = (CurrSysLoad - M_DIMINFO.PrevSysLoad);
|
||||
if (LoadIncrease > ((M_DIMINFO.PrevSysLoad *
|
||||
C_INT_MOD_ENABLE_PERCENTAGE) / 100)) {
|
||||
if (CurrSysLoad > 10) {
|
||||
/*
|
||||
** More than 50% increase with respect to the
|
||||
** previous load of the system. Most likely this
|
||||
** is due to our ISR-proc...
|
||||
*/
|
||||
EnableIntMod(pAC);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
/*
|
||||
** Neither too much system load at all nor too much increase
|
||||
** with respect to the previous system load. Hence, we can leave
|
||||
** the ISR-handling like it is without enabling moderation.
|
||||
*/
|
||||
}
|
||||
M_DIMINFO.PrevSysLoad = CurrSysLoad;
|
||||
}
|
||||
} else {
|
||||
if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
|
||||
ThresholdInts = ((M_DIMINFO.MaxModIntsPerSec *
|
||||
C_INT_MOD_DISABLE_PERCENTAGE) / 100);
|
||||
IsrCallsPerSec = GetIsrCalls(pAC);
|
||||
if (IsrCallsPerSec <= ThresholdInts) {
|
||||
/*
|
||||
** The number of interrupts within the last second is
|
||||
** lower than the disable_percentage of the desried
|
||||
** maxrate. Therefore we can disable the moderation.
|
||||
*/
|
||||
DisableIntMod(pAC);
|
||||
M_DIMINFO.MaxModIntsPerSec =
|
||||
(M_DIMINFO.MaxModIntsPerSecUpperLimit +
|
||||
M_DIMINFO.MaxModIntsPerSecLowerLimit) / 2;
|
||||
} else {
|
||||
/*
|
||||
** The number of interrupts per sec is the same as expected.
|
||||
** Evalulate the descriptor-ratio. If it has changed, a resize
|
||||
** in the moderation timer might be useful
|
||||
*/
|
||||
if (M_DIMINFO.AutoSizing) {
|
||||
ResizeDimTimerDuration(pAC);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
** Some information to the log...
|
||||
*/
|
||||
if (M_DIMINFO.DisplayStats) {
|
||||
DisplaySelectedModerationType(pAC);
|
||||
DisplaySelectedModerationMask(pAC);
|
||||
DisplayDescrRatio(pAC);
|
||||
}
|
||||
|
||||
M_DIMINFO.NbrProcessedDescr = 0;
|
||||
SetCurrIntCtr(pAC);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
** Function : SkDimStartModerationTimer
|
||||
** Description : Starts the audit-timer for the dynamic interrupt moderation
|
||||
** Programmer : Ralph Roesler
|
||||
** Last Modified: 22-mar-03
|
||||
** Returns : void (!)
|
||||
** Notes : -
|
||||
*******************************************************************************/
|
||||
|
||||
void
|
||||
SkDimStartModerationTimer(SK_AC *pAC) {
|
||||
SK_EVPARA EventParam; /* Event struct for timer event */
|
||||
|
||||
SK_MEMSET((char *) &EventParam, 0, sizeof(EventParam));
|
||||
EventParam.Para32[0] = SK_DRV_MODERATION_TIMER;
|
||||
SkTimerStart(pAC, pAC->IoBase, &pAC->DynIrqModInfo.ModTimer,
|
||||
SK_DRV_MODERATION_TIMER_LENGTH,
|
||||
SKGE_DRV, SK_DRV_TIMER, EventParam);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
** Function : SkDimEnableModerationIfNeeded
|
||||
** Description : Either enables or disables moderation
|
||||
** Programmer : Ralph Roesler
|
||||
** Last Modified: 22-mar-03
|
||||
** Returns : void (!)
|
||||
** Notes : This function is called when a particular adapter is opened
|
||||
** There is no Disable function, because when all interrupts
|
||||
** might be disable, the moderation timer has no meaning at all
|
||||
******************************************************************************/
|
||||
|
||||
void
|
||||
SkDimEnableModerationIfNeeded(SK_AC *pAC) {
|
||||
|
||||
if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_STATIC) {
|
||||
EnableIntMod(pAC); /* notification print in this function */
|
||||
} else if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
|
||||
SkDimStartModerationTimer(pAC);
|
||||
if (M_DIMINFO.DisplayStats) {
|
||||
printk("Dynamic moderation has been enabled\n");
|
||||
}
|
||||
} else {
|
||||
if (M_DIMINFO.DisplayStats) {
|
||||
printk("No moderation has been enabled\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
** Function : SkDimDisplayModerationSettings
|
||||
** Description : Displays the current settings regarding interrupt moderation
|
||||
** Programmer : Ralph Roesler
|
||||
** Last Modified: 22-mar-03
|
||||
** Returns : void (!)
|
||||
** Notes : -
|
||||
*******************************************************************************/
|
||||
|
||||
void
|
||||
SkDimDisplayModerationSettings(SK_AC *pAC) {
|
||||
DisplaySelectedModerationType(pAC);
|
||||
DisplaySelectedModerationMask(pAC);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
**
|
||||
** Local functions
|
||||
**
|
||||
*******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
** Function : GetCurrentSystemLoad
|
||||
** Description : Retrieves the current system load of the system. This load
|
||||
** is evaluated for all processors within the system.
|
||||
** Programmer : Ralph Roesler
|
||||
** Last Modified: 22-mar-03
|
||||
** Returns : unsigned int: load expressed in percentage
|
||||
** Notes : The possible range being returned is from 0 up to 100.
|
||||
** Whereas 0 means 'no load at all' and 100 'system fully loaded'
|
||||
** It is impossible to determine what actually causes the system
|
||||
** to be in 100%, but maybe that is due to too much interrupts.
|
||||
*******************************************************************************/
|
||||
|
||||
static unsigned int
|
||||
GetCurrentSystemLoad(SK_AC *pAC) {
|
||||
unsigned long jif = jiffies;
|
||||
unsigned int UserTime = 0;
|
||||
unsigned int SystemTime = 0;
|
||||
unsigned int NiceTime = 0;
|
||||
unsigned int IdleTime = 0;
|
||||
unsigned int TotalTime = 0;
|
||||
unsigned int UsedTime = 0;
|
||||
unsigned int SystemLoad = 0;
|
||||
|
||||
/* unsigned int NbrCpu = 0; */
|
||||
|
||||
/*
|
||||
** The following lines have been commented out, because
|
||||
** from kernel 2.5.44 onwards, the kernel-owned structure
|
||||
**
|
||||
** struct kernel_stat kstat
|
||||
**
|
||||
** is not marked as an exported symbol in the file
|
||||
**
|
||||
** kernel/ksyms.c
|
||||
**
|
||||
** As a consequence, using this driver as KLM is not possible
|
||||
** and any access of the structure kernel_stat via the
|
||||
** dedicated macros kstat_cpu(i).cpustat.xxx is to be avoided.
|
||||
**
|
||||
** The kstat-information might be added again in future
|
||||
** versions of the 2.5.xx kernel, but for the time being,
|
||||
** number of interrupts will serve as indication how much
|
||||
** load we currently have...
|
||||
**
|
||||
** for (NbrCpu = 0; NbrCpu < num_online_cpus(); NbrCpu++) {
|
||||
** UserTime = UserTime + kstat_cpu(NbrCpu).cpustat.user;
|
||||
** NiceTime = NiceTime + kstat_cpu(NbrCpu).cpustat.nice;
|
||||
** SystemTime = SystemTime + kstat_cpu(NbrCpu).cpustat.system;
|
||||
** }
|
||||
*/
|
||||
SK_U64 ThresholdInts = 0;
|
||||
SK_U64 IsrCallsPerSec = 0;
|
||||
|
||||
ThresholdInts = ((M_DIMINFO.MaxModIntsPerSec *
|
||||
C_INT_MOD_ENABLE_PERCENTAGE) + 100);
|
||||
IsrCallsPerSec = GetIsrCalls(pAC);
|
||||
if (IsrCallsPerSec >= ThresholdInts) {
|
||||
/*
|
||||
** We do not know how much the real CPU-load is!
|
||||
** Return 80% as a default in order to activate DIM
|
||||
*/
|
||||
SystemLoad = 80;
|
||||
return (SystemLoad);
|
||||
}
|
||||
|
||||
UsedTime = UserTime + NiceTime + SystemTime;
|
||||
|
||||
IdleTime = jif * num_online_cpus() - UsedTime;
|
||||
TotalTime = UsedTime + IdleTime;
|
||||
|
||||
SystemLoad = ( 100 * (UsedTime - M_DIMINFO.PrevUsedTime) ) /
|
||||
(TotalTime - M_DIMINFO.PrevTotalTime);
|
||||
|
||||
if (M_DIMINFO.DisplayStats) {
|
||||
printk("Current system load is: %u\n", SystemLoad);
|
||||
}
|
||||
|
||||
M_DIMINFO.PrevTotalTime = TotalTime;
|
||||
M_DIMINFO.PrevUsedTime = UsedTime;
|
||||
|
||||
return (SystemLoad);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
** Function : GetIsrCalls
|
||||
** Description : Depending on the selected moderation mask, this function will
|
||||
** return the number of interrupts handled in the previous time-
|
||||
** frame. This evaluated number is based on the current number
|
||||
** of interrupts stored in PNMI-context and the previous stored
|
||||
** interrupts.
|
||||
** Programmer : Ralph Roesler
|
||||
** Last Modified: 23-mar-03
|
||||
** Returns : int: the number of interrupts being executed in the last
|
||||
** timeframe
|
||||
** Notes : It makes only sense to call this function, when dynamic
|
||||
** interrupt moderation is applied
|
||||
*******************************************************************************/
|
||||
|
||||
static SK_U64
|
||||
GetIsrCalls(SK_AC *pAC) {
|
||||
SK_U64 RxPort0IntDiff = 0;
|
||||
SK_U64 RxPort1IntDiff = 0;
|
||||
SK_U64 TxPort0IntDiff = 0;
|
||||
SK_U64 TxPort1IntDiff = 0;
|
||||
|
||||
if (pAC->DynIrqModInfo.MaskIrqModeration == IRQ_MASK_TX_ONLY) {
|
||||
if (pAC->GIni.GIMacsFound == 2) {
|
||||
TxPort1IntDiff = pAC->Pnmi.Port[1].TxIntrCts -
|
||||
pAC->DynIrqModInfo.PrevPort1TxIntrCts;
|
||||
}
|
||||
TxPort0IntDiff = pAC->Pnmi.Port[0].TxIntrCts -
|
||||
pAC->DynIrqModInfo.PrevPort0TxIntrCts;
|
||||
} else if (pAC->DynIrqModInfo.MaskIrqModeration == IRQ_MASK_RX_ONLY) {
|
||||
if (pAC->GIni.GIMacsFound == 2) {
|
||||
RxPort1IntDiff = pAC->Pnmi.Port[1].RxIntrCts -
|
||||
pAC->DynIrqModInfo.PrevPort1RxIntrCts;
|
||||
}
|
||||
RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts -
|
||||
pAC->DynIrqModInfo.PrevPort0RxIntrCts;
|
||||
} else {
|
||||
if (pAC->GIni.GIMacsFound == 2) {
|
||||
RxPort1IntDiff = pAC->Pnmi.Port[1].RxIntrCts -
|
||||
pAC->DynIrqModInfo.PrevPort1RxIntrCts;
|
||||
TxPort1IntDiff = pAC->Pnmi.Port[1].TxIntrCts -
|
||||
pAC->DynIrqModInfo.PrevPort1TxIntrCts;
|
||||
}
|
||||
RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts -
|
||||
pAC->DynIrqModInfo.PrevPort0RxIntrCts;
|
||||
TxPort0IntDiff = pAC->Pnmi.Port[0].TxIntrCts -
|
||||
pAC->DynIrqModInfo.PrevPort0TxIntrCts;
|
||||
}
|
||||
|
||||
return (RxPort0IntDiff + RxPort1IntDiff + TxPort0IntDiff + TxPort1IntDiff);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
** Function : GetRxCalls
|
||||
** Description : This function will return the number of times a receive inter-
|
||||
** rupt was processed. This is needed to evaluate any resizing
|
||||
** factor.
|
||||
** Programmer : Ralph Roesler
|
||||
** Last Modified: 23-mar-03
|
||||
** Returns : SK_U64: the number of RX-ints being processed
|
||||
** Notes : It makes only sense to call this function, when dynamic
|
||||
** interrupt moderation is applied
|
||||
*******************************************************************************/
|
||||
|
||||
static SK_U64
|
||||
GetRxCalls(SK_AC *pAC) {
|
||||
SK_U64 RxPort0IntDiff = 0;
|
||||
SK_U64 RxPort1IntDiff = 0;
|
||||
|
||||
if (pAC->GIni.GIMacsFound == 2) {
|
||||
RxPort1IntDiff = pAC->Pnmi.Port[1].RxIntrCts -
|
||||
pAC->DynIrqModInfo.PrevPort1RxIntrCts;
|
||||
}
|
||||
RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts -
|
||||
pAC->DynIrqModInfo.PrevPort0RxIntrCts;
|
||||
|
||||
return (RxPort0IntDiff + RxPort1IntDiff);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
** Function : SetCurrIntCtr
|
||||
** Description : Will store the current number orf occured interrupts in the
|
||||
** adapter context. This is needed to evaluated the number of
|
||||
** interrupts within a current timeframe.
|
||||
** Programmer : Ralph Roesler
|
||||
** Last Modified: 23-mar-03
|
||||
** Returns : void (!)
|
||||
** Notes : -
|
||||
*******************************************************************************/
|
||||
|
||||
static void
|
||||
SetCurrIntCtr(SK_AC *pAC) {
|
||||
if (pAC->GIni.GIMacsFound == 2) {
|
||||
pAC->DynIrqModInfo.PrevPort1RxIntrCts = pAC->Pnmi.Port[1].RxIntrCts;
|
||||
pAC->DynIrqModInfo.PrevPort1TxIntrCts = pAC->Pnmi.Port[1].TxIntrCts;
|
||||
}
|
||||
pAC->DynIrqModInfo.PrevPort0RxIntrCts = pAC->Pnmi.Port[0].RxIntrCts;
|
||||
pAC->DynIrqModInfo.PrevPort0TxIntrCts = pAC->Pnmi.Port[0].TxIntrCts;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
** Function : IsIntModEnabled()
|
||||
** Description : Retrieves the current value of the interrupts moderation
|
||||
** command register. Its content determines whether any
|
||||
** moderation is running or not.
|
||||
** Programmer : Ralph Roesler
|
||||
** Last Modified: 23-mar-03
|
||||
** Returns : SK_TRUE : if mod timer running
|
||||
** SK_FALSE : if no moderation is being performed
|
||||
** Notes : -
|
||||
*******************************************************************************/
|
||||
|
||||
static SK_BOOL
|
||||
IsIntModEnabled(SK_AC *pAC) {
|
||||
unsigned long CtrCmd;
|
||||
|
||||
SK_IN32(pAC->IoBase, B2_IRQM_CTRL, &CtrCmd);
|
||||
if ((CtrCmd & TIM_START) == TIM_START) {
|
||||
return SK_TRUE;
|
||||
} else {
|
||||
return SK_FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
** Function : EnableIntMod()
|
||||
** Description : Enables the interrupt moderation using the values stored in
|
||||
** in the pAC->DynIntMod data structure
|
||||
** Programmer : Ralph Roesler
|
||||
** Last Modified: 22-mar-03
|
||||
** Returns : -
|
||||
** Notes : -
|
||||
*******************************************************************************/
|
||||
|
||||
static void
|
||||
EnableIntMod(SK_AC *pAC) {
|
||||
unsigned long ModBase;
|
||||
|
||||
if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
|
||||
ModBase = C_CLK_FREQ_GENESIS / pAC->DynIrqModInfo.MaxModIntsPerSec;
|
||||
} else {
|
||||
ModBase = C_CLK_FREQ_YUKON / pAC->DynIrqModInfo.MaxModIntsPerSec;
|
||||
}
|
||||
|
||||
SK_OUT32(pAC->IoBase, B2_IRQM_INI, ModBase);
|
||||
SK_OUT32(pAC->IoBase, B2_IRQM_MSK, pAC->DynIrqModInfo.MaskIrqModeration);
|
||||
SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_START);
|
||||
if (M_DIMINFO.DisplayStats) {
|
||||
printk("Enabled interrupt moderation (%i ints/sec)\n",
|
||||
M_DIMINFO.MaxModIntsPerSec);
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
** Function : DisableIntMod()
|
||||
** Description : Disables the interrupt moderation independent of what inter-
|
||||
** rupts are running or not
|
||||
** Programmer : Ralph Roesler
|
||||
** Last Modified: 23-mar-03
|
||||
** Returns : -
|
||||
** Notes : -
|
||||
*******************************************************************************/
|
||||
|
||||
static void
|
||||
DisableIntMod(SK_AC *pAC) {
|
||||
|
||||
SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_STOP);
|
||||
if (M_DIMINFO.DisplayStats) {
|
||||
printk("Disabled interrupt moderation\n");
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
** Function : ResizeDimTimerDuration();
|
||||
** Description : Checks the current used descriptor ratio and resizes the
|
||||
** duration timer (longer/smaller) if possible.
|
||||
** Programmer : Ralph Roesler
|
||||
** Last Modified: 23-mar-03
|
||||
** Returns : -
|
||||
** Notes : There are both maximum and minimum timer duration value.
|
||||
** This function assumes that interrupt moderation is already
|
||||
** enabled!
|
||||
*******************************************************************************/
|
||||
|
||||
static void
|
||||
ResizeDimTimerDuration(SK_AC *pAC) {
|
||||
SK_BOOL IncreaseTimerDuration;
|
||||
int TotalMaxNbrDescr;
|
||||
int UsedDescrRatio;
|
||||
int RatioDiffAbs;
|
||||
int RatioDiffRel;
|
||||
int NewMaxModIntsPerSec;
|
||||
int ModAdjValue;
|
||||
long ModBase;
|
||||
|
||||
/*
|
||||
** Check first if we are allowed to perform any modification
|
||||
*/
|
||||
if (IsIntModEnabled(pAC)) {
|
||||
if (M_DIMINFO.IntModTypeSelect != C_INT_MOD_DYNAMIC) {
|
||||
return;
|
||||
} else {
|
||||
if (M_DIMINFO.ModJustEnabled) {
|
||||
M_DIMINFO.ModJustEnabled = SK_FALSE;
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
** If we got until here, we have to evaluate the amount of the
|
||||
** descriptor ratio change...
|
||||
*/
|
||||
TotalMaxNbrDescr = pAC->RxDescrPerRing * GetRxCalls(pAC);
|
||||
UsedDescrRatio = (M_DIMINFO.NbrProcessedDescr * 100) / TotalMaxNbrDescr;
|
||||
|
||||
if (UsedDescrRatio > M_DIMINFO.PrevUsedDescrRatio) {
|
||||
RatioDiffAbs = (UsedDescrRatio - M_DIMINFO.PrevUsedDescrRatio);
|
||||
RatioDiffRel = (RatioDiffAbs * 100) / UsedDescrRatio;
|
||||
M_DIMINFO.PrevUsedDescrRatio = UsedDescrRatio;
|
||||
IncreaseTimerDuration = SK_FALSE; /* in other words: DECREASE */
|
||||
} else if (UsedDescrRatio < M_DIMINFO.PrevUsedDescrRatio) {
|
||||
RatioDiffAbs = (M_DIMINFO.PrevUsedDescrRatio - UsedDescrRatio);
|
||||
RatioDiffRel = (RatioDiffAbs * 100) / M_DIMINFO.PrevUsedDescrRatio;
|
||||
M_DIMINFO.PrevUsedDescrRatio = UsedDescrRatio;
|
||||
IncreaseTimerDuration = SK_TRUE; /* in other words: INCREASE */
|
||||
} else {
|
||||
RatioDiffAbs = (M_DIMINFO.PrevUsedDescrRatio - UsedDescrRatio);
|
||||
RatioDiffRel = (RatioDiffAbs * 100) / M_DIMINFO.PrevUsedDescrRatio;
|
||||
M_DIMINFO.PrevUsedDescrRatio = UsedDescrRatio;
|
||||
IncreaseTimerDuration = SK_TRUE; /* in other words: INCREASE */
|
||||
}
|
||||
|
||||
/*
|
||||
** Now we can determine the change in percent
|
||||
*/
|
||||
if ((RatioDiffRel >= 0) && (RatioDiffRel <= 5) ) {
|
||||
ModAdjValue = 1; /* 1% change - maybe some other value in future */
|
||||
} else if ((RatioDiffRel > 5) && (RatioDiffRel <= 10) ) {
|
||||
ModAdjValue = 1; /* 1% change - maybe some other value in future */
|
||||
} else if ((RatioDiffRel > 10) && (RatioDiffRel <= 15) ) {
|
||||
ModAdjValue = 1; /* 1% change - maybe some other value in future */
|
||||
} else {
|
||||
ModAdjValue = 1; /* 1% change - maybe some other value in future */
|
||||
}
|
||||
|
||||
if (IncreaseTimerDuration) {
|
||||
NewMaxModIntsPerSec = M_DIMINFO.MaxModIntsPerSec +
|
||||
(M_DIMINFO.MaxModIntsPerSec * ModAdjValue) / 100;
|
||||
} else {
|
||||
NewMaxModIntsPerSec = M_DIMINFO.MaxModIntsPerSec -
|
||||
(M_DIMINFO.MaxModIntsPerSec * ModAdjValue) / 100;
|
||||
}
|
||||
|
||||
/*
|
||||
** Check if we exceed boundaries...
|
||||
*/
|
||||
if ( (NewMaxModIntsPerSec > M_DIMINFO.MaxModIntsPerSecUpperLimit) ||
|
||||
(NewMaxModIntsPerSec < M_DIMINFO.MaxModIntsPerSecLowerLimit)) {
|
||||
if (M_DIMINFO.DisplayStats) {
|
||||
printk("Cannot change ModTim from %i to %i ints/sec\n",
|
||||
M_DIMINFO.MaxModIntsPerSec, NewMaxModIntsPerSec);
|
||||
}
|
||||
return;
|
||||
} else {
|
||||
if (M_DIMINFO.DisplayStats) {
|
||||
printk("Resized ModTim from %i to %i ints/sec\n",
|
||||
M_DIMINFO.MaxModIntsPerSec, NewMaxModIntsPerSec);
|
||||
}
|
||||
}
|
||||
|
||||
M_DIMINFO.MaxModIntsPerSec = NewMaxModIntsPerSec;
|
||||
|
||||
if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
|
||||
ModBase = C_CLK_FREQ_GENESIS / pAC->DynIrqModInfo.MaxModIntsPerSec;
|
||||
} else {
|
||||
ModBase = C_CLK_FREQ_YUKON / pAC->DynIrqModInfo.MaxModIntsPerSec;
|
||||
}
|
||||
|
||||
/*
|
||||
** We do not need to touch any other registers
|
||||
*/
|
||||
SK_OUT32(pAC->IoBase, B2_IRQM_INI, ModBase);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
** Function : DisplaySelectedModerationType()
|
||||
** Description : Displays what type of moderation we have
|
||||
** Programmer : Ralph Roesler
|
||||
** Last Modified: 23-mar-03
|
||||
** Returns : void!
|
||||
** Notes : -
|
||||
*******************************************************************************/
|
||||
|
||||
static void
|
||||
DisplaySelectedModerationType(SK_AC *pAC) {
|
||||
|
||||
if (pAC->DynIrqModInfo.DisplayStats) {
|
||||
if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_STATIC) {
|
||||
printk("Static int moderation runs with %i INTS/sec\n",
|
||||
pAC->DynIrqModInfo.MaxModIntsPerSec);
|
||||
} else if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
|
||||
if (IsIntModEnabled(pAC)) {
|
||||
printk("Dynamic int moderation runs with %i INTS/sec\n",
|
||||
pAC->DynIrqModInfo.MaxModIntsPerSec);
|
||||
} else {
|
||||
printk("Dynamic int moderation currently not applied\n");
|
||||
}
|
||||
} else {
|
||||
printk("No interrupt moderation selected!\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
** Function : DisplaySelectedModerationMask()
|
||||
** Description : Displays what interrupts are moderated
|
||||
** Programmer : Ralph Roesler
|
||||
** Last Modified: 23-mar-03
|
||||
** Returns : void!
|
||||
** Notes : -
|
||||
*******************************************************************************/
|
||||
|
||||
static void
|
||||
DisplaySelectedModerationMask(SK_AC *pAC) {
|
||||
|
||||
if (pAC->DynIrqModInfo.DisplayStats) {
|
||||
if (pAC->DynIrqModInfo.IntModTypeSelect != C_INT_MOD_NONE) {
|
||||
switch (pAC->DynIrqModInfo.MaskIrqModeration) {
|
||||
case IRQ_MASK_TX_ONLY:
|
||||
printk("Only Tx-interrupts are moderated\n");
|
||||
break;
|
||||
case IRQ_MASK_RX_ONLY:
|
||||
printk("Only Rx-interrupts are moderated\n");
|
||||
break;
|
||||
case IRQ_MASK_SP_ONLY:
|
||||
printk("Only special-interrupts are moderated\n");
|
||||
break;
|
||||
case IRQ_MASK_TX_RX:
|
||||
printk("Tx- and Rx-interrupts are moderated\n");
|
||||
break;
|
||||
case IRQ_MASK_SP_RX:
|
||||
printk("Special- and Rx-interrupts are moderated\n");
|
||||
break;
|
||||
case IRQ_MASK_SP_TX:
|
||||
printk("Special- and Tx-interrupts are moderated\n");
|
||||
break;
|
||||
case IRQ_MASK_RX_TX_SP:
|
||||
printk("All Rx-, Tx and special-interrupts are moderated\n");
|
||||
break;
|
||||
default:
|
||||
printk("Don't know what is moderated\n");
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
printk("No specific interrupts masked for moderation\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
** Function : DisplayDescrRatio
|
||||
** Description : Like the name states...
|
||||
** Programmer : Ralph Roesler
|
||||
** Last Modified: 23-mar-03
|
||||
** Returns : void!
|
||||
** Notes : -
|
||||
*******************************************************************************/
|
||||
|
||||
static void
|
||||
DisplayDescrRatio(SK_AC *pAC) {
|
||||
int TotalMaxNbrDescr = 0;
|
||||
|
||||
if (pAC->DynIrqModInfo.DisplayStats) {
|
||||
TotalMaxNbrDescr = pAC->RxDescrPerRing * GetRxCalls(pAC);
|
||||
printk("Ratio descriptors: %i/%i\n",
|
||||
M_DIMINFO.NbrProcessedDescr, TotalMaxNbrDescr);
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
**
|
||||
** End of file
|
||||
**
|
||||
*******************************************************************************/
|
|
@ -1,627 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Name: skethtool.c
|
||||
* Project: GEnesis, PCI Gigabit Ethernet Adapter
|
||||
* Version: $Revision: 1.7 $
|
||||
* Date: $Date: 2004/09/29 13:32:07 $
|
||||
* Purpose: All functions regarding ethtool handling
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* (C)Copyright 1998-2002 SysKonnect GmbH.
|
||||
* (C)Copyright 2002-2004 Marvell.
|
||||
*
|
||||
* Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet
|
||||
* Server Adapters.
|
||||
*
|
||||
* Author: Ralph Roesler (rroesler@syskonnect.de)
|
||||
* Mirko Lindner (mlindner@syskonnect.de)
|
||||
*
|
||||
* Address all question to: linux@syskonnect.de
|
||||
*
|
||||
* The technical manual for the adapters is available from SysKonnect's
|
||||
* web pages: www.syskonnect.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* The information in this file is provided "AS IS" without warranty.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#include "h/skdrv1st.h"
|
||||
#include "h/skdrv2nd.h"
|
||||
#include "h/skversion.h"
|
||||
|
||||
#include <linux/ethtool.h>
|
||||
#include <linux/timer.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Defines
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#define SUPP_COPPER_ALL (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
|
||||
SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
|
||||
SUPPORTED_1000baseT_Half| SUPPORTED_1000baseT_Full| \
|
||||
SUPPORTED_TP)
|
||||
|
||||
#define ADV_COPPER_ALL (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
|
||||
ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
|
||||
ADVERTISED_1000baseT_Half| ADVERTISED_1000baseT_Full| \
|
||||
ADVERTISED_TP)
|
||||
|
||||
#define SUPP_FIBRE_ALL (SUPPORTED_1000baseT_Full | \
|
||||
SUPPORTED_FIBRE | \
|
||||
SUPPORTED_Autoneg)
|
||||
|
||||
#define ADV_FIBRE_ALL (ADVERTISED_1000baseT_Full | \
|
||||
ADVERTISED_FIBRE | \
|
||||
ADVERTISED_Autoneg)
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Local Functions
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
*
|
||||
* getSettings - retrieves the current settings of the selected adapter
|
||||
*
|
||||
* Description:
|
||||
* The current configuration of the selected adapter is returned.
|
||||
* This configuration involves a)speed, b)duplex and c)autoneg plus
|
||||
* a number of other variables.
|
||||
*
|
||||
* Returns: always 0
|
||||
*
|
||||
*/
|
||||
static int getSettings(struct net_device *dev, struct ethtool_cmd *ecmd)
|
||||
{
|
||||
const DEV_NET *pNet = netdev_priv(dev);
|
||||
int port = pNet->PortNr;
|
||||
const SK_AC *pAC = pNet->pAC;
|
||||
const SK_GEPORT *pPort = &pAC->GIni.GP[port];
|
||||
|
||||
static int DuplexAutoNegConfMap[9][3]= {
|
||||
{ -1 , -1 , -1 },
|
||||
{ 0 , -1 , -1 },
|
||||
{ SK_LMODE_HALF , DUPLEX_HALF, AUTONEG_DISABLE },
|
||||
{ SK_LMODE_FULL , DUPLEX_FULL, AUTONEG_DISABLE },
|
||||
{ SK_LMODE_AUTOHALF , DUPLEX_HALF, AUTONEG_ENABLE },
|
||||
{ SK_LMODE_AUTOFULL , DUPLEX_FULL, AUTONEG_ENABLE },
|
||||
{ SK_LMODE_AUTOBOTH , DUPLEX_FULL, AUTONEG_ENABLE },
|
||||
{ SK_LMODE_AUTOSENSE , -1 , -1 },
|
||||
{ SK_LMODE_INDETERMINATED, -1 , -1 }
|
||||
};
|
||||
static int SpeedConfMap[6][2] = {
|
||||
{ 0 , -1 },
|
||||
{ SK_LSPEED_AUTO , -1 },
|
||||
{ SK_LSPEED_10MBPS , SPEED_10 },
|
||||
{ SK_LSPEED_100MBPS , SPEED_100 },
|
||||
{ SK_LSPEED_1000MBPS , SPEED_1000 },
|
||||
{ SK_LSPEED_INDETERMINATED, -1 }
|
||||
};
|
||||
static int AdvSpeedMap[6][2] = {
|
||||
{ 0 , -1 },
|
||||
{ SK_LSPEED_AUTO , -1 },
|
||||
{ SK_LSPEED_10MBPS , ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full },
|
||||
{ SK_LSPEED_100MBPS , ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full },
|
||||
{ SK_LSPEED_1000MBPS , ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full},
|
||||
{ SK_LSPEED_INDETERMINATED, -1 }
|
||||
};
|
||||
|
||||
ecmd->phy_address = port;
|
||||
ecmd->speed = SpeedConfMap[pPort->PLinkSpeedUsed][1];
|
||||
ecmd->duplex = DuplexAutoNegConfMap[pPort->PLinkModeStatus][1];
|
||||
ecmd->autoneg = DuplexAutoNegConfMap[pPort->PLinkModeStatus][2];
|
||||
ecmd->transceiver = XCVR_INTERNAL;
|
||||
|
||||
if (pAC->GIni.GICopperType) {
|
||||
ecmd->port = PORT_TP;
|
||||
ecmd->supported = (SUPP_COPPER_ALL|SUPPORTED_Autoneg);
|
||||
if (pAC->GIni.GIGenesis) {
|
||||
ecmd->supported &= ~(SUPPORTED_10baseT_Half);
|
||||
ecmd->supported &= ~(SUPPORTED_10baseT_Full);
|
||||
ecmd->supported &= ~(SUPPORTED_100baseT_Half);
|
||||
ecmd->supported &= ~(SUPPORTED_100baseT_Full);
|
||||
} else {
|
||||
if (pAC->GIni.GIChipId == CHIP_ID_YUKON) {
|
||||
ecmd->supported &= ~(SUPPORTED_1000baseT_Half);
|
||||
}
|
||||
#ifdef CHIP_ID_YUKON_FE
|
||||
if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) {
|
||||
ecmd->supported &= ~(SUPPORTED_1000baseT_Half);
|
||||
ecmd->supported &= ~(SUPPORTED_1000baseT_Full);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
if (pAC->GIni.GP[0].PLinkSpeed != SK_LSPEED_AUTO) {
|
||||
ecmd->advertising = AdvSpeedMap[pPort->PLinkSpeed][1];
|
||||
if (pAC->GIni.GIChipId == CHIP_ID_YUKON) {
|
||||
ecmd->advertising &= ~(SUPPORTED_1000baseT_Half);
|
||||
}
|
||||
} else {
|
||||
ecmd->advertising = ecmd->supported;
|
||||
}
|
||||
|
||||
if (ecmd->autoneg == AUTONEG_ENABLE)
|
||||
ecmd->advertising |= ADVERTISED_Autoneg;
|
||||
} else {
|
||||
ecmd->port = PORT_FIBRE;
|
||||
ecmd->supported = SUPP_FIBRE_ALL;
|
||||
ecmd->advertising = ADV_FIBRE_ALL;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* MIB infrastructure uses instance value starting at 1
|
||||
* based on board and port.
|
||||
*/
|
||||
static inline u32 pnmiInstance(const DEV_NET *pNet)
|
||||
{
|
||||
return 1 + (pNet->pAC->RlmtNets == 2) + pNet->PortNr;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
*
|
||||
* setSettings - configures the settings of a selected adapter
|
||||
*
|
||||
* Description:
|
||||
* Possible settings that may be altered are a)speed, b)duplex or
|
||||
* c)autonegotiation.
|
||||
*
|
||||
* Returns:
|
||||
* 0: everything fine, no error
|
||||
* <0: the return value is the error code of the failure
|
||||
*/
|
||||
static int setSettings(struct net_device *dev, struct ethtool_cmd *ecmd)
|
||||
{
|
||||
DEV_NET *pNet = netdev_priv(dev);
|
||||
SK_AC *pAC = pNet->pAC;
|
||||
u32 instance;
|
||||
char buf[4];
|
||||
int len = 1;
|
||||
|
||||
if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100
|
||||
&& ecmd->speed != SPEED_1000)
|
||||
return -EINVAL;
|
||||
|
||||
if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
|
||||
return -EINVAL;
|
||||
|
||||
if (ecmd->autoneg != AUTONEG_DISABLE && ecmd->autoneg != AUTONEG_ENABLE)
|
||||
return -EINVAL;
|
||||
|
||||
if (ecmd->autoneg == AUTONEG_DISABLE)
|
||||
*buf = (ecmd->duplex == DUPLEX_FULL)
|
||||
? SK_LMODE_FULL : SK_LMODE_HALF;
|
||||
else
|
||||
*buf = (ecmd->duplex == DUPLEX_FULL)
|
||||
? SK_LMODE_AUTOFULL : SK_LMODE_AUTOHALF;
|
||||
|
||||
instance = pnmiInstance(pNet);
|
||||
if (SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_LINK_MODE,
|
||||
&buf, &len, instance, pNet->NetNr) != SK_PNMI_ERR_OK)
|
||||
return -EINVAL;
|
||||
|
||||
switch(ecmd->speed) {
|
||||
case SPEED_1000:
|
||||
*buf = SK_LSPEED_1000MBPS;
|
||||
break;
|
||||
case SPEED_100:
|
||||
*buf = SK_LSPEED_100MBPS;
|
||||
break;
|
||||
case SPEED_10:
|
||||
*buf = SK_LSPEED_10MBPS;
|
||||
}
|
||||
|
||||
if (SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE,
|
||||
&buf, &len, instance, pNet->NetNr) != SK_PNMI_ERR_OK)
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
*
|
||||
* getDriverInfo - returns generic driver and adapter information
|
||||
*
|
||||
* Description:
|
||||
* Generic driver information is returned via this function, such as
|
||||
* the name of the driver, its version and and firmware version.
|
||||
* In addition to this, the location of the selected adapter is
|
||||
* returned as a bus info string (e.g. '01:05.0').
|
||||
*
|
||||
* Returns: N/A
|
||||
*
|
||||
*/
|
||||
static void getDriverInfo(struct net_device *dev, struct ethtool_drvinfo *info)
|
||||
{
|
||||
const DEV_NET *pNet = netdev_priv(dev);
|
||||
const SK_AC *pAC = pNet->pAC;
|
||||
char vers[32];
|
||||
|
||||
snprintf(vers, sizeof(vers)-1, VER_STRING "(v%d.%d)",
|
||||
(pAC->GIni.GIPciHwRev >> 4) & 0xf, pAC->GIni.GIPciHwRev & 0xf);
|
||||
|
||||
strlcpy(info->driver, DRIVER_FILE_NAME, sizeof(info->driver));
|
||||
strcpy(info->version, vers);
|
||||
strcpy(info->fw_version, "N/A");
|
||||
strlcpy(info->bus_info, pci_name(pAC->PciDev), ETHTOOL_BUSINFO_LEN);
|
||||
}
|
||||
|
||||
/*
|
||||
* Ethtool statistics support.
|
||||
*/
|
||||
static const char StringsStats[][ETH_GSTRING_LEN] = {
|
||||
"rx_packets", "tx_packets",
|
||||
"rx_bytes", "tx_bytes",
|
||||
"rx_errors", "tx_errors",
|
||||
"rx_dropped", "tx_dropped",
|
||||
"multicasts", "collisions",
|
||||
"rx_length_errors", "rx_buffer_overflow_errors",
|
||||
"rx_crc_errors", "rx_frame_errors",
|
||||
"rx_too_short_errors", "rx_too_long_errors",
|
||||
"rx_carrier_extension_errors", "rx_symbol_errors",
|
||||
"rx_llc_mac_size_errors", "rx_carrier_errors",
|
||||
"rx_jabber_errors", "rx_missed_errors",
|
||||
"tx_abort_collision_errors", "tx_carrier_errors",
|
||||
"tx_buffer_underrun_errors", "tx_heartbeat_errors",
|
||||
"tx_window_errors",
|
||||
};
|
||||
|
||||
static int getStatsCount(struct net_device *dev)
|
||||
{
|
||||
return ARRAY_SIZE(StringsStats);
|
||||
}
|
||||
|
||||
static void getStrings(struct net_device *dev, u32 stringset, u8 *data)
|
||||
{
|
||||
switch(stringset) {
|
||||
case ETH_SS_STATS:
|
||||
memcpy(data, *StringsStats, sizeof(StringsStats));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void getEthtoolStats(struct net_device *dev,
|
||||
struct ethtool_stats *stats, u64 *data)
|
||||
{
|
||||
const DEV_NET *pNet = netdev_priv(dev);
|
||||
const SK_AC *pAC = pNet->pAC;
|
||||
const SK_PNMI_STRUCT_DATA *pPnmiStruct = &pAC->PnmiStruct;
|
||||
|
||||
*data++ = pPnmiStruct->Stat[0].StatRxOkCts;
|
||||
*data++ = pPnmiStruct->Stat[0].StatTxOkCts;
|
||||
*data++ = pPnmiStruct->Stat[0].StatRxOctetsOkCts;
|
||||
*data++ = pPnmiStruct->Stat[0].StatTxOctetsOkCts;
|
||||
*data++ = pPnmiStruct->InErrorsCts;
|
||||
*data++ = pPnmiStruct->Stat[0].StatTxSingleCollisionCts;
|
||||
*data++ = pPnmiStruct->RxNoBufCts;
|
||||
*data++ = pPnmiStruct->TxNoBufCts;
|
||||
*data++ = pPnmiStruct->Stat[0].StatRxMulticastOkCts;
|
||||
*data++ = pPnmiStruct->Stat[0].StatTxSingleCollisionCts;
|
||||
*data++ = pPnmiStruct->Stat[0].StatRxRuntCts;
|
||||
*data++ = pPnmiStruct->Stat[0].StatRxFifoOverflowCts;
|
||||
*data++ = pPnmiStruct->Stat[0].StatRxFcsCts;
|
||||
*data++ = pPnmiStruct->Stat[0].StatRxFramingCts;
|
||||
*data++ = pPnmiStruct->Stat[0].StatRxShortsCts;
|
||||
*data++ = pPnmiStruct->Stat[0].StatRxTooLongCts;
|
||||
*data++ = pPnmiStruct->Stat[0].StatRxCextCts;
|
||||
*data++ = pPnmiStruct->Stat[0].StatRxSymbolCts;
|
||||
*data++ = pPnmiStruct->Stat[0].StatRxIRLengthCts;
|
||||
*data++ = pPnmiStruct->Stat[0].StatRxCarrierCts;
|
||||
*data++ = pPnmiStruct->Stat[0].StatRxJabberCts;
|
||||
*data++ = pPnmiStruct->Stat[0].StatRxMissedCts;
|
||||
*data++ = pAC->stats.tx_aborted_errors;
|
||||
*data++ = pPnmiStruct->Stat[0].StatTxCarrierCts;
|
||||
*data++ = pPnmiStruct->Stat[0].StatTxFifoUnderrunCts;
|
||||
*data++ = pPnmiStruct->Stat[0].StatTxCarrierCts;
|
||||
*data++ = pAC->stats.tx_window_errors;
|
||||
}
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
*
|
||||
* toggleLeds - Changes the LED state of an adapter
|
||||
*
|
||||
* Description:
|
||||
* This function changes the current state of all LEDs of an adapter so
|
||||
* that it can be located by a user.
|
||||
*
|
||||
* Returns: N/A
|
||||
*
|
||||
*/
|
||||
static void toggleLeds(DEV_NET *pNet, int on)
|
||||
{
|
||||
SK_AC *pAC = pNet->pAC;
|
||||
int port = pNet->PortNr;
|
||||
void __iomem *io = pAC->IoBase;
|
||||
|
||||
if (pAC->GIni.GIGenesis) {
|
||||
SK_OUT8(io, MR_ADDR(port,LNK_LED_REG),
|
||||
on ? SK_LNK_ON : SK_LNK_OFF);
|
||||
SkGeYellowLED(pAC, io,
|
||||
on ? (LED_ON >> 1) : (LED_OFF >> 1));
|
||||
SkGeXmitLED(pAC, io, MR_ADDR(port,RX_LED_INI),
|
||||
on ? SK_LED_TST : SK_LED_DIS);
|
||||
|
||||
if (pAC->GIni.GP[port].PhyType == SK_PHY_BCOM)
|
||||
SkXmPhyWrite(pAC, io, port, PHY_BCOM_P_EXT_CTRL,
|
||||
on ? PHY_B_PEC_LED_ON : PHY_B_PEC_LED_OFF);
|
||||
else if (pAC->GIni.GP[port].PhyType == SK_PHY_LONE)
|
||||
SkXmPhyWrite(pAC, io, port, PHY_LONE_LED_CFG,
|
||||
on ? 0x0800 : PHY_L_LC_LEDT);
|
||||
else
|
||||
SkGeXmitLED(pAC, io, MR_ADDR(port,TX_LED_INI),
|
||||
on ? SK_LED_TST : SK_LED_DIS);
|
||||
} else {
|
||||
const u16 YukLedOn = (PHY_M_LED_MO_DUP(MO_LED_ON) |
|
||||
PHY_M_LED_MO_10(MO_LED_ON) |
|
||||
PHY_M_LED_MO_100(MO_LED_ON) |
|
||||
PHY_M_LED_MO_1000(MO_LED_ON) |
|
||||
PHY_M_LED_MO_RX(MO_LED_ON));
|
||||
const u16 YukLedOff = (PHY_M_LED_MO_DUP(MO_LED_OFF) |
|
||||
PHY_M_LED_MO_10(MO_LED_OFF) |
|
||||
PHY_M_LED_MO_100(MO_LED_OFF) |
|
||||
PHY_M_LED_MO_1000(MO_LED_OFF) |
|
||||
PHY_M_LED_MO_RX(MO_LED_OFF));
|
||||
|
||||
|
||||
SkGmPhyWrite(pAC,io,port,PHY_MARV_LED_CTRL,0);
|
||||
SkGmPhyWrite(pAC,io,port,PHY_MARV_LED_OVER,
|
||||
on ? YukLedOn : YukLedOff);
|
||||
}
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
*
|
||||
* skGeBlinkTimer - Changes the LED state of an adapter
|
||||
*
|
||||
* Description:
|
||||
* This function changes the current state of all LEDs of an adapter so
|
||||
* that it can be located by a user. If the requested time interval for
|
||||
* this test has elapsed, this function cleans up everything that was
|
||||
* temporarily setup during the locate NIC test. This involves of course
|
||||
* also closing or opening any adapter so that the initial board state
|
||||
* is recovered.
|
||||
*
|
||||
* Returns: N/A
|
||||
*
|
||||
*/
|
||||
void SkGeBlinkTimer(unsigned long data)
|
||||
{
|
||||
struct net_device *dev = (struct net_device *) data;
|
||||
DEV_NET *pNet = netdev_priv(dev);
|
||||
SK_AC *pAC = pNet->pAC;
|
||||
|
||||
toggleLeds(pNet, pAC->LedsOn);
|
||||
|
||||
pAC->LedsOn = !pAC->LedsOn;
|
||||
mod_timer(&pAC->BlinkTimer, jiffies + HZ/4);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
*
|
||||
* locateDevice - start the locate NIC feature of the elected adapter
|
||||
*
|
||||
* Description:
|
||||
* This function is used if the user want to locate a particular NIC.
|
||||
* All LEDs are regularly switched on and off, so the NIC can easily
|
||||
* be identified.
|
||||
*
|
||||
* Returns:
|
||||
* ==0: everything fine, no error, locateNIC test was started
|
||||
* !=0: one locateNIC test runs already
|
||||
*
|
||||
*/
|
||||
static int locateDevice(struct net_device *dev, u32 data)
|
||||
{
|
||||
DEV_NET *pNet = netdev_priv(dev);
|
||||
SK_AC *pAC = pNet->pAC;
|
||||
|
||||
if(!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
|
||||
data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
|
||||
|
||||
/* start blinking */
|
||||
pAC->LedsOn = 0;
|
||||
mod_timer(&pAC->BlinkTimer, jiffies);
|
||||
msleep_interruptible(data * 1000);
|
||||
del_timer_sync(&pAC->BlinkTimer);
|
||||
toggleLeds(pNet, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
*
|
||||
* getPauseParams - retrieves the pause parameters
|
||||
*
|
||||
* Description:
|
||||
* All current pause parameters of a selected adapter are placed
|
||||
* in the passed ethtool_pauseparam structure and are returned.
|
||||
*
|
||||
* Returns: N/A
|
||||
*
|
||||
*/
|
||||
static void getPauseParams(struct net_device *dev, struct ethtool_pauseparam *epause)
|
||||
{
|
||||
DEV_NET *pNet = netdev_priv(dev);
|
||||
SK_AC *pAC = pNet->pAC;
|
||||
SK_GEPORT *pPort = &pAC->GIni.GP[pNet->PortNr];
|
||||
|
||||
epause->rx_pause = (pPort->PFlowCtrlMode == SK_FLOW_MODE_SYMMETRIC) ||
|
||||
(pPort->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM);
|
||||
|
||||
epause->tx_pause = epause->rx_pause || (pPort->PFlowCtrlMode == SK_FLOW_MODE_LOC_SEND);
|
||||
epause->autoneg = epause->rx_pause || epause->tx_pause;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
*
|
||||
* setPauseParams - configures the pause parameters of an adapter
|
||||
*
|
||||
* Description:
|
||||
* This function sets the Rx or Tx pause parameters
|
||||
*
|
||||
* Returns:
|
||||
* ==0: everything fine, no error
|
||||
* !=0: the return value is the error code of the failure
|
||||
*/
|
||||
static int setPauseParams(struct net_device *dev , struct ethtool_pauseparam *epause)
|
||||
{
|
||||
DEV_NET *pNet = netdev_priv(dev);
|
||||
SK_AC *pAC = pNet->pAC;
|
||||
SK_GEPORT *pPort = &pAC->GIni.GP[pNet->PortNr];
|
||||
u32 instance = pnmiInstance(pNet);
|
||||
struct ethtool_pauseparam old;
|
||||
u8 oldspeed = pPort->PLinkSpeedUsed;
|
||||
char buf[4];
|
||||
int len = 1;
|
||||
int ret;
|
||||
|
||||
/*
|
||||
** we have to determine the current settings to see if
|
||||
** the operator requested any modification of the flow
|
||||
** control parameters...
|
||||
*/
|
||||
getPauseParams(dev, &old);
|
||||
|
||||
/*
|
||||
** perform modifications regarding the changes
|
||||
** requested by the operator
|
||||
*/
|
||||
if (epause->autoneg != old.autoneg)
|
||||
*buf = epause->autoneg ? SK_FLOW_MODE_NONE : SK_FLOW_MODE_SYMMETRIC;
|
||||
else {
|
||||
if (epause->rx_pause && epause->tx_pause)
|
||||
*buf = SK_FLOW_MODE_SYMMETRIC;
|
||||
else if (epause->rx_pause && !epause->tx_pause)
|
||||
*buf = SK_FLOW_MODE_SYM_OR_REM;
|
||||
else if (!epause->rx_pause && epause->tx_pause)
|
||||
*buf = SK_FLOW_MODE_LOC_SEND;
|
||||
else
|
||||
*buf = SK_FLOW_MODE_NONE;
|
||||
}
|
||||
|
||||
ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_FLOWCTRL_MODE,
|
||||
&buf, &len, instance, pNet->NetNr);
|
||||
|
||||
if (ret != SK_PNMI_ERR_OK) {
|
||||
SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_CTRL,
|
||||
("ethtool (sk98lin): error changing rx/tx pause (%i)\n", ret));
|
||||
goto err;
|
||||
}
|
||||
|
||||
/*
|
||||
** It may be that autoneg has been disabled! Therefore
|
||||
** set the speed to the previously used value...
|
||||
*/
|
||||
if (!epause->autoneg) {
|
||||
len = 1;
|
||||
ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE,
|
||||
&oldspeed, &len, instance, pNet->NetNr);
|
||||
if (ret != SK_PNMI_ERR_OK)
|
||||
SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_CTRL,
|
||||
("ethtool (sk98lin): error setting speed (%i)\n", ret));
|
||||
}
|
||||
err:
|
||||
return ret ? -EIO : 0;
|
||||
}
|
||||
|
||||
/* Only Yukon supports checksum offload. */
|
||||
static int setScatterGather(struct net_device *dev, u32 data)
|
||||
{
|
||||
DEV_NET *pNet = netdev_priv(dev);
|
||||
SK_AC *pAC = pNet->pAC;
|
||||
|
||||
if (pAC->GIni.GIChipId == CHIP_ID_GENESIS)
|
||||
return -EOPNOTSUPP;
|
||||
return ethtool_op_set_sg(dev, data);
|
||||
}
|
||||
|
||||
static int setTxCsum(struct net_device *dev, u32 data)
|
||||
{
|
||||
DEV_NET *pNet = netdev_priv(dev);
|
||||
SK_AC *pAC = pNet->pAC;
|
||||
|
||||
if (pAC->GIni.GIChipId == CHIP_ID_GENESIS)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
return ethtool_op_set_tx_csum(dev, data);
|
||||
}
|
||||
|
||||
static u32 getRxCsum(struct net_device *dev)
|
||||
{
|
||||
DEV_NET *pNet = netdev_priv(dev);
|
||||
SK_AC *pAC = pNet->pAC;
|
||||
|
||||
return pAC->RxPort[pNet->PortNr].RxCsum;
|
||||
}
|
||||
|
||||
static int setRxCsum(struct net_device *dev, u32 data)
|
||||
{
|
||||
DEV_NET *pNet = netdev_priv(dev);
|
||||
SK_AC *pAC = pNet->pAC;
|
||||
|
||||
if (pAC->GIni.GIChipId == CHIP_ID_GENESIS)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
pAC->RxPort[pNet->PortNr].RxCsum = data != 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int getRegsLen(struct net_device *dev)
|
||||
{
|
||||
return 0x4000;
|
||||
}
|
||||
|
||||
/*
|
||||
* Returns copy of whole control register region
|
||||
* Note: skip RAM address register because accessing it will
|
||||
* cause bus hangs!
|
||||
*/
|
||||
static void getRegs(struct net_device *dev, struct ethtool_regs *regs,
|
||||
void *p)
|
||||
{
|
||||
DEV_NET *pNet = netdev_priv(dev);
|
||||
const void __iomem *io = pNet->pAC->IoBase;
|
||||
|
||||
regs->version = 1;
|
||||
memset(p, 0, regs->len);
|
||||
memcpy_fromio(p, io, B3_RAM_ADDR);
|
||||
|
||||
memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
|
||||
regs->len - B3_RI_WTO_R1);
|
||||
}
|
||||
|
||||
const struct ethtool_ops SkGeEthtoolOps = {
|
||||
.get_settings = getSettings,
|
||||
.set_settings = setSettings,
|
||||
.get_drvinfo = getDriverInfo,
|
||||
.get_strings = getStrings,
|
||||
.get_stats_count = getStatsCount,
|
||||
.get_ethtool_stats = getEthtoolStats,
|
||||
.phys_id = locateDevice,
|
||||
.get_pauseparam = getPauseParams,
|
||||
.set_pauseparam = setPauseParams,
|
||||
.get_link = ethtool_op_get_link,
|
||||
.get_sg = ethtool_op_get_sg,
|
||||
.set_sg = setScatterGather,
|
||||
.get_tx_csum = ethtool_op_get_tx_csum,
|
||||
.set_tx_csum = setTxCsum,
|
||||
.get_rx_csum = getRxCsum,
|
||||
.set_rx_csum = setRxCsum,
|
||||
.get_regs = getRegs,
|
||||
.get_regs_len = getRegsLen,
|
||||
};
|
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
@ -1,171 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Name: skgehwt.c
|
||||
* Project: Gigabit Ethernet Adapters, Event Scheduler Module
|
||||
* Version: $Revision: 1.15 $
|
||||
* Date: $Date: 2003/09/16 13:41:23 $
|
||||
* Purpose: Hardware Timer
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* (C)Copyright 1998-2002 SysKonnect GmbH.
|
||||
* (C)Copyright 2002-2003 Marvell.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* The information in this file is provided "AS IS" without warranty.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*
|
||||
* Event queue and dispatcher
|
||||
*/
|
||||
#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
|
||||
static const char SysKonnectFileId[] =
|
||||
"@(#) $Id: skgehwt.c,v 1.15 2003/09/16 13:41:23 rschmidt Exp $ (C) Marvell.";
|
||||
#endif
|
||||
|
||||
#include "h/skdrv1st.h" /* Driver Specific Definitions */
|
||||
#include "h/skdrv2nd.h" /* Adapter Control- and Driver specific Def. */
|
||||
|
||||
#ifdef __C2MAN__
|
||||
/*
|
||||
* Hardware Timer function queue management.
|
||||
*/
|
||||
intro()
|
||||
{}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Prototypes of local functions.
|
||||
*/
|
||||
#define SK_HWT_MAX (65000)
|
||||
|
||||
/* correction factor */
|
||||
#define SK_HWT_FAC (1000 * (SK_U32)pAC->GIni.GIHstClkFact / 100)
|
||||
|
||||
/*
|
||||
* Initialize hardware timer.
|
||||
*
|
||||
* Must be called during init level 1.
|
||||
*/
|
||||
void SkHwtInit(
|
||||
SK_AC *pAC, /* Adapters context */
|
||||
SK_IOC Ioc) /* IoContext */
|
||||
{
|
||||
pAC->Hwt.TStart = 0 ;
|
||||
pAC->Hwt.TStop = 0 ;
|
||||
pAC->Hwt.TActive = SK_FALSE;
|
||||
|
||||
SkHwtStop(pAC, Ioc);
|
||||
}
|
||||
|
||||
/*
|
||||
*
|
||||
* Start hardware timer (clock ticks are 16us).
|
||||
*
|
||||
*/
|
||||
void SkHwtStart(
|
||||
SK_AC *pAC, /* Adapters context */
|
||||
SK_IOC Ioc, /* IoContext */
|
||||
SK_U32 Time) /* Time in units of 16us to load the timer with. */
|
||||
{
|
||||
SK_U32 Cnt;
|
||||
|
||||
if (Time > SK_HWT_MAX)
|
||||
Time = SK_HWT_MAX;
|
||||
|
||||
pAC->Hwt.TStart = Time;
|
||||
pAC->Hwt.TStop = 0L;
|
||||
|
||||
Cnt = Time;
|
||||
|
||||
/*
|
||||
* if time < 16 us
|
||||
* time = 16 us
|
||||
*/
|
||||
if (!Cnt) {
|
||||
Cnt++;
|
||||
}
|
||||
|
||||
SK_OUT32(Ioc, B2_TI_INI, Cnt * SK_HWT_FAC);
|
||||
|
||||
SK_OUT16(Ioc, B2_TI_CTRL, TIM_START); /* Start timer. */
|
||||
|
||||
pAC->Hwt.TActive = SK_TRUE;
|
||||
}
|
||||
|
||||
/*
|
||||
* Stop hardware timer.
|
||||
* and clear the timer IRQ
|
||||
*/
|
||||
void SkHwtStop(
|
||||
SK_AC *pAC, /* Adapters context */
|
||||
SK_IOC Ioc) /* IoContext */
|
||||
{
|
||||
SK_OUT16(Ioc, B2_TI_CTRL, TIM_STOP);
|
||||
|
||||
SK_OUT16(Ioc, B2_TI_CTRL, TIM_CLR_IRQ);
|
||||
|
||||
pAC->Hwt.TActive = SK_FALSE;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Stop hardware timer and read time elapsed since last start.
|
||||
*
|
||||
* returns
|
||||
* The elapsed time since last start in units of 16us.
|
||||
*
|
||||
*/
|
||||
SK_U32 SkHwtRead(
|
||||
SK_AC *pAC, /* Adapters context */
|
||||
SK_IOC Ioc) /* IoContext */
|
||||
{
|
||||
SK_U32 TRead;
|
||||
SK_U32 IStatus;
|
||||
|
||||
if (pAC->Hwt.TActive) {
|
||||
|
||||
SkHwtStop(pAC, Ioc);
|
||||
|
||||
SK_IN32(Ioc, B2_TI_VAL, &TRead);
|
||||
TRead /= SK_HWT_FAC;
|
||||
|
||||
SK_IN32(Ioc, B0_ISRC, &IStatus);
|
||||
|
||||
/* Check if timer expired (or wraped around) */
|
||||
if ((TRead > pAC->Hwt.TStart) || (IStatus & IS_TIMINT)) {
|
||||
|
||||
SkHwtStop(pAC, Ioc);
|
||||
|
||||
pAC->Hwt.TStop = pAC->Hwt.TStart;
|
||||
}
|
||||
else {
|
||||
|
||||
pAC->Hwt.TStop = pAC->Hwt.TStart - TRead;
|
||||
}
|
||||
}
|
||||
return(pAC->Hwt.TStop);
|
||||
}
|
||||
|
||||
/*
|
||||
* interrupt source= timer
|
||||
*/
|
||||
void SkHwtIsr(
|
||||
SK_AC *pAC, /* Adapters context */
|
||||
SK_IOC Ioc) /* IoContext */
|
||||
{
|
||||
SkHwtStop(pAC, Ioc);
|
||||
|
||||
pAC->Hwt.TStop = pAC->Hwt.TStart;
|
||||
|
||||
SkTimerDone(pAC, Ioc);
|
||||
}
|
||||
|
||||
/* End of file */
|
Разница между файлами не показана из-за своего большого размера
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Разница между файлами не показана из-за своего большого размера
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Разница между файлами не показана из-за своего большого размера
Загрузить разницу
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
@ -1,141 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Name: sklm80.c
|
||||
* Project: Gigabit Ethernet Adapters, TWSI-Module
|
||||
* Version: $Revision: 1.22 $
|
||||
* Date: $Date: 2003/10/20 09:08:21 $
|
||||
* Purpose: Functions to access Voltage and Temperature Sensor (LM80)
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* (C)Copyright 1998-2002 SysKonnect.
|
||||
* (C)Copyright 2002-2003 Marvell.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* The information in this file is provided "AS IS" without warranty.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/*
|
||||
LM80 functions
|
||||
*/
|
||||
#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
|
||||
static const char SysKonnectFileId[] =
|
||||
"@(#) $Id: sklm80.c,v 1.22 2003/10/20 09:08:21 rschmidt Exp $ (C) Marvell. ";
|
||||
#endif
|
||||
|
||||
#include "h/skdrv1st.h" /* Driver Specific Definitions */
|
||||
#include "h/lm80.h"
|
||||
#include "h/skdrv2nd.h" /* Adapter Control- and Driver specific Def. */
|
||||
|
||||
#define BREAK_OR_WAIT(pAC,IoC,Event) break
|
||||
|
||||
/*
|
||||
* read a sensors value (LM80 specific)
|
||||
*
|
||||
* This function reads a sensors value from the I2C sensor chip LM80.
|
||||
* The sensor is defined by its index into the sensors database in the struct
|
||||
* pAC points to.
|
||||
*
|
||||
* Returns 1 if the read is completed
|
||||
* 0 if the read must be continued (I2C Bus still allocated)
|
||||
*/
|
||||
int SkLm80ReadSensor(
|
||||
SK_AC *pAC, /* Adapter Context */
|
||||
SK_IOC IoC, /* I/O Context needed in level 1 and 2 */
|
||||
SK_SENSOR *pSen) /* Sensor to be read */
|
||||
{
|
||||
SK_I32 Value;
|
||||
|
||||
switch (pSen->SenState) {
|
||||
case SK_SEN_IDLE:
|
||||
/* Send address to ADDR register */
|
||||
SK_I2C_CTL(IoC, I2C_READ, pSen->SenDev, I2C_025K_DEV, pSen->SenReg, 0);
|
||||
|
||||
pSen->SenState = SK_SEN_VALUE ;
|
||||
BREAK_OR_WAIT(pAC, IoC, I2C_READ);
|
||||
|
||||
case SK_SEN_VALUE:
|
||||
/* Read value from data register */
|
||||
SK_IN32(IoC, B2_I2C_DATA, ((SK_U32 *)&Value));
|
||||
|
||||
Value &= 0xff; /* only least significant byte is valid */
|
||||
|
||||
/* Do NOT check the Value against the thresholds */
|
||||
/* Checking is done in the calling instance */
|
||||
|
||||
if (pSen->SenType == SK_SEN_VOLT) {
|
||||
/* Voltage sensor */
|
||||
pSen->SenValue = Value * SK_LM80_VT_LSB;
|
||||
pSen->SenState = SK_SEN_IDLE ;
|
||||
return(1);
|
||||
}
|
||||
|
||||
if (pSen->SenType == SK_SEN_FAN) {
|
||||
if (Value != 0 && Value != 0xff) {
|
||||
/* Fan speed counter */
|
||||
pSen->SenValue = SK_LM80_FAN_FAKTOR/Value;
|
||||
}
|
||||
else {
|
||||
/* Indicate Fan error */
|
||||
pSen->SenValue = 0;
|
||||
}
|
||||
pSen->SenState = SK_SEN_IDLE ;
|
||||
return(1);
|
||||
}
|
||||
|
||||
/* First: correct the value: it might be negative */
|
||||
if ((Value & 0x80) != 0) {
|
||||
/* Value is negative */
|
||||
Value = Value - 256;
|
||||
}
|
||||
|
||||
/* We have a temperature sensor and need to get the signed extension.
|
||||
* For now we get the extension from the last reading, so in the normal
|
||||
* case we won't see flickering temperatures.
|
||||
*/
|
||||
pSen->SenValue = (Value * SK_LM80_TEMP_LSB) +
|
||||
(pSen->SenValue % SK_LM80_TEMP_LSB);
|
||||
|
||||
/* Send address to ADDR register */
|
||||
SK_I2C_CTL(IoC, I2C_READ, pSen->SenDev, I2C_025K_DEV, LM80_TEMP_CTRL, 0);
|
||||
|
||||
pSen->SenState = SK_SEN_VALEXT ;
|
||||
BREAK_OR_WAIT(pAC, IoC, I2C_READ);
|
||||
|
||||
case SK_SEN_VALEXT:
|
||||
/* Read value from data register */
|
||||
SK_IN32(IoC, B2_I2C_DATA, ((SK_U32 *)&Value));
|
||||
Value &= LM80_TEMP_LSB_9; /* only bit 7 is valid */
|
||||
|
||||
/* cut the LSB bit */
|
||||
pSen->SenValue = ((pSen->SenValue / SK_LM80_TEMP_LSB) *
|
||||
SK_LM80_TEMP_LSB);
|
||||
|
||||
if (pSen->SenValue < 0) {
|
||||
/* Value negative: The bit value must be subtracted */
|
||||
pSen->SenValue -= ((Value >> 7) * SK_LM80_TEMPEXT_LSB);
|
||||
}
|
||||
else {
|
||||
/* Value positive: The bit value must be added */
|
||||
pSen->SenValue += ((Value >> 7) * SK_LM80_TEMPEXT_LSB);
|
||||
}
|
||||
|
||||
pSen->SenState = SK_SEN_IDLE ;
|
||||
return(1);
|
||||
|
||||
default:
|
||||
SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E007, SKERR_I2C_E007MSG);
|
||||
return(1);
|
||||
}
|
||||
|
||||
/* Not completed */
|
||||
return(0);
|
||||
}
|
||||
|
|
@ -1,179 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Name: skqueue.c
|
||||
* Project: Gigabit Ethernet Adapters, Event Scheduler Module
|
||||
* Version: $Revision: 1.20 $
|
||||
* Date: $Date: 2003/09/16 13:44:00 $
|
||||
* Purpose: Management of an event queue.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* (C)Copyright 1998-2002 SysKonnect GmbH.
|
||||
* (C)Copyright 2002-2003 Marvell.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* The information in this file is provided "AS IS" without warranty.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/*
|
||||
* Event queue and dispatcher
|
||||
*/
|
||||
#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
|
||||
static const char SysKonnectFileId[] =
|
||||
"@(#) $Id: skqueue.c,v 1.20 2003/09/16 13:44:00 rschmidt Exp $ (C) Marvell.";
|
||||
#endif
|
||||
|
||||
#include "h/skdrv1st.h" /* Driver Specific Definitions */
|
||||
#include "h/skqueue.h" /* Queue Definitions */
|
||||
#include "h/skdrv2nd.h" /* Adapter Control- and Driver specific Def. */
|
||||
|
||||
#ifdef __C2MAN__
|
||||
/*
|
||||
Event queue management.
|
||||
|
||||
General Description:
|
||||
|
||||
*/
|
||||
intro()
|
||||
{}
|
||||
#endif
|
||||
|
||||
#define PRINTF(a,b,c)
|
||||
|
||||
/*
|
||||
* init event queue management
|
||||
*
|
||||
* Must be called during init level 0.
|
||||
*/
|
||||
void SkEventInit(
|
||||
SK_AC *pAC, /* Adapter context */
|
||||
SK_IOC Ioc, /* IO context */
|
||||
int Level) /* Init level */
|
||||
{
|
||||
switch (Level) {
|
||||
case SK_INIT_DATA:
|
||||
pAC->Event.EvPut = pAC->Event.EvGet = pAC->Event.EvQueue;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* add event to queue
|
||||
*/
|
||||
void SkEventQueue(
|
||||
SK_AC *pAC, /* Adapters context */
|
||||
SK_U32 Class, /* Event Class */
|
||||
SK_U32 Event, /* Event to be queued */
|
||||
SK_EVPARA Para) /* Event parameter */
|
||||
{
|
||||
pAC->Event.EvPut->Class = Class;
|
||||
pAC->Event.EvPut->Event = Event;
|
||||
pAC->Event.EvPut->Para = Para;
|
||||
|
||||
if (++pAC->Event.EvPut == &pAC->Event.EvQueue[SK_MAX_EVENT])
|
||||
pAC->Event.EvPut = pAC->Event.EvQueue;
|
||||
|
||||
if (pAC->Event.EvPut == pAC->Event.EvGet) {
|
||||
SK_ERR_LOG(pAC, SK_ERRCL_NORES, SKERR_Q_E001, SKERR_Q_E001MSG);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* event dispatcher
|
||||
* while event queue is not empty
|
||||
* get event from queue
|
||||
* send command to state machine
|
||||
* end
|
||||
* return error reported by individual Event function
|
||||
* 0 if no error occured.
|
||||
*/
|
||||
int SkEventDispatcher(
|
||||
SK_AC *pAC, /* Adapters Context */
|
||||
SK_IOC Ioc) /* Io context */
|
||||
{
|
||||
SK_EVENTELEM *pEv; /* pointer into queue */
|
||||
SK_U32 Class;
|
||||
int Rtv;
|
||||
|
||||
pEv = pAC->Event.EvGet;
|
||||
|
||||
PRINTF("dispatch get %x put %x\n", pEv, pAC->Event.ev_put);
|
||||
|
||||
while (pEv != pAC->Event.EvPut) {
|
||||
PRINTF("dispatch Class %d Event %d\n", pEv->Class, pEv->Event);
|
||||
|
||||
switch (Class = pEv->Class) {
|
||||
#ifndef SK_USE_LAC_EV
|
||||
#ifndef SK_SLIM
|
||||
case SKGE_RLMT: /* RLMT Event */
|
||||
Rtv = SkRlmtEvent(pAC, Ioc, pEv->Event, pEv->Para);
|
||||
break;
|
||||
case SKGE_I2C: /* I2C Event */
|
||||
Rtv = SkI2cEvent(pAC, Ioc, pEv->Event, pEv->Para);
|
||||
break;
|
||||
case SKGE_PNMI: /* PNMI Event */
|
||||
Rtv = SkPnmiEvent(pAC, Ioc, pEv->Event, pEv->Para);
|
||||
break;
|
||||
#endif /* not SK_SLIM */
|
||||
#endif /* not SK_USE_LAC_EV */
|
||||
case SKGE_DRV: /* Driver Event */
|
||||
Rtv = SkDrvEvent(pAC, Ioc, pEv->Event, pEv->Para);
|
||||
break;
|
||||
#ifndef SK_USE_SW_TIMER
|
||||
case SKGE_HWAC:
|
||||
Rtv = SkGeSirqEvent(pAC, Ioc, pEv->Event, pEv->Para);
|
||||
break;
|
||||
#else /* !SK_USE_SW_TIMER */
|
||||
case SKGE_SWT :
|
||||
Rtv = SkSwtEvent(pAC, Ioc, pEv->Event, pEv->Para);
|
||||
break;
|
||||
#endif /* !SK_USE_SW_TIMER */
|
||||
#ifdef SK_USE_LAC_EV
|
||||
case SKGE_LACP :
|
||||
Rtv = SkLacpEvent(pAC, Ioc, pEv->Event, pEv->Para);
|
||||
break;
|
||||
case SKGE_RSF :
|
||||
Rtv = SkRsfEvent(pAC, Ioc, pEv->Event, pEv->Para);
|
||||
break;
|
||||
case SKGE_MARKER :
|
||||
Rtv = SkMarkerEvent(pAC, Ioc, pEv->Event, pEv->Para);
|
||||
break;
|
||||
case SKGE_FD :
|
||||
Rtv = SkFdEvent(pAC, Ioc, pEv->Event, pEv->Para);
|
||||
break;
|
||||
#endif /* SK_USE_LAC_EV */
|
||||
#ifdef SK_USE_CSUM
|
||||
case SKGE_CSUM :
|
||||
Rtv = SkCsEvent(pAC, Ioc, pEv->Event, pEv->Para);
|
||||
break;
|
||||
#endif /* SK_USE_CSUM */
|
||||
default :
|
||||
SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_Q_E002, SKERR_Q_E002MSG);
|
||||
Rtv = 0;
|
||||
}
|
||||
|
||||
if (Rtv != 0) {
|
||||
return(Rtv);
|
||||
}
|
||||
|
||||
if (++pEv == &pAC->Event.EvQueue[SK_MAX_EVENT])
|
||||
pEv = pAC->Event.EvQueue;
|
||||
|
||||
/* Renew get: it is used in queue_events to detect overruns */
|
||||
pAC->Event.EvGet = pEv;
|
||||
}
|
||||
|
||||
return(0);
|
||||
}
|
||||
|
||||
/* End of file */
|
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
@ -1,250 +0,0 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Name: sktimer.c
|
||||
* Project: Gigabit Ethernet Adapters, Event Scheduler Module
|
||||
* Version: $Revision: 1.14 $
|
||||
* Date: $Date: 2003/09/16 13:46:51 $
|
||||
* Purpose: High level timer functions.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* (C)Copyright 1998-2002 SysKonnect GmbH.
|
||||
* (C)Copyright 2002-2003 Marvell.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* The information in this file is provided "AS IS" without warranty.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/*
|
||||
* Event queue and dispatcher
|
||||
*/
|
||||
#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
|
||||
static const char SysKonnectFileId[] =
|
||||
"@(#) $Id: sktimer.c,v 1.14 2003/09/16 13:46:51 rschmidt Exp $ (C) Marvell.";
|
||||
#endif
|
||||
|
||||
#include "h/skdrv1st.h" /* Driver Specific Definitions */
|
||||
#include "h/skdrv2nd.h" /* Adapter Control- and Driver specific Def. */
|
||||
|
||||
#ifdef __C2MAN__
|
||||
/*
|
||||
Event queue management.
|
||||
|
||||
General Description:
|
||||
|
||||
*/
|
||||
intro()
|
||||
{}
|
||||
#endif
|
||||
|
||||
|
||||
/* Forward declaration */
|
||||
static void timer_done(SK_AC *pAC,SK_IOC Ioc,int Restart);
|
||||
|
||||
|
||||
/*
|
||||
* Inits the software timer
|
||||
*
|
||||
* needs to be called during Init level 1.
|
||||
*/
|
||||
void SkTimerInit(
|
||||
SK_AC *pAC, /* Adapters context */
|
||||
SK_IOC Ioc, /* IoContext */
|
||||
int Level) /* Init Level */
|
||||
{
|
||||
switch (Level) {
|
||||
case SK_INIT_DATA:
|
||||
pAC->Tim.StQueue = NULL;
|
||||
break;
|
||||
case SK_INIT_IO:
|
||||
SkHwtInit(pAC, Ioc);
|
||||
SkTimerDone(pAC, Ioc);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Stops a high level timer
|
||||
* - If a timer is not in the queue the function returns normally, too.
|
||||
*/
|
||||
void SkTimerStop(
|
||||
SK_AC *pAC, /* Adapters context */
|
||||
SK_IOC Ioc, /* IoContext */
|
||||
SK_TIMER *pTimer) /* Timer Pointer to be started */
|
||||
{
|
||||
SK_TIMER **ppTimPrev;
|
||||
SK_TIMER *pTm;
|
||||
|
||||
/*
|
||||
* remove timer from queue
|
||||
*/
|
||||
pTimer->TmActive = SK_FALSE;
|
||||
|
||||
if (pAC->Tim.StQueue == pTimer && !pTimer->TmNext) {
|
||||
SkHwtStop(pAC, Ioc);
|
||||
}
|
||||
|
||||
for (ppTimPrev = &pAC->Tim.StQueue; (pTm = *ppTimPrev);
|
||||
ppTimPrev = &pTm->TmNext ) {
|
||||
|
||||
if (pTm == pTimer) {
|
||||
/*
|
||||
* Timer found in queue
|
||||
* - dequeue it and
|
||||
* - correct delta of the next timer
|
||||
*/
|
||||
*ppTimPrev = pTm->TmNext;
|
||||
|
||||
if (pTm->TmNext) {
|
||||
/* correct delta of next timer in queue */
|
||||
pTm->TmNext->TmDelta += pTm->TmDelta;
|
||||
}
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Start a high level software timer
|
||||
*/
|
||||
void SkTimerStart(
|
||||
SK_AC *pAC, /* Adapters context */
|
||||
SK_IOC Ioc, /* IoContext */
|
||||
SK_TIMER *pTimer, /* Timer Pointer to be started */
|
||||
SK_U32 Time, /* Time value */
|
||||
SK_U32 Class, /* Event Class for this timer */
|
||||
SK_U32 Event, /* Event Value for this timer */
|
||||
SK_EVPARA Para) /* Event Parameter for this timer */
|
||||
{
|
||||
SK_TIMER **ppTimPrev;
|
||||
SK_TIMER *pTm;
|
||||
SK_U32 Delta;
|
||||
|
||||
Time /= 16; /* input is uS, clock ticks are 16uS */
|
||||
|
||||
if (!Time)
|
||||
Time = 1;
|
||||
|
||||
SkTimerStop(pAC, Ioc, pTimer);
|
||||
|
||||
pTimer->TmClass = Class;
|
||||
pTimer->TmEvent = Event;
|
||||
pTimer->TmPara = Para;
|
||||
pTimer->TmActive = SK_TRUE;
|
||||
|
||||
if (!pAC->Tim.StQueue) {
|
||||
/* First Timer to be started */
|
||||
pAC->Tim.StQueue = pTimer;
|
||||
pTimer->TmNext = NULL;
|
||||
pTimer->TmDelta = Time;
|
||||
|
||||
SkHwtStart(pAC, Ioc, Time);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* timer correction
|
||||
*/
|
||||
timer_done(pAC, Ioc, 0);
|
||||
|
||||
/*
|
||||
* find position in queue
|
||||
*/
|
||||
Delta = 0;
|
||||
for (ppTimPrev = &pAC->Tim.StQueue; (pTm = *ppTimPrev);
|
||||
ppTimPrev = &pTm->TmNext ) {
|
||||
|
||||
if (Delta + pTm->TmDelta > Time) {
|
||||
/* Position found */
|
||||
/* Here the timer needs to be inserted. */
|
||||
break;
|
||||
}
|
||||
Delta += pTm->TmDelta;
|
||||
}
|
||||
|
||||
/* insert in queue */
|
||||
*ppTimPrev = pTimer;
|
||||
pTimer->TmNext = pTm;
|
||||
pTimer->TmDelta = Time - Delta;
|
||||
|
||||
if (pTm) {
|
||||
/* There is a next timer
|
||||
* -> correct its Delta value.
|
||||
*/
|
||||
pTm->TmDelta -= pTimer->TmDelta;
|
||||
}
|
||||
|
||||
/* restart with first */
|
||||
SkHwtStart(pAC, Ioc, pAC->Tim.StQueue->TmDelta);
|
||||
}
|
||||
|
||||
|
||||
void SkTimerDone(
|
||||
SK_AC *pAC, /* Adapters context */
|
||||
SK_IOC Ioc) /* IoContext */
|
||||
{
|
||||
timer_done(pAC, Ioc, 1);
|
||||
}
|
||||
|
||||
|
||||
static void timer_done(
|
||||
SK_AC *pAC, /* Adapters context */
|
||||
SK_IOC Ioc, /* IoContext */
|
||||
int Restart) /* Do we need to restart the Hardware timer ? */
|
||||
{
|
||||
SK_U32 Delta;
|
||||
SK_TIMER *pTm;
|
||||
SK_TIMER *pTComp; /* Timer completed now now */
|
||||
SK_TIMER **ppLast; /* Next field of Last timer to be deq */
|
||||
int Done = 0;
|
||||
|
||||
Delta = SkHwtRead(pAC, Ioc);
|
||||
|
||||
ppLast = &pAC->Tim.StQueue;
|
||||
pTm = pAC->Tim.StQueue;
|
||||
while (pTm && !Done) {
|
||||
if (Delta >= pTm->TmDelta) {
|
||||
/* Timer ran out */
|
||||
pTm->TmActive = SK_FALSE;
|
||||
Delta -= pTm->TmDelta;
|
||||
ppLast = &pTm->TmNext;
|
||||
pTm = pTm->TmNext;
|
||||
}
|
||||
else {
|
||||
/* We found the first timer that did not run out */
|
||||
pTm->TmDelta -= Delta;
|
||||
Delta = 0;
|
||||
Done = 1;
|
||||
}
|
||||
}
|
||||
*ppLast = NULL;
|
||||
/*
|
||||
* pTm points to the first Timer that did not run out.
|
||||
* StQueue points to the first Timer that run out.
|
||||
*/
|
||||
|
||||
for ( pTComp = pAC->Tim.StQueue; pTComp; pTComp = pTComp->TmNext) {
|
||||
SkEventQueue(pAC,pTComp->TmClass, pTComp->TmEvent, pTComp->TmPara);
|
||||
}
|
||||
|
||||
/* Set head of timer queue to the first timer that did not run out */
|
||||
pAC->Tim.StQueue = pTm;
|
||||
|
||||
if (Restart && pAC->Tim.StQueue) {
|
||||
/* Restart HW timer */
|
||||
SkHwtStart(pAC, Ioc, pAC->Tim.StQueue->TmDelta);
|
||||
}
|
||||
}
|
||||
|
||||
/* End of file */
|
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
@ -220,22 +220,22 @@ static void PRINT_PKT(u_char *buf, int length)
|
|||
|
||||
|
||||
/* this enables an interrupt in the interrupt mask register */
|
||||
#define SMC_ENABLE_INT(x) do { \
|
||||
#define SMC_ENABLE_INT(lp, x) do { \
|
||||
unsigned char mask; \
|
||||
spin_lock_irq(&lp->lock); \
|
||||
mask = SMC_GET_INT_MASK(); \
|
||||
mask = SMC_GET_INT_MASK(lp); \
|
||||
mask |= (x); \
|
||||
SMC_SET_INT_MASK(mask); \
|
||||
SMC_SET_INT_MASK(lp, mask); \
|
||||
spin_unlock_irq(&lp->lock); \
|
||||
} while (0)
|
||||
|
||||
/* this disables an interrupt from the interrupt mask register */
|
||||
#define SMC_DISABLE_INT(x) do { \
|
||||
#define SMC_DISABLE_INT(lp, x) do { \
|
||||
unsigned char mask; \
|
||||
spin_lock_irq(&lp->lock); \
|
||||
mask = SMC_GET_INT_MASK(); \
|
||||
mask = SMC_GET_INT_MASK(lp); \
|
||||
mask &= ~(x); \
|
||||
SMC_SET_INT_MASK(mask); \
|
||||
SMC_SET_INT_MASK(lp, mask); \
|
||||
spin_unlock_irq(&lp->lock); \
|
||||
} while (0)
|
||||
|
||||
|
@ -244,10 +244,10 @@ static void PRINT_PKT(u_char *buf, int length)
|
|||
* if at all, but let's avoid deadlocking the system if the hardware
|
||||
* decides to go south.
|
||||
*/
|
||||
#define SMC_WAIT_MMU_BUSY() do { \
|
||||
if (unlikely(SMC_GET_MMU_CMD() & MC_BUSY)) { \
|
||||
#define SMC_WAIT_MMU_BUSY(lp) do { \
|
||||
if (unlikely(SMC_GET_MMU_CMD(lp) & MC_BUSY)) { \
|
||||
unsigned long timeout = jiffies + 2; \
|
||||
while (SMC_GET_MMU_CMD() & MC_BUSY) { \
|
||||
while (SMC_GET_MMU_CMD(lp) & MC_BUSY) { \
|
||||
if (time_after(jiffies, timeout)) { \
|
||||
printk("%s: timeout %s line %d\n", \
|
||||
dev->name, __FILE__, __LINE__); \
|
||||
|
@ -273,8 +273,8 @@ static void smc_reset(struct net_device *dev)
|
|||
|
||||
/* Disable all interrupts, block TX tasklet */
|
||||
spin_lock_irq(&lp->lock);
|
||||
SMC_SELECT_BANK(2);
|
||||
SMC_SET_INT_MASK(0);
|
||||
SMC_SELECT_BANK(lp, 2);
|
||||
SMC_SET_INT_MASK(lp, 0);
|
||||
pending_skb = lp->pending_tx_skb;
|
||||
lp->pending_tx_skb = NULL;
|
||||
spin_unlock_irq(&lp->lock);
|
||||
|
@ -290,15 +290,15 @@ static void smc_reset(struct net_device *dev)
|
|||
* This resets the registers mostly to defaults, but doesn't
|
||||
* affect EEPROM. That seems unnecessary
|
||||
*/
|
||||
SMC_SELECT_BANK(0);
|
||||
SMC_SET_RCR(RCR_SOFTRST);
|
||||
SMC_SELECT_BANK(lp, 0);
|
||||
SMC_SET_RCR(lp, RCR_SOFTRST);
|
||||
|
||||
/*
|
||||
* Setup the Configuration Register
|
||||
* This is necessary because the CONFIG_REG is not affected
|
||||
* by a soft reset
|
||||
*/
|
||||
SMC_SELECT_BANK(1);
|
||||
SMC_SELECT_BANK(lp, 1);
|
||||
|
||||
cfg = CONFIG_DEFAULT;
|
||||
|
||||
|
@ -316,7 +316,7 @@ static void smc_reset(struct net_device *dev)
|
|||
*/
|
||||
cfg |= CONFIG_EPH_POWER_EN;
|
||||
|
||||
SMC_SET_CONFIG(cfg);
|
||||
SMC_SET_CONFIG(lp, cfg);
|
||||
|
||||
/* this should pause enough for the chip to be happy */
|
||||
/*
|
||||
|
@ -329,12 +329,12 @@ static void smc_reset(struct net_device *dev)
|
|||
udelay(1);
|
||||
|
||||
/* Disable transmit and receive functionality */
|
||||
SMC_SELECT_BANK(0);
|
||||
SMC_SET_RCR(RCR_CLEAR);
|
||||
SMC_SET_TCR(TCR_CLEAR);
|
||||
SMC_SELECT_BANK(lp, 0);
|
||||
SMC_SET_RCR(lp, RCR_CLEAR);
|
||||
SMC_SET_TCR(lp, TCR_CLEAR);
|
||||
|
||||
SMC_SELECT_BANK(1);
|
||||
ctl = SMC_GET_CTL() | CTL_LE_ENABLE;
|
||||
SMC_SELECT_BANK(lp, 1);
|
||||
ctl = SMC_GET_CTL(lp) | CTL_LE_ENABLE;
|
||||
|
||||
/*
|
||||
* Set the control register to automatically release successfully
|
||||
|
@ -345,12 +345,12 @@ static void smc_reset(struct net_device *dev)
|
|||
ctl |= CTL_AUTO_RELEASE;
|
||||
else
|
||||
ctl &= ~CTL_AUTO_RELEASE;
|
||||
SMC_SET_CTL(ctl);
|
||||
SMC_SET_CTL(lp, ctl);
|
||||
|
||||
/* Reset the MMU */
|
||||
SMC_SELECT_BANK(2);
|
||||
SMC_SET_MMU_CMD(MC_RESET);
|
||||
SMC_WAIT_MMU_BUSY();
|
||||
SMC_SELECT_BANK(lp, 2);
|
||||
SMC_SET_MMU_CMD(lp, MC_RESET);
|
||||
SMC_WAIT_MMU_BUSY(lp);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -365,19 +365,19 @@ static void smc_enable(struct net_device *dev)
|
|||
DBG(2, "%s: %s\n", dev->name, __FUNCTION__);
|
||||
|
||||
/* see the header file for options in TCR/RCR DEFAULT */
|
||||
SMC_SELECT_BANK(0);
|
||||
SMC_SET_TCR(lp->tcr_cur_mode);
|
||||
SMC_SET_RCR(lp->rcr_cur_mode);
|
||||
SMC_SELECT_BANK(lp, 0);
|
||||
SMC_SET_TCR(lp, lp->tcr_cur_mode);
|
||||
SMC_SET_RCR(lp, lp->rcr_cur_mode);
|
||||
|
||||
SMC_SELECT_BANK(1);
|
||||
SMC_SET_MAC_ADDR(dev->dev_addr);
|
||||
SMC_SELECT_BANK(lp, 1);
|
||||
SMC_SET_MAC_ADDR(lp, dev->dev_addr);
|
||||
|
||||
/* now, enable interrupts */
|
||||
mask = IM_EPH_INT|IM_RX_OVRN_INT|IM_RCV_INT;
|
||||
if (lp->version >= (CHIP_91100 << 4))
|
||||
mask |= IM_MDINT;
|
||||
SMC_SELECT_BANK(2);
|
||||
SMC_SET_INT_MASK(mask);
|
||||
SMC_SELECT_BANK(lp, 2);
|
||||
SMC_SET_INT_MASK(lp, mask);
|
||||
|
||||
/*
|
||||
* From this point the register bank must _NOT_ be switched away
|
||||
|
@ -400,8 +400,8 @@ static void smc_shutdown(struct net_device *dev)
|
|||
|
||||
/* no more interrupts for me */
|
||||
spin_lock_irq(&lp->lock);
|
||||
SMC_SELECT_BANK(2);
|
||||
SMC_SET_INT_MASK(0);
|
||||
SMC_SELECT_BANK(lp, 2);
|
||||
SMC_SET_INT_MASK(lp, 0);
|
||||
pending_skb = lp->pending_tx_skb;
|
||||
lp->pending_tx_skb = NULL;
|
||||
spin_unlock_irq(&lp->lock);
|
||||
|
@ -409,14 +409,14 @@ static void smc_shutdown(struct net_device *dev)
|
|||
dev_kfree_skb(pending_skb);
|
||||
|
||||
/* and tell the card to stay away from that nasty outside world */
|
||||
SMC_SELECT_BANK(0);
|
||||
SMC_SET_RCR(RCR_CLEAR);
|
||||
SMC_SET_TCR(TCR_CLEAR);
|
||||
SMC_SELECT_BANK(lp, 0);
|
||||
SMC_SET_RCR(lp, RCR_CLEAR);
|
||||
SMC_SET_TCR(lp, TCR_CLEAR);
|
||||
|
||||
#ifdef POWER_DOWN
|
||||
/* finally, shut the chip down */
|
||||
SMC_SELECT_BANK(1);
|
||||
SMC_SET_CONFIG(SMC_GET_CONFIG() & ~CONFIG_EPH_POWER_EN);
|
||||
SMC_SELECT_BANK(lp, 1);
|
||||
SMC_SET_CONFIG(lp, SMC_GET_CONFIG(lp) & ~CONFIG_EPH_POWER_EN);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
@ -431,17 +431,17 @@ static inline void smc_rcv(struct net_device *dev)
|
|||
|
||||
DBG(3, "%s: %s\n", dev->name, __FUNCTION__);
|
||||
|
||||
packet_number = SMC_GET_RXFIFO();
|
||||
packet_number = SMC_GET_RXFIFO(lp);
|
||||
if (unlikely(packet_number & RXFIFO_REMPTY)) {
|
||||
PRINTK("%s: smc_rcv with nothing on FIFO.\n", dev->name);
|
||||
return;
|
||||
}
|
||||
|
||||
/* read from start of packet */
|
||||
SMC_SET_PTR(PTR_READ | PTR_RCV | PTR_AUTOINC);
|
||||
SMC_SET_PTR(lp, PTR_READ | PTR_RCV | PTR_AUTOINC);
|
||||
|
||||
/* First two words are status and packet length */
|
||||
SMC_GET_PKT_HDR(status, packet_len);
|
||||
SMC_GET_PKT_HDR(lp, status, packet_len);
|
||||
packet_len &= 0x07ff; /* mask off top bits */
|
||||
DBG(2, "%s: RX PNR 0x%x STATUS 0x%04x LENGTH 0x%04x (%d)\n",
|
||||
dev->name, packet_number, status,
|
||||
|
@ -460,8 +460,8 @@ static inline void smc_rcv(struct net_device *dev)
|
|||
dev->name, packet_len, status);
|
||||
status |= RS_TOOSHORT;
|
||||
}
|
||||
SMC_WAIT_MMU_BUSY();
|
||||
SMC_SET_MMU_CMD(MC_RELEASE);
|
||||
SMC_WAIT_MMU_BUSY(lp);
|
||||
SMC_SET_MMU_CMD(lp, MC_RELEASE);
|
||||
dev->stats.rx_errors++;
|
||||
if (status & RS_ALGNERR)
|
||||
dev->stats.rx_frame_errors++;
|
||||
|
@ -490,8 +490,8 @@ static inline void smc_rcv(struct net_device *dev)
|
|||
if (unlikely(skb == NULL)) {
|
||||
printk(KERN_NOTICE "%s: Low memory, packet dropped.\n",
|
||||
dev->name);
|
||||
SMC_WAIT_MMU_BUSY();
|
||||
SMC_SET_MMU_CMD(MC_RELEASE);
|
||||
SMC_WAIT_MMU_BUSY(lp);
|
||||
SMC_SET_MMU_CMD(lp, MC_RELEASE);
|
||||
dev->stats.rx_dropped++;
|
||||
return;
|
||||
}
|
||||
|
@ -510,10 +510,10 @@ static inline void smc_rcv(struct net_device *dev)
|
|||
*/
|
||||
data_len = packet_len - ((status & RS_ODDFRAME) ? 5 : 6);
|
||||
data = skb_put(skb, data_len);
|
||||
SMC_PULL_DATA(data, packet_len - 4);
|
||||
SMC_PULL_DATA(lp, data, packet_len - 4);
|
||||
|
||||
SMC_WAIT_MMU_BUSY();
|
||||
SMC_SET_MMU_CMD(MC_RELEASE);
|
||||
SMC_WAIT_MMU_BUSY(lp);
|
||||
SMC_SET_MMU_CMD(lp, MC_RELEASE);
|
||||
|
||||
PRINT_PKT(data, packet_len - 4);
|
||||
|
||||
|
@ -591,7 +591,7 @@ static void smc_hardware_send_pkt(unsigned long data)
|
|||
}
|
||||
lp->pending_tx_skb = NULL;
|
||||
|
||||
packet_no = SMC_GET_AR();
|
||||
packet_no = SMC_GET_AR(lp);
|
||||
if (unlikely(packet_no & AR_FAILED)) {
|
||||
printk("%s: Memory allocation failed.\n", dev->name);
|
||||
dev->stats.tx_errors++;
|
||||
|
@ -601,8 +601,8 @@ static void smc_hardware_send_pkt(unsigned long data)
|
|||
}
|
||||
|
||||
/* point to the beginning of the packet */
|
||||
SMC_SET_PN(packet_no);
|
||||
SMC_SET_PTR(PTR_AUTOINC);
|
||||
SMC_SET_PN(lp, packet_no);
|
||||
SMC_SET_PTR(lp, PTR_AUTOINC);
|
||||
|
||||
buf = skb->data;
|
||||
len = skb->len;
|
||||
|
@ -614,13 +614,13 @@ static void smc_hardware_send_pkt(unsigned long data)
|
|||
* Send the packet length (+6 for status words, length, and ctl.
|
||||
* The card will pad to 64 bytes with zeroes if packet is too small.
|
||||
*/
|
||||
SMC_PUT_PKT_HDR(0, len + 6);
|
||||
SMC_PUT_PKT_HDR(lp, 0, len + 6);
|
||||
|
||||
/* send the actual data */
|
||||
SMC_PUSH_DATA(buf, len & ~1);
|
||||
SMC_PUSH_DATA(lp, buf, len & ~1);
|
||||
|
||||
/* Send final ctl word with the last byte if there is one */
|
||||
SMC_outw(((len & 1) ? (0x2000 | buf[len-1]) : 0), ioaddr, DATA_REG);
|
||||
SMC_outw(((len & 1) ? (0x2000 | buf[len-1]) : 0), ioaddr, DATA_REG(lp));
|
||||
|
||||
/*
|
||||
* If THROTTLE_TX_PKTS is set, we stop the queue here. This will
|
||||
|
@ -634,14 +634,14 @@ static void smc_hardware_send_pkt(unsigned long data)
|
|||
netif_stop_queue(dev);
|
||||
|
||||
/* queue the packet for TX */
|
||||
SMC_SET_MMU_CMD(MC_ENQUEUE);
|
||||
SMC_SET_MMU_CMD(lp, MC_ENQUEUE);
|
||||
smc_special_unlock(&lp->lock);
|
||||
|
||||
dev->trans_start = jiffies;
|
||||
dev->stats.tx_packets++;
|
||||
dev->stats.tx_bytes += len;
|
||||
|
||||
SMC_ENABLE_INT(IM_TX_INT | IM_TX_EMPTY_INT);
|
||||
SMC_ENABLE_INT(lp, IM_TX_INT | IM_TX_EMPTY_INT);
|
||||
|
||||
done: if (!THROTTLE_TX_PKTS)
|
||||
netif_wake_queue(dev);
|
||||
|
@ -688,7 +688,7 @@ static int smc_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
|
|||
smc_special_lock(&lp->lock);
|
||||
|
||||
/* now, try to allocate the memory */
|
||||
SMC_SET_MMU_CMD(MC_ALLOC | numPages);
|
||||
SMC_SET_MMU_CMD(lp, MC_ALLOC | numPages);
|
||||
|
||||
/*
|
||||
* Poll the chip for a short amount of time in case the
|
||||
|
@ -696,9 +696,9 @@ static int smc_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
|
|||
*/
|
||||
poll_count = MEMORY_WAIT_TIME;
|
||||
do {
|
||||
status = SMC_GET_INT();
|
||||
status = SMC_GET_INT(lp);
|
||||
if (status & IM_ALLOC_INT) {
|
||||
SMC_ACK_INT(IM_ALLOC_INT);
|
||||
SMC_ACK_INT(lp, IM_ALLOC_INT);
|
||||
break;
|
||||
}
|
||||
} while (--poll_count);
|
||||
|
@ -710,7 +710,7 @@ static int smc_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
|
|||
/* oh well, wait until the chip finds memory later */
|
||||
netif_stop_queue(dev);
|
||||
DBG(2, "%s: TX memory allocation deferred.\n", dev->name);
|
||||
SMC_ENABLE_INT(IM_ALLOC_INT);
|
||||
SMC_ENABLE_INT(lp, IM_ALLOC_INT);
|
||||
} else {
|
||||
/*
|
||||
* Allocation succeeded: push packet to the chip's own memory
|
||||
|
@ -736,19 +736,19 @@ static void smc_tx(struct net_device *dev)
|
|||
DBG(3, "%s: %s\n", dev->name, __FUNCTION__);
|
||||
|
||||
/* If the TX FIFO is empty then nothing to do */
|
||||
packet_no = SMC_GET_TXFIFO();
|
||||
packet_no = SMC_GET_TXFIFO(lp);
|
||||
if (unlikely(packet_no & TXFIFO_TEMPTY)) {
|
||||
PRINTK("%s: smc_tx with nothing on FIFO.\n", dev->name);
|
||||
return;
|
||||
}
|
||||
|
||||
/* select packet to read from */
|
||||
saved_packet = SMC_GET_PN();
|
||||
SMC_SET_PN(packet_no);
|
||||
saved_packet = SMC_GET_PN(lp);
|
||||
SMC_SET_PN(lp, packet_no);
|
||||
|
||||
/* read the first word (status word) from this packet */
|
||||
SMC_SET_PTR(PTR_AUTOINC | PTR_READ);
|
||||
SMC_GET_PKT_HDR(tx_status, pkt_len);
|
||||
SMC_SET_PTR(lp, PTR_AUTOINC | PTR_READ);
|
||||
SMC_GET_PKT_HDR(lp, tx_status, pkt_len);
|
||||
DBG(2, "%s: TX STATUS 0x%04x PNR 0x%02x\n",
|
||||
dev->name, tx_status, packet_no);
|
||||
|
||||
|
@ -771,17 +771,17 @@ static void smc_tx(struct net_device *dev)
|
|||
}
|
||||
|
||||
/* kill the packet */
|
||||
SMC_WAIT_MMU_BUSY();
|
||||
SMC_SET_MMU_CMD(MC_FREEPKT);
|
||||
SMC_WAIT_MMU_BUSY(lp);
|
||||
SMC_SET_MMU_CMD(lp, MC_FREEPKT);
|
||||
|
||||
/* Don't restore Packet Number Reg until busy bit is cleared */
|
||||
SMC_WAIT_MMU_BUSY();
|
||||
SMC_SET_PN(saved_packet);
|
||||
SMC_WAIT_MMU_BUSY(lp);
|
||||
SMC_SET_PN(lp, saved_packet);
|
||||
|
||||
/* re-enable transmit */
|
||||
SMC_SELECT_BANK(0);
|
||||
SMC_SET_TCR(lp->tcr_cur_mode);
|
||||
SMC_SELECT_BANK(2);
|
||||
SMC_SELECT_BANK(lp, 0);
|
||||
SMC_SET_TCR(lp, lp->tcr_cur_mode);
|
||||
SMC_SELECT_BANK(lp, 2);
|
||||
}
|
||||
|
||||
|
||||
|
@ -793,7 +793,7 @@ static void smc_mii_out(struct net_device *dev, unsigned int val, int bits)
|
|||
void __iomem *ioaddr = lp->base;
|
||||
unsigned int mii_reg, mask;
|
||||
|
||||
mii_reg = SMC_GET_MII() & ~(MII_MCLK | MII_MDOE | MII_MDO);
|
||||
mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO);
|
||||
mii_reg |= MII_MDOE;
|
||||
|
||||
for (mask = 1 << (bits - 1); mask; mask >>= 1) {
|
||||
|
@ -802,9 +802,9 @@ static void smc_mii_out(struct net_device *dev, unsigned int val, int bits)
|
|||
else
|
||||
mii_reg &= ~MII_MDO;
|
||||
|
||||
SMC_SET_MII(mii_reg);
|
||||
SMC_SET_MII(lp, mii_reg);
|
||||
udelay(MII_DELAY);
|
||||
SMC_SET_MII(mii_reg | MII_MCLK);
|
||||
SMC_SET_MII(lp, mii_reg | MII_MCLK);
|
||||
udelay(MII_DELAY);
|
||||
}
|
||||
}
|
||||
|
@ -815,16 +815,16 @@ static unsigned int smc_mii_in(struct net_device *dev, int bits)
|
|||
void __iomem *ioaddr = lp->base;
|
||||
unsigned int mii_reg, mask, val;
|
||||
|
||||
mii_reg = SMC_GET_MII() & ~(MII_MCLK | MII_MDOE | MII_MDO);
|
||||
SMC_SET_MII(mii_reg);
|
||||
mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO);
|
||||
SMC_SET_MII(lp, mii_reg);
|
||||
|
||||
for (mask = 1 << (bits - 1), val = 0; mask; mask >>= 1) {
|
||||
if (SMC_GET_MII() & MII_MDI)
|
||||
if (SMC_GET_MII(lp) & MII_MDI)
|
||||
val |= mask;
|
||||
|
||||
SMC_SET_MII(mii_reg);
|
||||
SMC_SET_MII(lp, mii_reg);
|
||||
udelay(MII_DELAY);
|
||||
SMC_SET_MII(mii_reg | MII_MCLK);
|
||||
SMC_SET_MII(lp, mii_reg | MII_MCLK);
|
||||
udelay(MII_DELAY);
|
||||
}
|
||||
|
||||
|
@ -840,7 +840,7 @@ static int smc_phy_read(struct net_device *dev, int phyaddr, int phyreg)
|
|||
void __iomem *ioaddr = lp->base;
|
||||
unsigned int phydata;
|
||||
|
||||
SMC_SELECT_BANK(3);
|
||||
SMC_SELECT_BANK(lp, 3);
|
||||
|
||||
/* Idle - 32 ones */
|
||||
smc_mii_out(dev, 0xffffffff, 32);
|
||||
|
@ -852,12 +852,12 @@ static int smc_phy_read(struct net_device *dev, int phyaddr, int phyreg)
|
|||
phydata = smc_mii_in(dev, 18);
|
||||
|
||||
/* Return to idle state */
|
||||
SMC_SET_MII(SMC_GET_MII() & ~(MII_MCLK|MII_MDOE|MII_MDO));
|
||||
SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO));
|
||||
|
||||
DBG(3, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
|
||||
__FUNCTION__, phyaddr, phyreg, phydata);
|
||||
|
||||
SMC_SELECT_BANK(2);
|
||||
SMC_SELECT_BANK(lp, 2);
|
||||
return phydata;
|
||||
}
|
||||
|
||||
|
@ -870,7 +870,7 @@ static void smc_phy_write(struct net_device *dev, int phyaddr, int phyreg,
|
|||
struct smc_local *lp = netdev_priv(dev);
|
||||
void __iomem *ioaddr = lp->base;
|
||||
|
||||
SMC_SELECT_BANK(3);
|
||||
SMC_SELECT_BANK(lp, 3);
|
||||
|
||||
/* Idle - 32 ones */
|
||||
smc_mii_out(dev, 0xffffffff, 32);
|
||||
|
@ -879,12 +879,12 @@ static void smc_phy_write(struct net_device *dev, int phyaddr, int phyreg,
|
|||
smc_mii_out(dev, 5 << 28 | phyaddr << 23 | phyreg << 18 | 2 << 16 | phydata, 32);
|
||||
|
||||
/* Return to idle state */
|
||||
SMC_SET_MII(SMC_GET_MII() & ~(MII_MCLK|MII_MDOE|MII_MDO));
|
||||
SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO));
|
||||
|
||||
DBG(3, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
|
||||
__FUNCTION__, phyaddr, phyreg, phydata);
|
||||
|
||||
SMC_SELECT_BANK(2);
|
||||
SMC_SELECT_BANK(lp, 2);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -957,9 +957,9 @@ static int smc_phy_fixed(struct net_device *dev)
|
|||
smc_phy_write(dev, phyaddr, MII_BMCR, bmcr);
|
||||
|
||||
/* Re-Configure the Receive/Phy Control register */
|
||||
SMC_SELECT_BANK(0);
|
||||
SMC_SET_RPC(lp->rpc_cur_mode);
|
||||
SMC_SELECT_BANK(2);
|
||||
SMC_SELECT_BANK(lp, 0);
|
||||
SMC_SET_RPC(lp, lp->rpc_cur_mode);
|
||||
SMC_SELECT_BANK(lp, 2);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
@ -1050,8 +1050,8 @@ static void smc_phy_check_media(struct net_device *dev, int init)
|
|||
lp->tcr_cur_mode &= ~TCR_SWFDUP;
|
||||
}
|
||||
|
||||
SMC_SELECT_BANK(0);
|
||||
SMC_SET_TCR(lp->tcr_cur_mode);
|
||||
SMC_SELECT_BANK(lp, 0);
|
||||
SMC_SET_TCR(lp, lp->tcr_cur_mode);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -1100,8 +1100,8 @@ static void smc_phy_configure(struct work_struct *work)
|
|||
PHY_INT_SPDDET | PHY_INT_DPLXDET);
|
||||
|
||||
/* Configure the Receive/Phy Control register */
|
||||
SMC_SELECT_BANK(0);
|
||||
SMC_SET_RPC(lp->rpc_cur_mode);
|
||||
SMC_SELECT_BANK(lp, 0);
|
||||
SMC_SET_RPC(lp, lp->rpc_cur_mode);
|
||||
|
||||
/* If the user requested no auto neg, then go set his request */
|
||||
if (lp->mii.force_media) {
|
||||
|
@ -1158,7 +1158,7 @@ static void smc_phy_configure(struct work_struct *work)
|
|||
smc_phy_check_media(dev, 1);
|
||||
|
||||
smc_phy_configure_exit:
|
||||
SMC_SELECT_BANK(2);
|
||||
SMC_SELECT_BANK(lp, 2);
|
||||
spin_unlock_irq(&lp->lock);
|
||||
lp->work_pending = 0;
|
||||
}
|
||||
|
@ -1200,9 +1200,9 @@ static void smc_10bt_check_media(struct net_device *dev, int init)
|
|||
|
||||
old_carrier = netif_carrier_ok(dev) ? 1 : 0;
|
||||
|
||||
SMC_SELECT_BANK(0);
|
||||
new_carrier = (SMC_GET_EPH_STATUS() & ES_LINK_OK) ? 1 : 0;
|
||||
SMC_SELECT_BANK(2);
|
||||
SMC_SELECT_BANK(lp, 0);
|
||||
new_carrier = (SMC_GET_EPH_STATUS(lp) & ES_LINK_OK) ? 1 : 0;
|
||||
SMC_SELECT_BANK(lp, 2);
|
||||
|
||||
if (init || (old_carrier != new_carrier)) {
|
||||
if (!new_carrier) {
|
||||
|
@ -1224,11 +1224,11 @@ static void smc_eph_interrupt(struct net_device *dev)
|
|||
|
||||
smc_10bt_check_media(dev, 0);
|
||||
|
||||
SMC_SELECT_BANK(1);
|
||||
ctl = SMC_GET_CTL();
|
||||
SMC_SET_CTL(ctl & ~CTL_LE_ENABLE);
|
||||
SMC_SET_CTL(ctl);
|
||||
SMC_SELECT_BANK(2);
|
||||
SMC_SELECT_BANK(lp, 1);
|
||||
ctl = SMC_GET_CTL(lp);
|
||||
SMC_SET_CTL(lp, ctl & ~CTL_LE_ENABLE);
|
||||
SMC_SET_CTL(lp, ctl);
|
||||
SMC_SELECT_BANK(lp, 2);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -1252,22 +1252,22 @@ static irqreturn_t smc_interrupt(int irq, void *dev_id)
|
|||
* ISR. */
|
||||
SMC_INTERRUPT_PREAMBLE;
|
||||
|
||||
saved_pointer = SMC_GET_PTR();
|
||||
mask = SMC_GET_INT_MASK();
|
||||
SMC_SET_INT_MASK(0);
|
||||
saved_pointer = SMC_GET_PTR(lp);
|
||||
mask = SMC_GET_INT_MASK(lp);
|
||||
SMC_SET_INT_MASK(lp, 0);
|
||||
|
||||
/* set a timeout value, so I don't stay here forever */
|
||||
timeout = MAX_IRQ_LOOPS;
|
||||
|
||||
do {
|
||||
status = SMC_GET_INT();
|
||||
status = SMC_GET_INT(lp);
|
||||
|
||||
DBG(2, "%s: INT 0x%02x MASK 0x%02x MEM 0x%04x FIFO 0x%04x\n",
|
||||
dev->name, status, mask,
|
||||
({ int meminfo; SMC_SELECT_BANK(0);
|
||||
meminfo = SMC_GET_MIR();
|
||||
SMC_SELECT_BANK(2); meminfo; }),
|
||||
SMC_GET_FIFO());
|
||||
({ int meminfo; SMC_SELECT_BANK(lp, 0);
|
||||
meminfo = SMC_GET_MIR(lp);
|
||||
SMC_SELECT_BANK(lp, 2); meminfo; }),
|
||||
SMC_GET_FIFO(lp));
|
||||
|
||||
status &= mask;
|
||||
if (!status)
|
||||
|
@ -1277,7 +1277,7 @@ static irqreturn_t smc_interrupt(int irq, void *dev_id)
|
|||
/* do this before RX as it will free memory quickly */
|
||||
DBG(3, "%s: TX int\n", dev->name);
|
||||
smc_tx(dev);
|
||||
SMC_ACK_INT(IM_TX_INT);
|
||||
SMC_ACK_INT(lp, IM_TX_INT);
|
||||
if (THROTTLE_TX_PKTS)
|
||||
netif_wake_queue(dev);
|
||||
} else if (status & IM_RCV_INT) {
|
||||
|
@ -1292,9 +1292,9 @@ static irqreturn_t smc_interrupt(int irq, void *dev_id)
|
|||
mask &= ~IM_TX_EMPTY_INT;
|
||||
|
||||
/* update stats */
|
||||
SMC_SELECT_BANK(0);
|
||||
card_stats = SMC_GET_COUNTER();
|
||||
SMC_SELECT_BANK(2);
|
||||
SMC_SELECT_BANK(lp, 0);
|
||||
card_stats = SMC_GET_COUNTER(lp);
|
||||
SMC_SELECT_BANK(lp, 2);
|
||||
|
||||
/* single collisions */
|
||||
dev->stats.collisions += card_stats & 0xF;
|
||||
|
@ -1304,26 +1304,26 @@ static irqreturn_t smc_interrupt(int irq, void *dev_id)
|
|||
dev->stats.collisions += card_stats & 0xF;
|
||||
} else if (status & IM_RX_OVRN_INT) {
|
||||
DBG(1, "%s: RX overrun (EPH_ST 0x%04x)\n", dev->name,
|
||||
({ int eph_st; SMC_SELECT_BANK(0);
|
||||
eph_st = SMC_GET_EPH_STATUS();
|
||||
SMC_SELECT_BANK(2); eph_st; }) );
|
||||
SMC_ACK_INT(IM_RX_OVRN_INT);
|
||||
({ int eph_st; SMC_SELECT_BANK(lp, 0);
|
||||
eph_st = SMC_GET_EPH_STATUS(lp);
|
||||
SMC_SELECT_BANK(lp, 2); eph_st; }));
|
||||
SMC_ACK_INT(lp, IM_RX_OVRN_INT);
|
||||
dev->stats.rx_errors++;
|
||||
dev->stats.rx_fifo_errors++;
|
||||
} else if (status & IM_EPH_INT) {
|
||||
smc_eph_interrupt(dev);
|
||||
} else if (status & IM_MDINT) {
|
||||
SMC_ACK_INT(IM_MDINT);
|
||||
SMC_ACK_INT(lp, IM_MDINT);
|
||||
smc_phy_interrupt(dev);
|
||||
} else if (status & IM_ERCV_INT) {
|
||||
SMC_ACK_INT(IM_ERCV_INT);
|
||||
SMC_ACK_INT(lp, IM_ERCV_INT);
|
||||
PRINTK("%s: UNSUPPORTED: ERCV INTERRUPT \n", dev->name);
|
||||
}
|
||||
} while (--timeout);
|
||||
|
||||
/* restore register states */
|
||||
SMC_SET_PTR(saved_pointer);
|
||||
SMC_SET_INT_MASK(mask);
|
||||
SMC_SET_PTR(lp, saved_pointer);
|
||||
SMC_SET_INT_MASK(lp, mask);
|
||||
spin_unlock(&lp->lock);
|
||||
|
||||
if (timeout == MAX_IRQ_LOOPS)
|
||||
|
@ -1366,13 +1366,13 @@ static void smc_timeout(struct net_device *dev)
|
|||
DBG(2, "%s: %s\n", dev->name, __FUNCTION__);
|
||||
|
||||
spin_lock_irq(&lp->lock);
|
||||
status = SMC_GET_INT();
|
||||
mask = SMC_GET_INT_MASK();
|
||||
fifo = SMC_GET_FIFO();
|
||||
SMC_SELECT_BANK(0);
|
||||
eph_st = SMC_GET_EPH_STATUS();
|
||||
meminfo = SMC_GET_MIR();
|
||||
SMC_SELECT_BANK(2);
|
||||
status = SMC_GET_INT(lp);
|
||||
mask = SMC_GET_INT_MASK(lp);
|
||||
fifo = SMC_GET_FIFO(lp);
|
||||
SMC_SELECT_BANK(lp, 0);
|
||||
eph_st = SMC_GET_EPH_STATUS(lp);
|
||||
meminfo = SMC_GET_MIR(lp);
|
||||
SMC_SELECT_BANK(lp, 2);
|
||||
spin_unlock_irq(&lp->lock);
|
||||
PRINTK( "%s: TX timeout (INT 0x%02x INTMASK 0x%02x "
|
||||
"MEM 0x%04x FIFO 0x%04x EPH_ST 0x%04x)\n",
|
||||
|
@ -1492,13 +1492,13 @@ static void smc_set_multicast_list(struct net_device *dev)
|
|||
}
|
||||
|
||||
spin_lock_irq(&lp->lock);
|
||||
SMC_SELECT_BANK(0);
|
||||
SMC_SET_RCR(lp->rcr_cur_mode);
|
||||
SMC_SELECT_BANK(lp, 0);
|
||||
SMC_SET_RCR(lp, lp->rcr_cur_mode);
|
||||
if (update_multicast) {
|
||||
SMC_SELECT_BANK(3);
|
||||
SMC_SET_MCAST(multicast_table);
|
||||
SMC_SELECT_BANK(lp, 3);
|
||||
SMC_SET_MCAST(lp, multicast_table);
|
||||
}
|
||||
SMC_SELECT_BANK(2);
|
||||
SMC_SELECT_BANK(lp, 2);
|
||||
spin_unlock_irq(&lp->lock);
|
||||
}
|
||||
|
||||
|
@ -1702,8 +1702,9 @@ static const struct ethtool_ops smc_ethtool_ops = {
|
|||
* I just deleted auto_irq.c, since it was never built...
|
||||
* --jgarzik
|
||||
*/
|
||||
static int __init smc_findirq(void __iomem *ioaddr)
|
||||
static int __init smc_findirq(struct smc_local *lp)
|
||||
{
|
||||
void __iomem *ioaddr = lp->base;
|
||||
int timeout = 20;
|
||||
unsigned long cookie;
|
||||
|
||||
|
@ -1717,14 +1718,14 @@ static int __init smc_findirq(void __iomem *ioaddr)
|
|||
* when done.
|
||||
*/
|
||||
/* enable ALLOCation interrupts ONLY */
|
||||
SMC_SELECT_BANK(2);
|
||||
SMC_SET_INT_MASK(IM_ALLOC_INT);
|
||||
SMC_SELECT_BANK(lp, 2);
|
||||
SMC_SET_INT_MASK(lp, IM_ALLOC_INT);
|
||||
|
||||
/*
|
||||
* Allocate 512 bytes of memory. Note that the chip was just
|
||||
* reset so all the memory is available
|
||||
*/
|
||||
SMC_SET_MMU_CMD(MC_ALLOC | 1);
|
||||
SMC_SET_MMU_CMD(lp, MC_ALLOC | 1);
|
||||
|
||||
/*
|
||||
* Wait until positive that the interrupt has been generated
|
||||
|
@ -1732,7 +1733,7 @@ static int __init smc_findirq(void __iomem *ioaddr)
|
|||
do {
|
||||
int int_status;
|
||||
udelay(10);
|
||||
int_status = SMC_GET_INT();
|
||||
int_status = SMC_GET_INT(lp);
|
||||
if (int_status & IM_ALLOC_INT)
|
||||
break; /* got the interrupt */
|
||||
} while (--timeout);
|
||||
|
@ -1745,7 +1746,7 @@ static int __init smc_findirq(void __iomem *ioaddr)
|
|||
*/
|
||||
|
||||
/* and disable all interrupts again */
|
||||
SMC_SET_INT_MASK(0);
|
||||
SMC_SET_INT_MASK(lp, 0);
|
||||
|
||||
/* and return what I found */
|
||||
return probe_irq_off(cookie);
|
||||
|
@ -1788,7 +1789,7 @@ static int __init smc_probe(struct net_device *dev, void __iomem *ioaddr,
|
|||
DBG(2, "%s: %s\n", CARDNAME, __FUNCTION__);
|
||||
|
||||
/* First, see if the high byte is 0x33 */
|
||||
val = SMC_CURRENT_BANK();
|
||||
val = SMC_CURRENT_BANK(lp);
|
||||
DBG(2, "%s: bank signature probe returned 0x%04x\n", CARDNAME, val);
|
||||
if ((val & 0xFF00) != 0x3300) {
|
||||
if ((val & 0xFF) == 0x33) {
|
||||
|
@ -1804,8 +1805,8 @@ static int __init smc_probe(struct net_device *dev, void __iomem *ioaddr,
|
|||
* The above MIGHT indicate a device, but I need to write to
|
||||
* further test this.
|
||||
*/
|
||||
SMC_SELECT_BANK(0);
|
||||
val = SMC_CURRENT_BANK();
|
||||
SMC_SELECT_BANK(lp, 0);
|
||||
val = SMC_CURRENT_BANK(lp);
|
||||
if ((val & 0xFF00) != 0x3300) {
|
||||
retval = -ENODEV;
|
||||
goto err_out;
|
||||
|
@ -1817,8 +1818,8 @@ static int __init smc_probe(struct net_device *dev, void __iomem *ioaddr,
|
|||
* register to bank 1, so I can access the base address
|
||||
* register
|
||||
*/
|
||||
SMC_SELECT_BANK(1);
|
||||
val = SMC_GET_BASE();
|
||||
SMC_SELECT_BANK(lp, 1);
|
||||
val = SMC_GET_BASE(lp);
|
||||
val = ((val & 0x1F00) >> 3) << SMC_IO_SHIFT;
|
||||
if (((unsigned int)ioaddr & (0x3e0 << SMC_IO_SHIFT)) != val) {
|
||||
printk("%s: IOADDR %p doesn't match configuration (%x).\n",
|
||||
|
@ -1830,8 +1831,8 @@ static int __init smc_probe(struct net_device *dev, void __iomem *ioaddr,
|
|||
* recognize. These might need to be added to later,
|
||||
* as future revisions could be added.
|
||||
*/
|
||||
SMC_SELECT_BANK(3);
|
||||
revision_register = SMC_GET_REV();
|
||||
SMC_SELECT_BANK(lp, 3);
|
||||
revision_register = SMC_GET_REV(lp);
|
||||
DBG(2, "%s: revision = 0x%04x\n", CARDNAME, revision_register);
|
||||
version_string = chip_ids[ (revision_register >> 4) & 0xF];
|
||||
if (!version_string || (revision_register & 0xff00) != 0x3300) {
|
||||
|
@ -1855,8 +1856,8 @@ static int __init smc_probe(struct net_device *dev, void __iomem *ioaddr,
|
|||
spin_lock_init(&lp->lock);
|
||||
|
||||
/* Get the MAC address */
|
||||
SMC_SELECT_BANK(1);
|
||||
SMC_GET_MAC_ADDR(dev->dev_addr);
|
||||
SMC_SELECT_BANK(lp, 1);
|
||||
SMC_GET_MAC_ADDR(lp, dev->dev_addr);
|
||||
|
||||
/* now, reset the chip, and put it into a known state */
|
||||
smc_reset(dev);
|
||||
|
@ -1881,7 +1882,7 @@ static int __init smc_probe(struct net_device *dev, void __iomem *ioaddr,
|
|||
|
||||
trials = 3;
|
||||
while (trials--) {
|
||||
dev->irq = smc_findirq(ioaddr);
|
||||
dev->irq = smc_findirq(lp);
|
||||
if (dev->irq)
|
||||
break;
|
||||
/* kick the card and try again */
|
||||
|
@ -1996,6 +1997,8 @@ err_out:
|
|||
|
||||
static int smc_enable_device(struct platform_device *pdev)
|
||||
{
|
||||
struct net_device *ndev = platform_get_drvdata(pdev);
|
||||
struct smc_local *lp = netdev_priv(ndev);
|
||||
unsigned long flags;
|
||||
unsigned char ecor, ecsr;
|
||||
void __iomem *addr;
|
||||
|
@ -2038,7 +2041,7 @@ static int smc_enable_device(struct platform_device *pdev)
|
|||
* Set the appropriate byte/word mode.
|
||||
*/
|
||||
ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8;
|
||||
if (!SMC_CAN_USE_16BIT)
|
||||
if (!SMC_16BIT(lp))
|
||||
ecsr |= ECSR_IOIS8;
|
||||
writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT));
|
||||
local_irq_restore(flags);
|
||||
|
@ -2123,10 +2126,11 @@ static void smc_release_datacs(struct platform_device *pdev, struct net_device *
|
|||
*/
|
||||
static int smc_drv_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct smc91x_platdata *pd = pdev->dev.platform_data;
|
||||
struct smc_local *lp;
|
||||
struct net_device *ndev;
|
||||
struct resource *res, *ires;
|
||||
unsigned int __iomem *addr;
|
||||
unsigned long irq_flags = SMC_IRQ_FLAGS;
|
||||
int ret;
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs");
|
||||
|
@ -2151,6 +2155,27 @@ static int smc_drv_probe(struct platform_device *pdev)
|
|||
}
|
||||
SET_NETDEV_DEV(ndev, &pdev->dev);
|
||||
|
||||
/* get configuration from platform data, only allow use of
|
||||
* bus width if both SMC_CAN_USE_xxx and SMC91X_USE_xxx are set.
|
||||
*/
|
||||
|
||||
lp = netdev_priv(ndev);
|
||||
lp->cfg.irq_flags = SMC_IRQ_FLAGS;
|
||||
|
||||
#ifdef SMC_DYNAMIC_BUS_CONFIG
|
||||
if (pd)
|
||||
memcpy(&lp->cfg, pd, sizeof(lp->cfg));
|
||||
else {
|
||||
lp->cfg.flags = SMC91X_USE_8BIT;
|
||||
lp->cfg.flags |= SMC91X_USE_16BIT;
|
||||
lp->cfg.flags |= SMC91X_USE_32BIT;
|
||||
}
|
||||
|
||||
lp->cfg.flags &= ~(SMC_CAN_USE_8BIT ? 0 : SMC91X_USE_8BIT);
|
||||
lp->cfg.flags &= ~(SMC_CAN_USE_16BIT ? 0 : SMC91X_USE_16BIT);
|
||||
lp->cfg.flags &= ~(SMC_CAN_USE_32BIT ? 0 : SMC91X_USE_32BIT);
|
||||
#endif
|
||||
|
||||
ndev->dma = (unsigned char)-1;
|
||||
|
||||
ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
||||
|
@ -2161,7 +2186,7 @@ static int smc_drv_probe(struct platform_device *pdev)
|
|||
|
||||
ndev->irq = ires->start;
|
||||
if (SMC_IRQ_FLAGS == -1)
|
||||
irq_flags = ires->flags & IRQF_TRIGGER_MASK;
|
||||
lp->cfg.irq_flags = ires->flags & IRQF_TRIGGER_MASK;
|
||||
|
||||
ret = smc_request_attrib(pdev);
|
||||
if (ret)
|
||||
|
@ -2169,6 +2194,7 @@ static int smc_drv_probe(struct platform_device *pdev)
|
|||
#if defined(CONFIG_SA1100_ASSABET)
|
||||
NCR_0 |= NCR_ENET_OSC_EN;
|
||||
#endif
|
||||
platform_set_drvdata(pdev, ndev);
|
||||
ret = smc_enable_device(pdev);
|
||||
if (ret)
|
||||
goto out_release_attrib;
|
||||
|
@ -2187,8 +2213,7 @@ static int smc_drv_probe(struct platform_device *pdev)
|
|||
}
|
||||
#endif
|
||||
|
||||
platform_set_drvdata(pdev, ndev);
|
||||
ret = smc_probe(ndev, addr, irq_flags);
|
||||
ret = smc_probe(ndev, addr, lp->cfg.irq_flags);
|
||||
if (ret != 0)
|
||||
goto out_iounmap;
|
||||
|
||||
|
|
|
@ -34,6 +34,7 @@
|
|||
#ifndef _SMC91X_H_
|
||||
#define _SMC91X_H_
|
||||
|
||||
#include <linux/smc91x.h>
|
||||
|
||||
/*
|
||||
* Define your architecture specific bus configuration parameters here.
|
||||
|
@ -291,36 +292,6 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg)
|
|||
#define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
|
||||
#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
|
||||
|
||||
#elif defined(CONFIG_SUPERH)
|
||||
|
||||
#ifdef CONFIG_SOLUTION_ENGINE
|
||||
#define SMC_IRQ_FLAGS (0)
|
||||
#define SMC_CAN_USE_8BIT 0
|
||||
#define SMC_CAN_USE_16BIT 1
|
||||
#define SMC_CAN_USE_32BIT 0
|
||||
#define SMC_IO_SHIFT 0
|
||||
#define SMC_NOWAIT 1
|
||||
|
||||
#define SMC_inw(a, r) inw((a) + (r))
|
||||
#define SMC_outw(v, a, r) outw(v, (a) + (r))
|
||||
#define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
|
||||
#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
|
||||
|
||||
#else /* BOARDS */
|
||||
|
||||
#define SMC_CAN_USE_8BIT 1
|
||||
#define SMC_CAN_USE_16BIT 1
|
||||
#define SMC_CAN_USE_32BIT 0
|
||||
|
||||
#define SMC_inb(a, r) inb((a) + (r))
|
||||
#define SMC_inw(a, r) inw((a) + (r))
|
||||
#define SMC_outb(v, a, r) outb(v, (a) + (r))
|
||||
#define SMC_outw(v, a, r) outw(v, (a) + (r))
|
||||
#define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
|
||||
#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
|
||||
|
||||
#endif /* BOARDS */
|
||||
|
||||
#elif defined(CONFIG_M32R)
|
||||
|
||||
#define SMC_CAN_USE_8BIT 0
|
||||
|
@ -475,12 +446,15 @@ static inline void LPD7_SMC_outsw (unsigned char* a, int r,
|
|||
#define SMC_outb(v, a, r) writeb(v, (a) + (r))
|
||||
#define SMC_outw(v, a, r) writew(v, (a) + (r))
|
||||
#define SMC_outl(v, a, r) writel(v, (a) + (r))
|
||||
#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
|
||||
#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
|
||||
#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
|
||||
#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
|
||||
|
||||
#define RPC_LSA_DEFAULT RPC_LED_100_10
|
||||
#define RPC_LSB_DEFAULT RPC_LED_TX_RX
|
||||
|
||||
#define SMC_DYNAMIC_BUS_CONFIG
|
||||
#endif
|
||||
|
||||
|
||||
|
@ -526,8 +500,19 @@ struct smc_local {
|
|||
#endif
|
||||
void __iomem *base;
|
||||
void __iomem *datacs;
|
||||
|
||||
struct smc91x_platdata cfg;
|
||||
};
|
||||
|
||||
#ifdef SMC_DYNAMIC_BUS_CONFIG
|
||||
#define SMC_8BIT(p) (((p)->cfg.flags & SMC91X_USE_8BIT) && SMC_CAN_USE_8BIT)
|
||||
#define SMC_16BIT(p) (((p)->cfg.flags & SMC91X_USE_16BIT) && SMC_CAN_USE_16BIT)
|
||||
#define SMC_32BIT(p) (((p)->cfg.flags & SMC91X_USE_32BIT) && SMC_CAN_USE_32BIT)
|
||||
#else
|
||||
#define SMC_8BIT(p) SMC_CAN_USE_8BIT
|
||||
#define SMC_16BIT(p) SMC_CAN_USE_16BIT
|
||||
#define SMC_32BIT(p) SMC_CAN_USE_32BIT
|
||||
#endif
|
||||
|
||||
#ifdef SMC_USE_PXA_DMA
|
||||
/*
|
||||
|
@ -720,7 +705,7 @@ smc_pxa_dma_irq(int dma, void *dummy)
|
|||
|
||||
// Transmit Control Register
|
||||
/* BANK 0 */
|
||||
#define TCR_REG SMC_REG(0x0000, 0)
|
||||
#define TCR_REG(lp) SMC_REG(lp, 0x0000, 0)
|
||||
#define TCR_ENABLE 0x0001 // When 1 we can transmit
|
||||
#define TCR_LOOP 0x0002 // Controls output pin LBK
|
||||
#define TCR_FORCOL 0x0004 // When 1 will force a collision
|
||||
|
@ -739,7 +724,7 @@ smc_pxa_dma_irq(int dma, void *dummy)
|
|||
|
||||
// EPH Status Register
|
||||
/* BANK 0 */
|
||||
#define EPH_STATUS_REG SMC_REG(0x0002, 0)
|
||||
#define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0)
|
||||
#define ES_TX_SUC 0x0001 // Last TX was successful
|
||||
#define ES_SNGL_COL 0x0002 // Single collision detected for last tx
|
||||
#define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
|
||||
|
@ -758,7 +743,7 @@ smc_pxa_dma_irq(int dma, void *dummy)
|
|||
|
||||
// Receive Control Register
|
||||
/* BANK 0 */
|
||||
#define RCR_REG SMC_REG(0x0004, 0)
|
||||
#define RCR_REG(lp) SMC_REG(lp, 0x0004, 0)
|
||||
#define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
|
||||
#define RCR_PRMS 0x0002 // Enable promiscuous mode
|
||||
#define RCR_ALMUL 0x0004 // When set accepts all multicast frames
|
||||
|
@ -775,17 +760,17 @@ smc_pxa_dma_irq(int dma, void *dummy)
|
|||
|
||||
// Counter Register
|
||||
/* BANK 0 */
|
||||
#define COUNTER_REG SMC_REG(0x0006, 0)
|
||||
#define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
|
||||
|
||||
|
||||
// Memory Information Register
|
||||
/* BANK 0 */
|
||||
#define MIR_REG SMC_REG(0x0008, 0)
|
||||
#define MIR_REG(lp) SMC_REG(lp, 0x0008, 0)
|
||||
|
||||
|
||||
// Receive/Phy Control Register
|
||||
/* BANK 0 */
|
||||
#define RPC_REG SMC_REG(0x000A, 0)
|
||||
#define RPC_REG(lp) SMC_REG(lp, 0x000A, 0)
|
||||
#define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
|
||||
#define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
|
||||
#define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
|
||||
|
@ -819,7 +804,7 @@ smc_pxa_dma_irq(int dma, void *dummy)
|
|||
|
||||
// Configuration Reg
|
||||
/* BANK 1 */
|
||||
#define CONFIG_REG SMC_REG(0x0000, 1)
|
||||
#define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1)
|
||||
#define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
|
||||
#define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
|
||||
#define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
|
||||
|
@ -831,24 +816,24 @@ smc_pxa_dma_irq(int dma, void *dummy)
|
|||
|
||||
// Base Address Register
|
||||
/* BANK 1 */
|
||||
#define BASE_REG SMC_REG(0x0002, 1)
|
||||
#define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
|
||||
|
||||
|
||||
// Individual Address Registers
|
||||
/* BANK 1 */
|
||||
#define ADDR0_REG SMC_REG(0x0004, 1)
|
||||
#define ADDR1_REG SMC_REG(0x0006, 1)
|
||||
#define ADDR2_REG SMC_REG(0x0008, 1)
|
||||
#define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1)
|
||||
#define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1)
|
||||
#define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1)
|
||||
|
||||
|
||||
// General Purpose Register
|
||||
/* BANK 1 */
|
||||
#define GP_REG SMC_REG(0x000A, 1)
|
||||
#define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
|
||||
|
||||
|
||||
// Control Register
|
||||
/* BANK 1 */
|
||||
#define CTL_REG SMC_REG(0x000C, 1)
|
||||
#define CTL_REG(lp) SMC_REG(lp, 0x000C, 1)
|
||||
#define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
|
||||
#define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
|
||||
#define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
|
||||
|
@ -861,7 +846,7 @@ smc_pxa_dma_irq(int dma, void *dummy)
|
|||
|
||||
// MMU Command Register
|
||||
/* BANK 2 */
|
||||
#define MMU_CMD_REG SMC_REG(0x0000, 2)
|
||||
#define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
|
||||
#define MC_BUSY 1 // When 1 the last release has not completed
|
||||
#define MC_NOP (0<<5) // No Op
|
||||
#define MC_ALLOC (1<<5) // OR with number of 256 byte packets
|
||||
|
@ -875,30 +860,30 @@ smc_pxa_dma_irq(int dma, void *dummy)
|
|||
|
||||
// Packet Number Register
|
||||
/* BANK 2 */
|
||||
#define PN_REG SMC_REG(0x0002, 2)
|
||||
#define PN_REG(lp) SMC_REG(lp, 0x0002, 2)
|
||||
|
||||
|
||||
// Allocation Result Register
|
||||
/* BANK 2 */
|
||||
#define AR_REG SMC_REG(0x0003, 2)
|
||||
#define AR_REG(lp) SMC_REG(lp, 0x0003, 2)
|
||||
#define AR_FAILED 0x80 // Alocation Failed
|
||||
|
||||
|
||||
// TX FIFO Ports Register
|
||||
/* BANK 2 */
|
||||
#define TXFIFO_REG SMC_REG(0x0004, 2)
|
||||
#define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
|
||||
#define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
|
||||
|
||||
// RX FIFO Ports Register
|
||||
/* BANK 2 */
|
||||
#define RXFIFO_REG SMC_REG(0x0005, 2)
|
||||
#define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2)
|
||||
#define RXFIFO_REMPTY 0x80 // RX FIFO Empty
|
||||
|
||||
#define FIFO_REG SMC_REG(0x0004, 2)
|
||||
#define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
|
||||
|
||||
// Pointer Register
|
||||
/* BANK 2 */
|
||||
#define PTR_REG SMC_REG(0x0006, 2)
|
||||
#define PTR_REG(lp) SMC_REG(lp, 0x0006, 2)
|
||||
#define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
|
||||
#define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
|
||||
#define PTR_READ 0x2000 // When 1 the operation is a read
|
||||
|
@ -906,17 +891,17 @@ smc_pxa_dma_irq(int dma, void *dummy)
|
|||
|
||||
// Data Register
|
||||
/* BANK 2 */
|
||||
#define DATA_REG SMC_REG(0x0008, 2)
|
||||
#define DATA_REG(lp) SMC_REG(lp, 0x0008, 2)
|
||||
|
||||
|
||||
// Interrupt Status/Acknowledge Register
|
||||
/* BANK 2 */
|
||||
#define INT_REG SMC_REG(0x000C, 2)
|
||||
#define INT_REG(lp) SMC_REG(lp, 0x000C, 2)
|
||||
|
||||
|
||||
// Interrupt Mask Register
|
||||
/* BANK 2 */
|
||||
#define IM_REG SMC_REG(0x000D, 2)
|
||||
#define IM_REG(lp) SMC_REG(lp, 0x000D, 2)
|
||||
#define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
|
||||
#define IM_ERCV_INT 0x40 // Early Receive Interrupt
|
||||
#define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
|
||||
|
@ -929,15 +914,15 @@ smc_pxa_dma_irq(int dma, void *dummy)
|
|||
|
||||
// Multicast Table Registers
|
||||
/* BANK 3 */
|
||||
#define MCAST_REG1 SMC_REG(0x0000, 3)
|
||||
#define MCAST_REG2 SMC_REG(0x0002, 3)
|
||||
#define MCAST_REG3 SMC_REG(0x0004, 3)
|
||||
#define MCAST_REG4 SMC_REG(0x0006, 3)
|
||||
#define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3)
|
||||
#define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3)
|
||||
#define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3)
|
||||
#define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3)
|
||||
|
||||
|
||||
// Management Interface Register (MII)
|
||||
/* BANK 3 */
|
||||
#define MII_REG SMC_REG(0x0008, 3)
|
||||
#define MII_REG(lp) SMC_REG(lp, 0x0008, 3)
|
||||
#define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
|
||||
#define MII_MDOE 0x0008 // MII Output Enable
|
||||
#define MII_MCLK 0x0004 // MII Clock, pin MDCLK
|
||||
|
@ -948,20 +933,20 @@ smc_pxa_dma_irq(int dma, void *dummy)
|
|||
// Revision Register
|
||||
/* BANK 3 */
|
||||
/* ( hi: chip id low: rev # ) */
|
||||
#define REV_REG SMC_REG(0x000A, 3)
|
||||
#define REV_REG(lp) SMC_REG(lp, 0x000A, 3)
|
||||
|
||||
|
||||
// Early RCV Register
|
||||
/* BANK 3 */
|
||||
/* this is NOT on SMC9192 */
|
||||
#define ERCV_REG SMC_REG(0x000C, 3)
|
||||
#define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3)
|
||||
#define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
|
||||
#define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
|
||||
|
||||
|
||||
// External Register
|
||||
/* BANK 7 */
|
||||
#define EXT_REG SMC_REG(0x0000, 7)
|
||||
#define EXT_REG(lp) SMC_REG(lp, 0x0000, 7)
|
||||
|
||||
|
||||
#define CHIP_9192 3
|
||||
|
@ -1085,9 +1070,9 @@ static const char * chip_ids[ 16 ] = {
|
|||
*/
|
||||
|
||||
#if SMC_DEBUG > 0
|
||||
#define SMC_REG(reg, bank) \
|
||||
#define SMC_REG(lp, reg, bank) \
|
||||
({ \
|
||||
int __b = SMC_CURRENT_BANK(); \
|
||||
int __b = SMC_CURRENT_BANK(lp); \
|
||||
if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
|
||||
printk( "%s: bank reg screwed (0x%04x)\n", \
|
||||
CARDNAME, __b ); \
|
||||
|
@ -1096,7 +1081,7 @@ static const char * chip_ids[ 16 ] = {
|
|||
reg<<SMC_IO_SHIFT; \
|
||||
})
|
||||
#else
|
||||
#define SMC_REG(reg, bank) (reg<<SMC_IO_SHIFT)
|
||||
#define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT)
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
@ -1108,212 +1093,215 @@ static const char * chip_ids[ 16 ] = {
|
|||
*
|
||||
* Enforce it on any 32-bit capable setup for now.
|
||||
*/
|
||||
#define SMC_MUST_ALIGN_WRITE SMC_CAN_USE_32BIT
|
||||
#define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp)
|
||||
|
||||
#define SMC_GET_PN() \
|
||||
( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, PN_REG)) \
|
||||
: (SMC_inw(ioaddr, PN_REG) & 0xFF) )
|
||||
#define SMC_GET_PN(lp) \
|
||||
(SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \
|
||||
: (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
|
||||
|
||||
#define SMC_SET_PN(x) \
|
||||
#define SMC_SET_PN(lp, x) \
|
||||
do { \
|
||||
if (SMC_MUST_ALIGN_WRITE) \
|
||||
SMC_outl((x)<<16, ioaddr, SMC_REG(0, 2)); \
|
||||
else if (SMC_CAN_USE_8BIT) \
|
||||
SMC_outb(x, ioaddr, PN_REG); \
|
||||
if (SMC_MUST_ALIGN_WRITE(lp)) \
|
||||
SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
|
||||
else if (SMC_8BIT(lp)) \
|
||||
SMC_outb(x, ioaddr, PN_REG(lp)); \
|
||||
else \
|
||||
SMC_outw(x, ioaddr, PN_REG); \
|
||||
SMC_outw(x, ioaddr, PN_REG(lp)); \
|
||||
} while (0)
|
||||
|
||||
#define SMC_GET_AR() \
|
||||
( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, AR_REG)) \
|
||||
: (SMC_inw(ioaddr, PN_REG) >> 8) )
|
||||
#define SMC_GET_AR(lp) \
|
||||
(SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \
|
||||
: (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
|
||||
|
||||
#define SMC_GET_TXFIFO() \
|
||||
( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, TXFIFO_REG)) \
|
||||
: (SMC_inw(ioaddr, TXFIFO_REG) & 0xFF) )
|
||||
#define SMC_GET_TXFIFO(lp) \
|
||||
(SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \
|
||||
: (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
|
||||
|
||||
#define SMC_GET_RXFIFO() \
|
||||
( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, RXFIFO_REG)) \
|
||||
: (SMC_inw(ioaddr, TXFIFO_REG) >> 8) )
|
||||
#define SMC_GET_RXFIFO(lp) \
|
||||
(SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \
|
||||
: (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
|
||||
|
||||
#define SMC_GET_INT() \
|
||||
( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, INT_REG)) \
|
||||
: (SMC_inw(ioaddr, INT_REG) & 0xFF) )
|
||||
#define SMC_GET_INT(lp) \
|
||||
(SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \
|
||||
: (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
|
||||
|
||||
#define SMC_ACK_INT(x) \
|
||||
#define SMC_ACK_INT(lp, x) \
|
||||
do { \
|
||||
if (SMC_CAN_USE_8BIT) \
|
||||
SMC_outb(x, ioaddr, INT_REG); \
|
||||
if (SMC_8BIT(lp)) \
|
||||
SMC_outb(x, ioaddr, INT_REG(lp)); \
|
||||
else { \
|
||||
unsigned long __flags; \
|
||||
int __mask; \
|
||||
local_irq_save(__flags); \
|
||||
__mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \
|
||||
SMC_outw( __mask | (x), ioaddr, INT_REG ); \
|
||||
__mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
|
||||
SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \
|
||||
local_irq_restore(__flags); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define SMC_GET_INT_MASK() \
|
||||
( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, IM_REG)) \
|
||||
: (SMC_inw( ioaddr, INT_REG ) >> 8) )
|
||||
#define SMC_GET_INT_MASK(lp) \
|
||||
(SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \
|
||||
: (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
|
||||
|
||||
#define SMC_SET_INT_MASK(x) \
|
||||
#define SMC_SET_INT_MASK(lp, x) \
|
||||
do { \
|
||||
if (SMC_CAN_USE_8BIT) \
|
||||
SMC_outb(x, ioaddr, IM_REG); \
|
||||
if (SMC_8BIT(lp)) \
|
||||
SMC_outb(x, ioaddr, IM_REG(lp)); \
|
||||
else \
|
||||
SMC_outw((x) << 8, ioaddr, INT_REG); \
|
||||
SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \
|
||||
} while (0)
|
||||
|
||||
#define SMC_CURRENT_BANK() SMC_inw(ioaddr, BANK_SELECT)
|
||||
#define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT)
|
||||
|
||||
#define SMC_SELECT_BANK(x) \
|
||||
#define SMC_SELECT_BANK(lp, x) \
|
||||
do { \
|
||||
if (SMC_MUST_ALIGN_WRITE) \
|
||||
if (SMC_MUST_ALIGN_WRITE(lp)) \
|
||||
SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
|
||||
else \
|
||||
SMC_outw(x, ioaddr, BANK_SELECT); \
|
||||
} while (0)
|
||||
|
||||
#define SMC_GET_BASE() SMC_inw(ioaddr, BASE_REG)
|
||||
#define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp))
|
||||
|
||||
#define SMC_SET_BASE(x) SMC_outw(x, ioaddr, BASE_REG)
|
||||
#define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp))
|
||||
|
||||
#define SMC_GET_CONFIG() SMC_inw(ioaddr, CONFIG_REG)
|
||||
#define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp))
|
||||
|
||||
#define SMC_SET_CONFIG(x) SMC_outw(x, ioaddr, CONFIG_REG)
|
||||
#define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp))
|
||||
|
||||
#define SMC_GET_COUNTER() SMC_inw(ioaddr, COUNTER_REG)
|
||||
#define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp))
|
||||
|
||||
#define SMC_GET_CTL() SMC_inw(ioaddr, CTL_REG)
|
||||
#define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp))
|
||||
|
||||
#define SMC_SET_CTL(x) SMC_outw(x, ioaddr, CTL_REG)
|
||||
#define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp))
|
||||
|
||||
#define SMC_GET_MII() SMC_inw(ioaddr, MII_REG)
|
||||
#define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp))
|
||||
|
||||
#define SMC_SET_MII(x) SMC_outw(x, ioaddr, MII_REG)
|
||||
#define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp))
|
||||
|
||||
#define SMC_GET_MIR() SMC_inw(ioaddr, MIR_REG)
|
||||
#define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp))
|
||||
|
||||
#define SMC_SET_MIR(x) SMC_outw(x, ioaddr, MIR_REG)
|
||||
#define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp))
|
||||
|
||||
#define SMC_GET_MMU_CMD() SMC_inw(ioaddr, MMU_CMD_REG)
|
||||
#define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp))
|
||||
|
||||
#define SMC_SET_MMU_CMD(x) SMC_outw(x, ioaddr, MMU_CMD_REG)
|
||||
#define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp))
|
||||
|
||||
#define SMC_GET_FIFO() SMC_inw(ioaddr, FIFO_REG)
|
||||
#define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp))
|
||||
|
||||
#define SMC_GET_PTR() SMC_inw(ioaddr, PTR_REG)
|
||||
#define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp))
|
||||
|
||||
#define SMC_SET_PTR(x) \
|
||||
#define SMC_SET_PTR(lp, x) \
|
||||
do { \
|
||||
if (SMC_MUST_ALIGN_WRITE) \
|
||||
SMC_outl((x)<<16, ioaddr, SMC_REG(4, 2)); \
|
||||
if (SMC_MUST_ALIGN_WRITE(lp)) \
|
||||
SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
|
||||
else \
|
||||
SMC_outw(x, ioaddr, PTR_REG); \
|
||||
SMC_outw(x, ioaddr, PTR_REG(lp)); \
|
||||
} while (0)
|
||||
|
||||
#define SMC_GET_EPH_STATUS() SMC_inw(ioaddr, EPH_STATUS_REG)
|
||||
#define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp))
|
||||
|
||||
#define SMC_GET_RCR() SMC_inw(ioaddr, RCR_REG)
|
||||
#define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp))
|
||||
|
||||
#define SMC_SET_RCR(x) SMC_outw(x, ioaddr, RCR_REG)
|
||||
#define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp))
|
||||
|
||||
#define SMC_GET_REV() SMC_inw(ioaddr, REV_REG)
|
||||
#define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp))
|
||||
|
||||
#define SMC_GET_RPC() SMC_inw(ioaddr, RPC_REG)
|
||||
#define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp))
|
||||
|
||||
#define SMC_SET_RPC(x) \
|
||||
#define SMC_SET_RPC(lp, x) \
|
||||
do { \
|
||||
if (SMC_MUST_ALIGN_WRITE) \
|
||||
SMC_outl((x)<<16, ioaddr, SMC_REG(8, 0)); \
|
||||
if (SMC_MUST_ALIGN_WRITE(lp)) \
|
||||
SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \
|
||||
else \
|
||||
SMC_outw(x, ioaddr, RPC_REG); \
|
||||
SMC_outw(x, ioaddr, RPC_REG(lp)); \
|
||||
} while (0)
|
||||
|
||||
#define SMC_GET_TCR() SMC_inw(ioaddr, TCR_REG)
|
||||
#define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp))
|
||||
|
||||
#define SMC_SET_TCR(x) SMC_outw(x, ioaddr, TCR_REG)
|
||||
#define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp))
|
||||
|
||||
#ifndef SMC_GET_MAC_ADDR
|
||||
#define SMC_GET_MAC_ADDR(addr) \
|
||||
#define SMC_GET_MAC_ADDR(lp, addr) \
|
||||
do { \
|
||||
unsigned int __v; \
|
||||
__v = SMC_inw( ioaddr, ADDR0_REG ); \
|
||||
__v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
|
||||
addr[0] = __v; addr[1] = __v >> 8; \
|
||||
__v = SMC_inw( ioaddr, ADDR1_REG ); \
|
||||
__v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
|
||||
addr[2] = __v; addr[3] = __v >> 8; \
|
||||
__v = SMC_inw( ioaddr, ADDR2_REG ); \
|
||||
__v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
|
||||
addr[4] = __v; addr[5] = __v >> 8; \
|
||||
} while (0)
|
||||
#endif
|
||||
|
||||
#define SMC_SET_MAC_ADDR(addr) \
|
||||
#define SMC_SET_MAC_ADDR(lp, addr) \
|
||||
do { \
|
||||
SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \
|
||||
SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \
|
||||
SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \
|
||||
SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
|
||||
SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
|
||||
SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
|
||||
} while (0)
|
||||
|
||||
#define SMC_SET_MCAST(x) \
|
||||
#define SMC_SET_MCAST(lp, x) \
|
||||
do { \
|
||||
const unsigned char *mt = (x); \
|
||||
SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \
|
||||
SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \
|
||||
SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \
|
||||
SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \
|
||||
SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
|
||||
SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
|
||||
SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
|
||||
SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
|
||||
} while (0)
|
||||
|
||||
#define SMC_PUT_PKT_HDR(status, length) \
|
||||
#define SMC_PUT_PKT_HDR(lp, status, length) \
|
||||
do { \
|
||||
if (SMC_CAN_USE_32BIT) \
|
||||
SMC_outl((status) | (length)<<16, ioaddr, DATA_REG); \
|
||||
if (SMC_32BIT(lp)) \
|
||||
SMC_outl((status) | (length)<<16, ioaddr, \
|
||||
DATA_REG(lp)); \
|
||||
else { \
|
||||
SMC_outw(status, ioaddr, DATA_REG); \
|
||||
SMC_outw(length, ioaddr, DATA_REG); \
|
||||
SMC_outw(status, ioaddr, DATA_REG(lp)); \
|
||||
SMC_outw(length, ioaddr, DATA_REG(lp)); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define SMC_GET_PKT_HDR(status, length) \
|
||||
#define SMC_GET_PKT_HDR(lp, status, length) \
|
||||
do { \
|
||||
if (SMC_CAN_USE_32BIT) { \
|
||||
unsigned int __val = SMC_inl(ioaddr, DATA_REG); \
|
||||
if (SMC_32BIT(lp)) { \
|
||||
unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
|
||||
(status) = __val & 0xffff; \
|
||||
(length) = __val >> 16; \
|
||||
} else { \
|
||||
(status) = SMC_inw(ioaddr, DATA_REG); \
|
||||
(length) = SMC_inw(ioaddr, DATA_REG); \
|
||||
(status) = SMC_inw(ioaddr, DATA_REG(lp)); \
|
||||
(length) = SMC_inw(ioaddr, DATA_REG(lp)); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define SMC_PUSH_DATA(p, l) \
|
||||
#define SMC_PUSH_DATA(lp, p, l) \
|
||||
do { \
|
||||
if (SMC_CAN_USE_32BIT) { \
|
||||
if (SMC_32BIT(lp)) { \
|
||||
void *__ptr = (p); \
|
||||
int __len = (l); \
|
||||
void __iomem *__ioaddr = ioaddr; \
|
||||
if (__len >= 2 && (unsigned long)__ptr & 2) { \
|
||||
__len -= 2; \
|
||||
SMC_outw(*(u16 *)__ptr, ioaddr, DATA_REG); \
|
||||
SMC_outw(*(u16 *)__ptr, ioaddr, \
|
||||
DATA_REG(lp)); \
|
||||
__ptr += 2; \
|
||||
} \
|
||||
if (SMC_CAN_USE_DATACS && lp->datacs) \
|
||||
__ioaddr = lp->datacs; \
|
||||
SMC_outsl(__ioaddr, DATA_REG, __ptr, __len>>2); \
|
||||
SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
|
||||
if (__len & 2) { \
|
||||
__ptr += (__len & ~3); \
|
||||
SMC_outw(*((u16 *)__ptr), ioaddr, DATA_REG); \
|
||||
SMC_outw(*((u16 *)__ptr), ioaddr, \
|
||||
DATA_REG(lp)); \
|
||||
} \
|
||||
} else if (SMC_CAN_USE_16BIT) \
|
||||
SMC_outsw(ioaddr, DATA_REG, p, (l) >> 1); \
|
||||
else if (SMC_CAN_USE_8BIT) \
|
||||
SMC_outsb(ioaddr, DATA_REG, p, l); \
|
||||
} else if (SMC_16BIT(lp)) \
|
||||
SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
|
||||
else if (SMC_8BIT(lp)) \
|
||||
SMC_outsb(ioaddr, DATA_REG(lp), p, l); \
|
||||
} while (0)
|
||||
|
||||
#define SMC_PULL_DATA(p, l) \
|
||||
#define SMC_PULL_DATA(lp, p, l) \
|
||||
do { \
|
||||
if (SMC_CAN_USE_32BIT) { \
|
||||
if (SMC_32BIT(lp)) { \
|
||||
void *__ptr = (p); \
|
||||
int __len = (l); \
|
||||
void __iomem *__ioaddr = ioaddr; \
|
||||
|
@ -1333,16 +1321,17 @@ static const char * chip_ids[ 16 ] = {
|
|||
*/ \
|
||||
__ptr -= 2; \
|
||||
__len += 2; \
|
||||
SMC_SET_PTR(2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
|
||||
SMC_SET_PTR(lp, \
|
||||
2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
|
||||
} \
|
||||
if (SMC_CAN_USE_DATACS && lp->datacs) \
|
||||
__ioaddr = lp->datacs; \
|
||||
__len += 2; \
|
||||
SMC_insl(__ioaddr, DATA_REG, __ptr, __len>>2); \
|
||||
} else if (SMC_CAN_USE_16BIT) \
|
||||
SMC_insw(ioaddr, DATA_REG, p, (l) >> 1); \
|
||||
else if (SMC_CAN_USE_8BIT) \
|
||||
SMC_insb(ioaddr, DATA_REG, p, l); \
|
||||
SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
|
||||
} else if (SMC_16BIT(lp)) \
|
||||
SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
|
||||
else if (SMC_8BIT(lp)) \
|
||||
SMC_insb(ioaddr, DATA_REG(lp), p, l); \
|
||||
} while (0)
|
||||
|
||||
#endif /* _SMC91X_H_ */
|
||||
|
|
|
@ -141,7 +141,7 @@ config ULI526X
|
|||
be called uli526x.
|
||||
|
||||
config PCMCIA_XIRCOM
|
||||
tristate "Xircom CardBus support (new driver)"
|
||||
tristate "Xircom CardBus support"
|
||||
depends on CARDBUS
|
||||
---help---
|
||||
This driver is for the Digital "Tulip" Ethernet CardBus adapters.
|
||||
|
@ -152,17 +152,4 @@ config PCMCIA_XIRCOM
|
|||
To compile this driver as a module, choose M here. The module will
|
||||
be called xircom_cb. If unsure, say N.
|
||||
|
||||
config PCMCIA_XIRTULIP
|
||||
tristate "Xircom Tulip-like CardBus support (old driver)"
|
||||
depends on CARDBUS && BROKEN_ON_SMP
|
||||
select CRC32
|
||||
---help---
|
||||
This driver is for the Digital "Tulip" Ethernet CardBus adapters.
|
||||
It should work with most DEC 21*4*-based chips/ethercards, as well
|
||||
as with work-alike chips from Lite-On (PNIC) and Macronix (MXIC) and
|
||||
ASIX.
|
||||
|
||||
To compile this driver as a module, choose M here. The module will
|
||||
be called xircom_tulip_cb. If unsure, say N.
|
||||
|
||||
endif # NET_TULIP
|
||||
|
|
|
@ -2,7 +2,6 @@
|
|||
# Makefile for the Linux "Tulip" family network device drivers.
|
||||
#
|
||||
|
||||
obj-$(CONFIG_PCMCIA_XIRTULIP) += xircom_tulip_cb.o
|
||||
obj-$(CONFIG_PCMCIA_XIRCOM) += xircom_cb.o
|
||||
obj-$(CONFIG_DM9102) += dmfe.o
|
||||
obj-$(CONFIG_WINBOND_840) += winbond-840.o
|
||||
|
|
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
@ -5,22 +5,25 @@ config LCS
|
|||
tristate "Lan Channel Station Interface"
|
||||
depends on CCW && NETDEVICES && (NET_ETHERNET || TR || FDDI)
|
||||
help
|
||||
Select this option if you want to use LCS networking on IBM S/390
|
||||
or zSeries. This device driver supports Token Ring (IEEE 802.5),
|
||||
Select this option if you want to use LCS networking on IBM System z.
|
||||
This device driver supports Token Ring (IEEE 802.5),
|
||||
FDDI (IEEE 802.7) and Ethernet.
|
||||
This option is also available as a module which will be
|
||||
called lcs.ko. If you do not know what it is, it's safe to say "Y".
|
||||
To compile as a module, choose M. The module name is lcs.ko.
|
||||
If you do not know what it is, it's safe to choose Y.
|
||||
|
||||
config CTC
|
||||
tristate "CTC device support"
|
||||
config CTCM
|
||||
tristate "CTC and MPC SNA device support"
|
||||
depends on CCW && NETDEVICES
|
||||
help
|
||||
Select this option if you want to use channel-to-channel networking
|
||||
on IBM S/390 or zSeries. This device driver supports real CTC
|
||||
coupling using ESCON. It also supports virtual CTCs when running
|
||||
under VM. It will use the channel device configuration if this is
|
||||
available. This option is also available as a module which will be
|
||||
called ctc.ko. If you do not know what it is, it's safe to say "Y".
|
||||
Select this option if you want to use channel-to-channel
|
||||
point-to-point networking on IBM System z.
|
||||
This device driver supports real CTC coupling using ESCON.
|
||||
It also supports virtual CTCs when running under VM.
|
||||
This driver also supports channel-to-channel MPC SNA devices.
|
||||
MPC is an SNA protocol device used by Communication Server for Linux.
|
||||
To compile as a module, choose M. The module name is ctcm.ko.
|
||||
To compile into the kernel, choose Y.
|
||||
If you do not need any channel-to-channel connection, choose N.
|
||||
|
||||
config NETIUCV
|
||||
tristate "IUCV network device support (VM only)"
|
||||
|
@ -29,9 +32,9 @@ config NETIUCV
|
|||
Select this option if you want to use inter-user communication
|
||||
vehicle networking under VM or VIF. It enables a fast communication
|
||||
link between VM guests. Using ifconfig a point-to-point connection
|
||||
can be established to the Linux for zSeries and S7390 system
|
||||
running on the other VM guest. This option is also available
|
||||
as a module which will be called netiucv.ko. If unsure, say "Y".
|
||||
can be established to the Linux on IBM System z
|
||||
running on the other VM guest. To compile as a module, choose M.
|
||||
The module name is netiucv.ko. If unsure, choose Y.
|
||||
|
||||
config SMSGIUCV
|
||||
tristate "IUCV special message support (VM only)"
|
||||
|
@ -47,43 +50,46 @@ config CLAW
|
|||
This driver supports channel attached CLAW devices.
|
||||
CLAW is Common Link Access for Workstation. Common devices
|
||||
that use CLAW are RS/6000s, Cisco Routers (CIP) and 3172 devices.
|
||||
To compile as a module choose M here: The module will be called
|
||||
claw.ko to compile into the kernel choose Y
|
||||
To compile as a module, choose M. The module name is claw.ko.
|
||||
To compile into the kernel, choose Y.
|
||||
|
||||
config QETH
|
||||
tristate "Gigabit Ethernet device support"
|
||||
depends on CCW && NETDEVICES && IP_MULTICAST && QDIO
|
||||
help
|
||||
This driver supports the IBM S/390 and zSeries OSA Express adapters
|
||||
This driver supports the IBM System z OSA Express adapters
|
||||
in QDIO mode (all media types), HiperSockets interfaces and VM GuestLAN
|
||||
interfaces in QDIO and HIPER mode.
|
||||
|
||||
For details please refer to the documentation provided by IBM at
|
||||
<http://www10.software.ibm.com/developerworks/opensource/linux390>
|
||||
<http://www.ibm.com/developerworks/linux/linux390>
|
||||
|
||||
To compile this driver as a module, choose M here: the
|
||||
module will be called qeth.ko.
|
||||
To compile this driver as a module, choose M.
|
||||
The module name is qeth.ko.
|
||||
|
||||
|
||||
comment "Gigabit Ethernet default settings"
|
||||
config QETH_L2
|
||||
tristate "qeth layer 2 device support"
|
||||
depends on QETH
|
||||
help
|
||||
Select this option to be able to run qeth devices in layer 2 mode.
|
||||
To compile as a module, choose M. The module name is qeth_l2.ko.
|
||||
If unsure, choose y.
|
||||
|
||||
config QETH_L3
|
||||
tristate "qeth layer 3 device support"
|
||||
depends on QETH
|
||||
help
|
||||
Select this option to be able to run qeth devices in layer 3 mode.
|
||||
To compile as a module choose M. The module name is qeth_l3.ko.
|
||||
If unsure, choose Y.
|
||||
|
||||
config QETH_IPV6
|
||||
bool "IPv6 support for gigabit ethernet"
|
||||
depends on (QETH = IPV6) || (QETH && IPV6 = 'y')
|
||||
help
|
||||
If CONFIG_QETH is switched on, this option will include IPv6
|
||||
support in the qeth device driver.
|
||||
|
||||
config QETH_VLAN
|
||||
bool "VLAN support for gigabit ethernet"
|
||||
depends on (QETH = VLAN_8021Q) || (QETH && VLAN_8021Q = 'y')
|
||||
help
|
||||
If CONFIG_QETH is switched on, this option will include IEEE
|
||||
802.1q VLAN support in the qeth device driver.
|
||||
bool
|
||||
depends on (QETH_L3 = IPV6) || (QETH_L3 && IPV6 = 'y')
|
||||
default y
|
||||
|
||||
config CCWGROUP
|
||||
tristate
|
||||
default (LCS || CTC || QETH)
|
||||
default (LCS || CTCM || QETH)
|
||||
|
||||
endmenu
|
||||
|
|
|
@ -2,13 +2,15 @@
|
|||
# S/390 network devices
|
||||
#
|
||||
|
||||
ctc-objs := ctcmain.o ctcdbug.o
|
||||
|
||||
ctcm-y += ctcm_main.o ctcm_fsms.o ctcm_mpc.o ctcm_sysfs.o ctcm_dbug.o
|
||||
obj-$(CONFIG_CTCM) += ctcm.o fsm.o cu3088.o
|
||||
obj-$(CONFIG_NETIUCV) += netiucv.o fsm.o
|
||||
obj-$(CONFIG_SMSGIUCV) += smsgiucv.o
|
||||
obj-$(CONFIG_CTC) += ctc.o fsm.o cu3088.o
|
||||
obj-$(CONFIG_LCS) += lcs.o cu3088.o
|
||||
obj-$(CONFIG_CLAW) += claw.o cu3088.o
|
||||
qeth-y := qeth_main.o qeth_mpc.o qeth_sys.o qeth_eddp.o
|
||||
qeth-$(CONFIG_PROC_FS) += qeth_proc.o
|
||||
qeth-y += qeth_core_sys.o qeth_core_main.o qeth_core_mpc.o qeth_core_offl.o
|
||||
obj-$(CONFIG_QETH) += qeth.o
|
||||
qeth_l2-y += qeth_l2_main.o
|
||||
obj-$(CONFIG_QETH_L2) += qeth_l2.o
|
||||
qeth_l3-y += qeth_l3_main.o qeth_l3_sys.o
|
||||
obj-$(CONFIG_QETH_L3) += qeth_l3.o
|
||||
|
|
|
@ -1,80 +0,0 @@
|
|||
/*
|
||||
*
|
||||
* linux/drivers/s390/net/ctcdbug.c
|
||||
*
|
||||
* CTC / ESCON network driver - s390 dbf exploit.
|
||||
*
|
||||
* Copyright 2000,2003 IBM Corporation
|
||||
*
|
||||
* Author(s): Original Code written by
|
||||
* Peter Tiedemann (ptiedem@de.ibm.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#include "ctcdbug.h"
|
||||
|
||||
/**
|
||||
* Debug Facility Stuff
|
||||
*/
|
||||
debug_info_t *ctc_dbf_setup = NULL;
|
||||
debug_info_t *ctc_dbf_data = NULL;
|
||||
debug_info_t *ctc_dbf_trace = NULL;
|
||||
|
||||
DEFINE_PER_CPU(char[256], ctc_dbf_txt_buf);
|
||||
|
||||
void
|
||||
ctc_unregister_dbf_views(void)
|
||||
{
|
||||
if (ctc_dbf_setup)
|
||||
debug_unregister(ctc_dbf_setup);
|
||||
if (ctc_dbf_data)
|
||||
debug_unregister(ctc_dbf_data);
|
||||
if (ctc_dbf_trace)
|
||||
debug_unregister(ctc_dbf_trace);
|
||||
}
|
||||
int
|
||||
ctc_register_dbf_views(void)
|
||||
{
|
||||
ctc_dbf_setup = debug_register(CTC_DBF_SETUP_NAME,
|
||||
CTC_DBF_SETUP_PAGES,
|
||||
CTC_DBF_SETUP_NR_AREAS,
|
||||
CTC_DBF_SETUP_LEN);
|
||||
ctc_dbf_data = debug_register(CTC_DBF_DATA_NAME,
|
||||
CTC_DBF_DATA_PAGES,
|
||||
CTC_DBF_DATA_NR_AREAS,
|
||||
CTC_DBF_DATA_LEN);
|
||||
ctc_dbf_trace = debug_register(CTC_DBF_TRACE_NAME,
|
||||
CTC_DBF_TRACE_PAGES,
|
||||
CTC_DBF_TRACE_NR_AREAS,
|
||||
CTC_DBF_TRACE_LEN);
|
||||
|
||||
if ((ctc_dbf_setup == NULL) || (ctc_dbf_data == NULL) ||
|
||||
(ctc_dbf_trace == NULL)) {
|
||||
ctc_unregister_dbf_views();
|
||||
return -ENOMEM;
|
||||
}
|
||||
debug_register_view(ctc_dbf_setup, &debug_hex_ascii_view);
|
||||
debug_set_level(ctc_dbf_setup, CTC_DBF_SETUP_LEVEL);
|
||||
|
||||
debug_register_view(ctc_dbf_data, &debug_hex_ascii_view);
|
||||
debug_set_level(ctc_dbf_data, CTC_DBF_DATA_LEVEL);
|
||||
|
||||
debug_register_view(ctc_dbf_trace, &debug_hex_ascii_view);
|
||||
debug_set_level(ctc_dbf_trace, CTC_DBF_TRACE_LEVEL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1,125 +0,0 @@
|
|||
/*
|
||||
*
|
||||
* linux/drivers/s390/net/ctcdbug.h
|
||||
*
|
||||
* CTC / ESCON network driver - s390 dbf exploit.
|
||||
*
|
||||
* Copyright 2000,2003 IBM Corporation
|
||||
*
|
||||
* Author(s): Original Code written by
|
||||
* Peter Tiedemann (ptiedem@de.ibm.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
#ifndef _CTCDBUG_H_
|
||||
#define _CTCDBUG_H_
|
||||
|
||||
#include <asm/debug.h>
|
||||
#include "ctcmain.h"
|
||||
/**
|
||||
* Debug Facility stuff
|
||||
*/
|
||||
#define CTC_DBF_SETUP_NAME "ctc_setup"
|
||||
#define CTC_DBF_SETUP_LEN 16
|
||||
#define CTC_DBF_SETUP_PAGES 8
|
||||
#define CTC_DBF_SETUP_NR_AREAS 1
|
||||
#define CTC_DBF_SETUP_LEVEL 3
|
||||
|
||||
#define CTC_DBF_DATA_NAME "ctc_data"
|
||||
#define CTC_DBF_DATA_LEN 128
|
||||
#define CTC_DBF_DATA_PAGES 8
|
||||
#define CTC_DBF_DATA_NR_AREAS 1
|
||||
#define CTC_DBF_DATA_LEVEL 3
|
||||
|
||||
#define CTC_DBF_TRACE_NAME "ctc_trace"
|
||||
#define CTC_DBF_TRACE_LEN 16
|
||||
#define CTC_DBF_TRACE_PAGES 4
|
||||
#define CTC_DBF_TRACE_NR_AREAS 2
|
||||
#define CTC_DBF_TRACE_LEVEL 3
|
||||
|
||||
#define DBF_TEXT(name,level,text) \
|
||||
do { \
|
||||
debug_text_event(ctc_dbf_##name,level,text); \
|
||||
} while (0)
|
||||
|
||||
#define DBF_HEX(name,level,addr,len) \
|
||||
do { \
|
||||
debug_event(ctc_dbf_##name,level,(void*)(addr),len); \
|
||||
} while (0)
|
||||
|
||||
DECLARE_PER_CPU(char[256], ctc_dbf_txt_buf);
|
||||
extern debug_info_t *ctc_dbf_setup;
|
||||
extern debug_info_t *ctc_dbf_data;
|
||||
extern debug_info_t *ctc_dbf_trace;
|
||||
|
||||
|
||||
#define DBF_TEXT_(name,level,text...) \
|
||||
do { \
|
||||
char* ctc_dbf_txt_buf = get_cpu_var(ctc_dbf_txt_buf); \
|
||||
sprintf(ctc_dbf_txt_buf, text); \
|
||||
debug_text_event(ctc_dbf_##name,level,ctc_dbf_txt_buf); \
|
||||
put_cpu_var(ctc_dbf_txt_buf); \
|
||||
} while (0)
|
||||
|
||||
#define DBF_SPRINTF(name,level,text...) \
|
||||
do { \
|
||||
debug_sprintf_event(ctc_dbf_trace, level, ##text ); \
|
||||
debug_sprintf_event(ctc_dbf_trace, level, text ); \
|
||||
} while (0)
|
||||
|
||||
|
||||
int ctc_register_dbf_views(void);
|
||||
|
||||
void ctc_unregister_dbf_views(void);
|
||||
|
||||
/**
|
||||
* some more debug stuff
|
||||
*/
|
||||
|
||||
#define HEXDUMP16(importance,header,ptr) \
|
||||
PRINT_##importance(header "%02x %02x %02x %02x %02x %02x %02x %02x " \
|
||||
"%02x %02x %02x %02x %02x %02x %02x %02x\n", \
|
||||
*(((char*)ptr)),*(((char*)ptr)+1),*(((char*)ptr)+2), \
|
||||
*(((char*)ptr)+3),*(((char*)ptr)+4),*(((char*)ptr)+5), \
|
||||
*(((char*)ptr)+6),*(((char*)ptr)+7),*(((char*)ptr)+8), \
|
||||
*(((char*)ptr)+9),*(((char*)ptr)+10),*(((char*)ptr)+11), \
|
||||
*(((char*)ptr)+12),*(((char*)ptr)+13), \
|
||||
*(((char*)ptr)+14),*(((char*)ptr)+15)); \
|
||||
PRINT_##importance(header "%02x %02x %02x %02x %02x %02x %02x %02x " \
|
||||
"%02x %02x %02x %02x %02x %02x %02x %02x\n", \
|
||||
*(((char*)ptr)+16),*(((char*)ptr)+17), \
|
||||
*(((char*)ptr)+18),*(((char*)ptr)+19), \
|
||||
*(((char*)ptr)+20),*(((char*)ptr)+21), \
|
||||
*(((char*)ptr)+22),*(((char*)ptr)+23), \
|
||||
*(((char*)ptr)+24),*(((char*)ptr)+25), \
|
||||
*(((char*)ptr)+26),*(((char*)ptr)+27), \
|
||||
*(((char*)ptr)+28),*(((char*)ptr)+29), \
|
||||
*(((char*)ptr)+30),*(((char*)ptr)+31));
|
||||
|
||||
static inline void
|
||||
hex_dump(unsigned char *buf, size_t len)
|
||||
{
|
||||
size_t i;
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
if (i && !(i % 16))
|
||||
printk("\n");
|
||||
printk("%02x ", *(buf + i));
|
||||
}
|
||||
printk("\n");
|
||||
}
|
||||
|
||||
|
||||
#endif
|
|
@ -0,0 +1,67 @@
|
|||
/*
|
||||
* drivers/s390/net/ctcm_dbug.c
|
||||
*
|
||||
* Copyright IBM Corp. 2001, 2007
|
||||
* Authors: Peter Tiedemann (ptiedem@de.ibm.com)
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/stddef.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/ctype.h>
|
||||
#include <linux/sysctl.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/fs.h>
|
||||
#include <linux/debugfs.h>
|
||||
#include "ctcm_dbug.h"
|
||||
|
||||
/*
|
||||
* Debug Facility Stuff
|
||||
*/
|
||||
|
||||
DEFINE_PER_CPU(char[256], ctcm_dbf_txt_buf);
|
||||
|
||||
struct ctcm_dbf_info ctcm_dbf[CTCM_DBF_INFOS] = {
|
||||
[CTCM_DBF_SETUP] = {"ctc_setup", 8, 1, 64, 5, NULL},
|
||||
[CTCM_DBF_ERROR] = {"ctc_error", 8, 1, 64, 3, NULL},
|
||||
[CTCM_DBF_TRACE] = {"ctc_trace", 8, 1, 64, 3, NULL},
|
||||
[CTCM_DBF_MPC_SETUP] = {"mpc_setup", 8, 1, 64, 5, NULL},
|
||||
[CTCM_DBF_MPC_ERROR] = {"mpc_error", 8, 1, 64, 3, NULL},
|
||||
[CTCM_DBF_MPC_TRACE] = {"mpc_trace", 8, 1, 64, 3, NULL},
|
||||
};
|
||||
|
||||
void ctcm_unregister_dbf_views(void)
|
||||
{
|
||||
int x;
|
||||
for (x = 0; x < CTCM_DBF_INFOS; x++) {
|
||||
debug_unregister(ctcm_dbf[x].id);
|
||||
ctcm_dbf[x].id = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
int ctcm_register_dbf_views(void)
|
||||
{
|
||||
int x;
|
||||
for (x = 0; x < CTCM_DBF_INFOS; x++) {
|
||||
/* register the areas */
|
||||
ctcm_dbf[x].id = debug_register(ctcm_dbf[x].name,
|
||||
ctcm_dbf[x].pages,
|
||||
ctcm_dbf[x].areas,
|
||||
ctcm_dbf[x].len);
|
||||
if (ctcm_dbf[x].id == NULL) {
|
||||
ctcm_unregister_dbf_views();
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/* register a view */
|
||||
debug_register_view(ctcm_dbf[x].id, &debug_hex_ascii_view);
|
||||
/* set a passing level */
|
||||
debug_set_level(ctcm_dbf[x].id, ctcm_dbf[x].level);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,158 @@
|
|||
/*
|
||||
* drivers/s390/net/ctcm_dbug.h
|
||||
*
|
||||
* Copyright IBM Corp. 2001, 2007
|
||||
* Authors: Peter Tiedemann (ptiedem@de.ibm.com)
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _CTCM_DBUG_H_
|
||||
#define _CTCM_DBUG_H_
|
||||
|
||||
/*
|
||||
* Debug Facility stuff
|
||||
*/
|
||||
|
||||
#include <asm/debug.h>
|
||||
|
||||
#ifdef DEBUG
|
||||
#define do_debug 1
|
||||
#else
|
||||
#define do_debug 0
|
||||
#endif
|
||||
#ifdef DEBUGDATA
|
||||
#define do_debug_data 1
|
||||
#else
|
||||
#define do_debug_data 0
|
||||
#endif
|
||||
#ifdef DEBUGCCW
|
||||
#define do_debug_ccw 1
|
||||
#else
|
||||
#define do_debug_ccw 0
|
||||
#endif
|
||||
|
||||
/* define dbf debug levels similar to kernel msg levels */
|
||||
#define CTC_DBF_ALWAYS 0 /* always print this */
|
||||
#define CTC_DBF_EMERG 0 /* system is unusable */
|
||||
#define CTC_DBF_ALERT 1 /* action must be taken immediately */
|
||||
#define CTC_DBF_CRIT 2 /* critical conditions */
|
||||
#define CTC_DBF_ERROR 3 /* error conditions */
|
||||
#define CTC_DBF_WARN 4 /* warning conditions */
|
||||
#define CTC_DBF_NOTICE 5 /* normal but significant condition */
|
||||
#define CTC_DBF_INFO 5 /* informational */
|
||||
#define CTC_DBF_DEBUG 6 /* debug-level messages */
|
||||
|
||||
DECLARE_PER_CPU(char[256], ctcm_dbf_txt_buf);
|
||||
|
||||
enum ctcm_dbf_names {
|
||||
CTCM_DBF_SETUP,
|
||||
CTCM_DBF_ERROR,
|
||||
CTCM_DBF_TRACE,
|
||||
CTCM_DBF_MPC_SETUP,
|
||||
CTCM_DBF_MPC_ERROR,
|
||||
CTCM_DBF_MPC_TRACE,
|
||||
CTCM_DBF_INFOS /* must be last element */
|
||||
};
|
||||
|
||||
struct ctcm_dbf_info {
|
||||
char name[DEBUG_MAX_NAME_LEN];
|
||||
int pages;
|
||||
int areas;
|
||||
int len;
|
||||
int level;
|
||||
debug_info_t *id;
|
||||
};
|
||||
|
||||
extern struct ctcm_dbf_info ctcm_dbf[CTCM_DBF_INFOS];
|
||||
|
||||
int ctcm_register_dbf_views(void);
|
||||
void ctcm_unregister_dbf_views(void);
|
||||
|
||||
static inline const char *strtail(const char *s, int n)
|
||||
{
|
||||
int l = strlen(s);
|
||||
return (l > n) ? s + (l - n) : s;
|
||||
}
|
||||
|
||||
/* sort out levels early to avoid unnecessary sprintfs */
|
||||
static inline int ctcm_dbf_passes(debug_info_t *dbf_grp, int level)
|
||||
{
|
||||
return (dbf_grp->level >= level);
|
||||
}
|
||||
|
||||
#define CTCM_FUNTAIL strtail((char *)__func__, 16)
|
||||
|
||||
#define CTCM_DBF_TEXT(name, level, text) \
|
||||
do { \
|
||||
debug_text_event(ctcm_dbf[CTCM_DBF_##name].id, level, text); \
|
||||
} while (0)
|
||||
|
||||
#define CTCM_DBF_HEX(name, level, addr, len) \
|
||||
do { \
|
||||
debug_event(ctcm_dbf[CTCM_DBF_##name].id, \
|
||||
level, (void *)(addr), len); \
|
||||
} while (0)
|
||||
|
||||
#define CTCM_DBF_TEXT_(name, level, text...) \
|
||||
do { \
|
||||
if (ctcm_dbf_passes(ctcm_dbf[CTCM_DBF_##name].id, level)) { \
|
||||
char *ctcm_dbf_txt_buf = \
|
||||
get_cpu_var(ctcm_dbf_txt_buf); \
|
||||
sprintf(ctcm_dbf_txt_buf, text); \
|
||||
debug_text_event(ctcm_dbf[CTCM_DBF_##name].id, \
|
||||
level, ctcm_dbf_txt_buf); \
|
||||
put_cpu_var(ctcm_dbf_txt_buf); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
/*
|
||||
* cat : one of {setup, mpc_setup, trace, mpc_trace, error, mpc_error}.
|
||||
* dev : netdevice with valid name field.
|
||||
* text: any text string.
|
||||
*/
|
||||
#define CTCM_DBF_DEV_NAME(cat, dev, text) \
|
||||
do { \
|
||||
CTCM_DBF_TEXT_(cat, CTC_DBF_INFO, "%s(%s) : %s", \
|
||||
CTCM_FUNTAIL, dev->name, text); \
|
||||
} while (0)
|
||||
|
||||
#define MPC_DBF_DEV_NAME(cat, dev, text) \
|
||||
do { \
|
||||
CTCM_DBF_TEXT_(MPC_##cat, CTC_DBF_INFO, "%s(%s) : %s", \
|
||||
CTCM_FUNTAIL, dev->name, text); \
|
||||
} while (0)
|
||||
|
||||
#define CTCMY_DBF_DEV_NAME(cat, dev, text) \
|
||||
do { \
|
||||
if (IS_MPCDEV(dev)) \
|
||||
MPC_DBF_DEV_NAME(cat, dev, text); \
|
||||
else \
|
||||
CTCM_DBF_DEV_NAME(cat, dev, text); \
|
||||
} while (0)
|
||||
|
||||
/*
|
||||
* cat : one of {setup, mpc_setup, trace, mpc_trace, error, mpc_error}.
|
||||
* dev : netdevice.
|
||||
* text: any text string.
|
||||
*/
|
||||
#define CTCM_DBF_DEV(cat, dev, text) \
|
||||
do { \
|
||||
CTCM_DBF_TEXT_(cat, CTC_DBF_INFO, "%s(%p) : %s", \
|
||||
CTCM_FUNTAIL, dev, text); \
|
||||
} while (0)
|
||||
|
||||
#define MPC_DBF_DEV(cat, dev, text) \
|
||||
do { \
|
||||
CTCM_DBF_TEXT_(MPC_##cat, CTC_DBF_INFO, "%s(%p) : %s", \
|
||||
CTCM_FUNTAIL, dev, text); \
|
||||
} while (0)
|
||||
|
||||
#define CTCMY_DBF_DEV(cat, dev, text) \
|
||||
do { \
|
||||
if (IS_MPCDEV(dev)) \
|
||||
MPC_DBF_DEV(cat, dev, text); \
|
||||
else \
|
||||
CTCM_DBF_DEV(cat, dev, text); \
|
||||
} while (0)
|
||||
|
||||
#endif
|
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
@ -0,0 +1,359 @@
|
|||
/*
|
||||
* drivers/s390/net/ctcm_fsms.h
|
||||
*
|
||||
* Copyright IBM Corp. 2001, 2007
|
||||
* Authors: Fritz Elfert (felfert@millenux.com)
|
||||
* Peter Tiedemann (ptiedem@de.ibm.com)
|
||||
* MPC additions :
|
||||
* Belinda Thompson (belindat@us.ibm.com)
|
||||
* Andy Richter (richtera@us.ibm.com)
|
||||
*/
|
||||
#ifndef _CTCM_FSMS_H_
|
||||
#define _CTCM_FSMS_H_
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/timer.h>
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#include <linux/signal.h>
|
||||
#include <linux/string.h>
|
||||
|
||||
#include <linux/ip.h>
|
||||
#include <linux/if_arp.h>
|
||||
#include <linux/tcp.h>
|
||||
#include <linux/skbuff.h>
|
||||
#include <linux/ctype.h>
|
||||
#include <net/dst.h>
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <asm/ccwdev.h>
|
||||
#include <asm/ccwgroup.h>
|
||||
#include <linux/uaccess.h>
|
||||
|
||||
#include <asm/idals.h>
|
||||
|
||||
#include "fsm.h"
|
||||
#include "cu3088.h"
|
||||
#include "ctcm_main.h"
|
||||
|
||||
/*
|
||||
* Definitions for the channel statemachine(s) for ctc and ctcmpc
|
||||
*
|
||||
* To allow better kerntyping, prefix-less definitions for channel states
|
||||
* and channel events have been replaced :
|
||||
* ch_event... -> ctc_ch_event...
|
||||
* CH_EVENT... -> CTC_EVENT...
|
||||
* ch_state... -> ctc_ch_state...
|
||||
* CH_STATE... -> CTC_STATE...
|
||||
*/
|
||||
/*
|
||||
* Events of the channel statemachine(s) for ctc and ctcmpc
|
||||
*/
|
||||
enum ctc_ch_events {
|
||||
/*
|
||||
* Events, representing return code of
|
||||
* I/O operations (ccw_device_start, ccw_device_halt et al.)
|
||||
*/
|
||||
CTC_EVENT_IO_SUCCESS,
|
||||
CTC_EVENT_IO_EBUSY,
|
||||
CTC_EVENT_IO_ENODEV,
|
||||
CTC_EVENT_IO_UNKNOWN,
|
||||
|
||||
CTC_EVENT_ATTNBUSY,
|
||||
CTC_EVENT_ATTN,
|
||||
CTC_EVENT_BUSY,
|
||||
/*
|
||||
* Events, representing unit-check
|
||||
*/
|
||||
CTC_EVENT_UC_RCRESET,
|
||||
CTC_EVENT_UC_RSRESET,
|
||||
CTC_EVENT_UC_TXTIMEOUT,
|
||||
CTC_EVENT_UC_TXPARITY,
|
||||
CTC_EVENT_UC_HWFAIL,
|
||||
CTC_EVENT_UC_RXPARITY,
|
||||
CTC_EVENT_UC_ZERO,
|
||||
CTC_EVENT_UC_UNKNOWN,
|
||||
/*
|
||||
* Events, representing subchannel-check
|
||||
*/
|
||||
CTC_EVENT_SC_UNKNOWN,
|
||||
/*
|
||||
* Events, representing machine checks
|
||||
*/
|
||||
CTC_EVENT_MC_FAIL,
|
||||
CTC_EVENT_MC_GOOD,
|
||||
/*
|
||||
* Event, representing normal IRQ
|
||||
*/
|
||||
CTC_EVENT_IRQ,
|
||||
CTC_EVENT_FINSTAT,
|
||||
/*
|
||||
* Event, representing timer expiry.
|
||||
*/
|
||||
CTC_EVENT_TIMER,
|
||||
/*
|
||||
* Events, representing commands from upper levels.
|
||||
*/
|
||||
CTC_EVENT_START,
|
||||
CTC_EVENT_STOP,
|
||||
CTC_NR_EVENTS,
|
||||
/*
|
||||
* additional MPC events
|
||||
*/
|
||||
CTC_EVENT_SEND_XID = CTC_NR_EVENTS,
|
||||
CTC_EVENT_RSWEEP_TIMER,
|
||||
/*
|
||||
* MUST be always the last element!!
|
||||
*/
|
||||
CTC_MPC_NR_EVENTS,
|
||||
};
|
||||
|
||||
/*
|
||||
* States of the channel statemachine(s) for ctc and ctcmpc.
|
||||
*/
|
||||
enum ctc_ch_states {
|
||||
/*
|
||||
* Channel not assigned to any device,
|
||||
* initial state, direction invalid
|
||||
*/
|
||||
CTC_STATE_IDLE,
|
||||
/*
|
||||
* Channel assigned but not operating
|
||||
*/
|
||||
CTC_STATE_STOPPED,
|
||||
CTC_STATE_STARTWAIT,
|
||||
CTC_STATE_STARTRETRY,
|
||||
CTC_STATE_SETUPWAIT,
|
||||
CTC_STATE_RXINIT,
|
||||
CTC_STATE_TXINIT,
|
||||
CTC_STATE_RX,
|
||||
CTC_STATE_TX,
|
||||
CTC_STATE_RXIDLE,
|
||||
CTC_STATE_TXIDLE,
|
||||
CTC_STATE_RXERR,
|
||||
CTC_STATE_TXERR,
|
||||
CTC_STATE_TERM,
|
||||
CTC_STATE_DTERM,
|
||||
CTC_STATE_NOTOP,
|
||||
CTC_NR_STATES, /* MUST be the last element of non-expanded states */
|
||||
/*
|
||||
* additional MPC states
|
||||
*/
|
||||
CH_XID0_PENDING = CTC_NR_STATES,
|
||||
CH_XID0_INPROGRESS,
|
||||
CH_XID7_PENDING,
|
||||
CH_XID7_PENDING1,
|
||||
CH_XID7_PENDING2,
|
||||
CH_XID7_PENDING3,
|
||||
CH_XID7_PENDING4,
|
||||
CTC_MPC_NR_STATES, /* MUST be the last element of expanded mpc states */
|
||||
};
|
||||
|
||||
extern const char *ctc_ch_event_names[];
|
||||
|
||||
extern const char *ctc_ch_state_names[];
|
||||
|
||||
void ctcm_ccw_check_rc(struct channel *ch, int rc, char *msg);
|
||||
void ctcm_purge_skb_queue(struct sk_buff_head *q);
|
||||
void fsm_action_nop(fsm_instance *fi, int event, void *arg);
|
||||
|
||||
/*
|
||||
* ----- non-static actions for ctcm channel statemachine -----
|
||||
*
|
||||
*/
|
||||
void ctcm_chx_txidle(fsm_instance *fi, int event, void *arg);
|
||||
|
||||
/*
|
||||
* ----- FSM (state/event/action) of the ctcm channel statemachine -----
|
||||
*/
|
||||
extern const fsm_node ch_fsm[];
|
||||
extern int ch_fsm_len;
|
||||
|
||||
|
||||
/*
|
||||
* ----- non-static actions for ctcmpc channel statemachine ----
|
||||
*
|
||||
*/
|
||||
/* shared :
|
||||
void ctcm_chx_txidle(fsm_instance * fi, int event, void *arg);
|
||||
*/
|
||||
void ctcmpc_chx_rxidle(fsm_instance *fi, int event, void *arg);
|
||||
|
||||
/*
|
||||
* ----- FSM (state/event/action) of the ctcmpc channel statemachine -----
|
||||
*/
|
||||
extern const fsm_node ctcmpc_ch_fsm[];
|
||||
extern int mpc_ch_fsm_len;
|
||||
|
||||
/*
|
||||
* Definitions for the device interface statemachine for ctc and mpc
|
||||
*/
|
||||
|
||||
/*
|
||||
* States of the device interface statemachine.
|
||||
*/
|
||||
enum dev_states {
|
||||
DEV_STATE_STOPPED,
|
||||
DEV_STATE_STARTWAIT_RXTX,
|
||||
DEV_STATE_STARTWAIT_RX,
|
||||
DEV_STATE_STARTWAIT_TX,
|
||||
DEV_STATE_STOPWAIT_RXTX,
|
||||
DEV_STATE_STOPWAIT_RX,
|
||||
DEV_STATE_STOPWAIT_TX,
|
||||
DEV_STATE_RUNNING,
|
||||
/*
|
||||
* MUST be always the last element!!
|
||||
*/
|
||||
CTCM_NR_DEV_STATES
|
||||
};
|
||||
|
||||
extern const char *dev_state_names[];
|
||||
|
||||
/*
|
||||
* Events of the device interface statemachine.
|
||||
* ctcm and ctcmpc
|
||||
*/
|
||||
enum dev_events {
|
||||
DEV_EVENT_START,
|
||||
DEV_EVENT_STOP,
|
||||
DEV_EVENT_RXUP,
|
||||
DEV_EVENT_TXUP,
|
||||
DEV_EVENT_RXDOWN,
|
||||
DEV_EVENT_TXDOWN,
|
||||
DEV_EVENT_RESTART,
|
||||
/*
|
||||
* MUST be always the last element!!
|
||||
*/
|
||||
CTCM_NR_DEV_EVENTS
|
||||
};
|
||||
|
||||
extern const char *dev_event_names[];
|
||||
|
||||
/*
|
||||
* Actions for the device interface statemachine.
|
||||
* ctc and ctcmpc
|
||||
*/
|
||||
/*
|
||||
static void dev_action_start(fsm_instance * fi, int event, void *arg);
|
||||
static void dev_action_stop(fsm_instance * fi, int event, void *arg);
|
||||
static void dev_action_restart(fsm_instance *fi, int event, void *arg);
|
||||
static void dev_action_chup(fsm_instance * fi, int event, void *arg);
|
||||
static void dev_action_chdown(fsm_instance * fi, int event, void *arg);
|
||||
*/
|
||||
|
||||
/*
|
||||
* The (state/event/action) fsm table of the device interface statemachine.
|
||||
* ctcm and ctcmpc
|
||||
*/
|
||||
extern const fsm_node dev_fsm[];
|
||||
extern int dev_fsm_len;
|
||||
|
||||
|
||||
/*
|
||||
* Definitions for the MPC Group statemachine
|
||||
*/
|
||||
|
||||
/*
|
||||
* MPC Group Station FSM States
|
||||
|
||||
State Name When In This State
|
||||
====================== =======================================
|
||||
MPCG_STATE_RESET Initial State When Driver Loaded
|
||||
We receive and send NOTHING
|
||||
|
||||
MPCG_STATE_INOP INOP Received.
|
||||
Group level non-recoverable error
|
||||
|
||||
MPCG_STATE_READY XID exchanges for at least 1 write and
|
||||
1 read channel have completed.
|
||||
Group is ready for data transfer.
|
||||
|
||||
States from ctc_mpc_alloc_channel
|
||||
==============================================================
|
||||
MPCG_STATE_XID2INITW Awaiting XID2(0) Initiation
|
||||
ATTN from other side will start
|
||||
XID negotiations.
|
||||
Y-side protocol only.
|
||||
|
||||
MPCG_STATE_XID2INITX XID2(0) negotiations are in progress.
|
||||
At least 1, but not all, XID2(0)'s
|
||||
have been received from partner.
|
||||
|
||||
MPCG_STATE_XID7INITW XID2(0) complete
|
||||
No XID2(7)'s have yet been received.
|
||||
XID2(7) negotiations pending.
|
||||
|
||||
MPCG_STATE_XID7INITX XID2(7) negotiations in progress.
|
||||
At least 1, but not all, XID2(7)'s
|
||||
have been received from partner.
|
||||
|
||||
MPCG_STATE_XID7INITF XID2(7) negotiations complete.
|
||||
Transitioning to READY.
|
||||
|
||||
MPCG_STATE_READY Ready for Data Transfer.
|
||||
|
||||
|
||||
States from ctc_mpc_establish_connectivity call
|
||||
==============================================================
|
||||
MPCG_STATE_XID0IOWAIT Initiating XID2(0) negotiations.
|
||||
X-side protocol only.
|
||||
ATTN-BUSY from other side will convert
|
||||
this to Y-side protocol and the
|
||||
ctc_mpc_alloc_channel flow will begin.
|
||||
|
||||
MPCG_STATE_XID0IOWAIX XID2(0) negotiations are in progress.
|
||||
At least 1, but not all, XID2(0)'s
|
||||
have been received from partner.
|
||||
|
||||
MPCG_STATE_XID7INITI XID2(0) complete
|
||||
No XID2(7)'s have yet been received.
|
||||
XID2(7) negotiations pending.
|
||||
|
||||
MPCG_STATE_XID7INITZ XID2(7) negotiations in progress.
|
||||
At least 1, but not all, XID2(7)'s
|
||||
have been received from partner.
|
||||
|
||||
MPCG_STATE_XID7INITF XID2(7) negotiations complete.
|
||||
Transitioning to READY.
|
||||
|
||||
MPCG_STATE_READY Ready for Data Transfer.
|
||||
|
||||
*/
|
||||
|
||||
enum mpcg_events {
|
||||
MPCG_EVENT_INOP,
|
||||
MPCG_EVENT_DISCONC,
|
||||
MPCG_EVENT_XID0DO,
|
||||
MPCG_EVENT_XID2,
|
||||
MPCG_EVENT_XID2DONE,
|
||||
MPCG_EVENT_XID7DONE,
|
||||
MPCG_EVENT_TIMER,
|
||||
MPCG_EVENT_DOIO,
|
||||
MPCG_NR_EVENTS,
|
||||
};
|
||||
|
||||
enum mpcg_states {
|
||||
MPCG_STATE_RESET,
|
||||
MPCG_STATE_INOP,
|
||||
MPCG_STATE_XID2INITW,
|
||||
MPCG_STATE_XID2INITX,
|
||||
MPCG_STATE_XID7INITW,
|
||||
MPCG_STATE_XID7INITX,
|
||||
MPCG_STATE_XID0IOWAIT,
|
||||
MPCG_STATE_XID0IOWAIX,
|
||||
MPCG_STATE_XID7INITI,
|
||||
MPCG_STATE_XID7INITZ,
|
||||
MPCG_STATE_XID7INITF,
|
||||
MPCG_STATE_FLOWC,
|
||||
MPCG_STATE_READY,
|
||||
MPCG_NR_STATES,
|
||||
};
|
||||
|
||||
#endif
|
||||
/* --- This is the END my friend --- */
|
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|
@ -0,0 +1,287 @@
|
|||
/*
|
||||
* drivers/s390/net/ctcm_main.h
|
||||
*
|
||||
* Copyright IBM Corp. 2001, 2007
|
||||
* Authors: Fritz Elfert (felfert@millenux.com)
|
||||
* Peter Tiedemann (ptiedem@de.ibm.com)
|
||||
*/
|
||||
|
||||
#ifndef _CTCM_MAIN_H_
|
||||
#define _CTCM_MAIN_H_
|
||||
|
||||
#include <asm/ccwdev.h>
|
||||
#include <asm/ccwgroup.h>
|
||||
|
||||
#include <linux/skbuff.h>
|
||||
#include <linux/netdevice.h>
|
||||
|
||||
#include "fsm.h"
|
||||
#include "cu3088.h"
|
||||
#include "ctcm_dbug.h"
|
||||
#include "ctcm_mpc.h"
|
||||
|
||||
#define CTC_DRIVER_NAME "ctcm"
|
||||
#define CTC_DEVICE_NAME "ctc"
|
||||
#define CTC_DEVICE_GENE "ctc%d"
|
||||
#define MPC_DEVICE_NAME "mpc"
|
||||
#define MPC_DEVICE_GENE "mpc%d"
|
||||
|
||||
#define CHANNEL_FLAGS_READ 0
|
||||
#define CHANNEL_FLAGS_WRITE 1
|
||||
#define CHANNEL_FLAGS_INUSE 2
|
||||
#define CHANNEL_FLAGS_BUFSIZE_CHANGED 4
|
||||
#define CHANNEL_FLAGS_FAILED 8
|
||||
#define CHANNEL_FLAGS_WAITIRQ 16
|
||||
#define CHANNEL_FLAGS_RWMASK 1
|
||||
#define CHANNEL_DIRECTION(f) (f & CHANNEL_FLAGS_RWMASK)
|
||||
|
||||
#define LOG_FLAG_ILLEGALPKT 1
|
||||
#define LOG_FLAG_ILLEGALSIZE 2
|
||||
#define LOG_FLAG_OVERRUN 4
|
||||
#define LOG_FLAG_NOMEM 8
|
||||
|
||||
#define ctcm_pr_debug(fmt, arg...) printk(KERN_DEBUG fmt, ##arg)
|
||||
#define ctcm_pr_info(fmt, arg...) printk(KERN_INFO fmt, ##arg)
|
||||
#define ctcm_pr_notice(fmt, arg...) printk(KERN_NOTICE fmt, ##arg)
|
||||
#define ctcm_pr_warn(fmt, arg...) printk(KERN_WARNING fmt, ##arg)
|
||||
#define ctcm_pr_emerg(fmt, arg...) printk(KERN_EMERG fmt, ##arg)
|
||||
#define ctcm_pr_err(fmt, arg...) printk(KERN_ERR fmt, ##arg)
|
||||
#define ctcm_pr_crit(fmt, arg...) printk(KERN_CRIT fmt, ##arg)
|
||||
|
||||
/*
|
||||
* CCW commands, used in this driver.
|
||||
*/
|
||||
#define CCW_CMD_WRITE 0x01
|
||||
#define CCW_CMD_READ 0x02
|
||||
#define CCW_CMD_NOOP 0x03
|
||||
#define CCW_CMD_TIC 0x08
|
||||
#define CCW_CMD_SENSE_CMD 0x14
|
||||
#define CCW_CMD_WRITE_CTL 0x17
|
||||
#define CCW_CMD_SET_EXTENDED 0xc3
|
||||
#define CCW_CMD_PREPARE 0xe3
|
||||
|
||||
#define CTCM_PROTO_S390 0
|
||||
#define CTCM_PROTO_LINUX 1
|
||||
#define CTCM_PROTO_LINUX_TTY 2
|
||||
#define CTCM_PROTO_OS390 3
|
||||
#define CTCM_PROTO_MPC 4
|
||||
#define CTCM_PROTO_MAX 4
|
||||
|
||||
#define CTCM_BUFSIZE_LIMIT 65535
|
||||
#define CTCM_BUFSIZE_DEFAULT 32768
|
||||
#define MPC_BUFSIZE_DEFAULT CTCM_BUFSIZE_LIMIT
|
||||
|
||||
#define CTCM_TIME_1_SEC 1000
|
||||
#define CTCM_TIME_5_SEC 5000
|
||||
#define CTCM_TIME_10_SEC 10000
|
||||
|
||||
#define CTCM_INITIAL_BLOCKLEN 2
|
||||
|
||||
#define READ 0
|
||||
#define WRITE 1
|
||||
|
||||
#define CTCM_ID_SIZE BUS_ID_SIZE+3
|
||||
|
||||
struct ctcm_profile {
|
||||
unsigned long maxmulti;
|
||||
unsigned long maxcqueue;
|
||||
unsigned long doios_single;
|
||||
unsigned long doios_multi;
|
||||
unsigned long txlen;
|
||||
unsigned long tx_time;
|
||||
struct timespec send_stamp;
|
||||
};
|
||||
|
||||
/*
|
||||
* Definition of one channel
|
||||
*/
|
||||
struct channel {
|
||||
struct channel *next;
|
||||
char id[CTCM_ID_SIZE];
|
||||
struct ccw_device *cdev;
|
||||
/*
|
||||
* Type of this channel.
|
||||
* CTC/A or Escon for valid channels.
|
||||
*/
|
||||
enum channel_types type;
|
||||
/*
|
||||
* Misc. flags. See CHANNEL_FLAGS_... below
|
||||
*/
|
||||
__u32 flags;
|
||||
__u16 protocol; /* protocol of this channel (4 = MPC) */
|
||||
/*
|
||||
* I/O and irq related stuff
|
||||
*/
|
||||
struct ccw1 *ccw;
|
||||
struct irb *irb;
|
||||
/*
|
||||
* RX/TX buffer size
|
||||
*/
|
||||
int max_bufsize;
|
||||
struct sk_buff *trans_skb; /* transmit/receive buffer */
|
||||
struct sk_buff_head io_queue; /* universal I/O queue */
|
||||
struct tasklet_struct ch_tasklet; /* MPC ONLY */
|
||||
/*
|
||||
* TX queue for collecting skb's during busy.
|
||||
*/
|
||||
struct sk_buff_head collect_queue;
|
||||
/*
|
||||
* Amount of data in collect_queue.
|
||||
*/
|
||||
int collect_len;
|
||||
/*
|
||||
* spinlock for collect_queue and collect_len
|
||||
*/
|
||||
spinlock_t collect_lock;
|
||||
/*
|
||||
* Timer for detecting unresposive
|
||||
* I/O operations.
|
||||
*/
|
||||
fsm_timer timer;
|
||||
/* MPC ONLY section begin */
|
||||
__u32 th_seq_num; /* SNA TH seq number */
|
||||
__u8 th_seg;
|
||||
__u32 pdu_seq;
|
||||
struct sk_buff *xid_skb;
|
||||
char *xid_skb_data;
|
||||
struct th_header *xid_th;
|
||||
struct xid2 *xid;
|
||||
char *xid_id;
|
||||
struct th_header *rcvd_xid_th;
|
||||
struct xid2 *rcvd_xid;
|
||||
char *rcvd_xid_id;
|
||||
__u8 in_mpcgroup;
|
||||
fsm_timer sweep_timer;
|
||||
struct sk_buff_head sweep_queue;
|
||||
struct th_header *discontact_th;
|
||||
struct tasklet_struct ch_disc_tasklet;
|
||||
/* MPC ONLY section end */
|
||||
|
||||
int retry; /* retry counter for misc. operations */
|
||||
fsm_instance *fsm; /* finite state machine of this channel */
|
||||
struct net_device *netdev; /* corresponding net_device */
|
||||
struct ctcm_profile prof;
|
||||
unsigned char *trans_skb_data;
|
||||
__u16 logflags;
|
||||
};
|
||||
|
||||
struct ctcm_priv {
|
||||
struct net_device_stats stats;
|
||||
unsigned long tbusy;
|
||||
|
||||
/* The MPC group struct of this interface */
|
||||
struct mpc_group *mpcg; /* MPC only */
|
||||
struct xid2 *xid; /* MPC only */
|
||||
|
||||
/* The finite state machine of this interface */
|
||||
fsm_instance *fsm;
|
||||
|
||||
/* The protocol of this device */
|
||||
__u16 protocol;
|
||||
|
||||
/* Timer for restarting after I/O Errors */
|
||||
fsm_timer restart_timer;
|
||||
|
||||
int buffer_size; /* ctc only */
|
||||
|
||||
struct channel *channel[2];
|
||||
};
|
||||
|
||||
int ctcm_open(struct net_device *dev);
|
||||
int ctcm_close(struct net_device *dev);
|
||||
|
||||
/*
|
||||
* prototypes for non-static sysfs functions
|
||||
*/
|
||||
int ctcm_add_attributes(struct device *dev);
|
||||
void ctcm_remove_attributes(struct device *dev);
|
||||
int ctcm_add_files(struct device *dev);
|
||||
void ctcm_remove_files(struct device *dev);
|
||||
|
||||
/*
|
||||
* Compatibility macros for busy handling
|
||||
* of network devices.
|
||||
*/
|
||||
static inline void ctcm_clear_busy_do(struct net_device *dev)
|
||||
{
|
||||
clear_bit(0, &(((struct ctcm_priv *)dev->priv)->tbusy));
|
||||
netif_wake_queue(dev);
|
||||
}
|
||||
|
||||
static inline void ctcm_clear_busy(struct net_device *dev)
|
||||
{
|
||||
struct mpc_group *grp;
|
||||
grp = ((struct ctcm_priv *)dev->priv)->mpcg;
|
||||
|
||||
if (!(grp && grp->in_sweep))
|
||||
ctcm_clear_busy_do(dev);
|
||||
}
|
||||
|
||||
|
||||
static inline int ctcm_test_and_set_busy(struct net_device *dev)
|
||||
{
|
||||
netif_stop_queue(dev);
|
||||
return test_and_set_bit(0, &(((struct ctcm_priv *)dev->priv)->tbusy));
|
||||
}
|
||||
|
||||
extern int loglevel;
|
||||
extern struct channel *channels;
|
||||
|
||||
void ctcm_unpack_skb(struct channel *ch, struct sk_buff *pskb);
|
||||
|
||||
/*
|
||||
* Functions related to setup and device detection.
|
||||
*/
|
||||
|
||||
static inline int ctcm_less_than(char *id1, char *id2)
|
||||
{
|
||||
unsigned long dev1, dev2;
|
||||
|
||||
id1 = id1 + 5;
|
||||
id2 = id2 + 5;
|
||||
|
||||
dev1 = simple_strtoul(id1, &id1, 16);
|
||||
dev2 = simple_strtoul(id2, &id2, 16);
|
||||
|
||||
return (dev1 < dev2);
|
||||
}
|
||||
|
||||
int ctcm_ch_alloc_buffer(struct channel *ch);
|
||||
|
||||
static inline int ctcm_checkalloc_buffer(struct channel *ch)
|
||||
{
|
||||
if (ch->trans_skb == NULL)
|
||||
return ctcm_ch_alloc_buffer(ch);
|
||||
if (ch->flags & CHANNEL_FLAGS_BUFSIZE_CHANGED) {
|
||||
dev_kfree_skb(ch->trans_skb);
|
||||
return ctcm_ch_alloc_buffer(ch);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct mpc_group *ctcmpc_init_mpc_group(struct ctcm_priv *priv);
|
||||
|
||||
/* test if protocol attribute (of struct ctcm_priv or struct channel)
|
||||
* has MPC protocol setting. Type is not checked
|
||||
*/
|
||||
#define IS_MPC(p) ((p)->protocol == CTCM_PROTO_MPC)
|
||||
|
||||
/* test if struct ctcm_priv of struct net_device has MPC protocol setting */
|
||||
#define IS_MPCDEV(d) IS_MPC((struct ctcm_priv *)d->priv)
|
||||
|
||||
static inline gfp_t gfp_type(void)
|
||||
{
|
||||
return in_interrupt() ? GFP_ATOMIC : GFP_KERNEL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Definition of our link level header.
|
||||
*/
|
||||
struct ll_header {
|
||||
__u16 length;
|
||||
__u16 type;
|
||||
__u16 unused;
|
||||
};
|
||||
#define LL_HEADER_LENGTH (sizeof(struct ll_header))
|
||||
|
||||
#endif
|
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
@ -0,0 +1,239 @@
|
|||
/*
|
||||
* drivers/s390/net/ctcm_mpc.h
|
||||
*
|
||||
* Copyright IBM Corp. 2007
|
||||
* Authors: Peter Tiedemann (ptiedem@de.ibm.com)
|
||||
*
|
||||
* MPC additions:
|
||||
* Belinda Thompson (belindat@us.ibm.com)
|
||||
* Andy Richter (richtera@us.ibm.com)
|
||||
*/
|
||||
|
||||
#ifndef _CTC_MPC_H_
|
||||
#define _CTC_MPC_H_
|
||||
|
||||
#include <linux/skbuff.h>
|
||||
#include "fsm.h"
|
||||
|
||||
/*
|
||||
* MPC external interface
|
||||
* Note that ctc_mpc_xyz are called with a lock on ................
|
||||
*/
|
||||
|
||||
/* port_number is the mpc device 0, 1, 2 etc mpc2 is port_number 2 */
|
||||
|
||||
/* passive open Just wait for XID2 exchange */
|
||||
extern int ctc_mpc_alloc_channel(int port,
|
||||
void (*callback)(int port_num, int max_write_size));
|
||||
/* active open Alloc then send XID2 */
|
||||
extern void ctc_mpc_establish_connectivity(int port,
|
||||
void (*callback)(int port_num, int rc, int max_write_size));
|
||||
|
||||
extern void ctc_mpc_dealloc_ch(int port);
|
||||
extern void ctc_mpc_flow_control(int port, int flowc);
|
||||
|
||||
/*
|
||||
* other MPC Group prototypes and structures
|
||||
*/
|
||||
|
||||
#define ETH_P_SNA_DIX 0x80D5
|
||||
|
||||
/*
|
||||
* Declaration of an XID2
|
||||
*
|
||||
*/
|
||||
#define ALLZEROS 0x0000000000000000
|
||||
|
||||
#define XID_FM2 0x20
|
||||
#define XID2_0 0x00
|
||||
#define XID2_7 0x07
|
||||
#define XID2_WRITE_SIDE 0x04
|
||||
#define XID2_READ_SIDE 0x05
|
||||
|
||||
struct xid2 {
|
||||
__u8 xid2_type_id;
|
||||
__u8 xid2_len;
|
||||
__u32 xid2_adj_id;
|
||||
__u8 xid2_rlen;
|
||||
__u8 xid2_resv1;
|
||||
__u8 xid2_flag1;
|
||||
__u8 xid2_fmtt;
|
||||
__u8 xid2_flag4;
|
||||
__u16 xid2_resv2;
|
||||
__u8 xid2_tgnum;
|
||||
__u32 xid2_sender_id;
|
||||
__u8 xid2_flag2;
|
||||
__u8 xid2_option;
|
||||
char xid2_resv3[8];
|
||||
__u16 xid2_resv4;
|
||||
__u8 xid2_dlc_type;
|
||||
__u16 xid2_resv5;
|
||||
__u8 xid2_mpc_flag;
|
||||
__u8 xid2_resv6;
|
||||
__u16 xid2_buf_len;
|
||||
char xid2_buffer[255 - (13 * sizeof(__u8) +
|
||||
2 * sizeof(__u32) +
|
||||
4 * sizeof(__u16) +
|
||||
8 * sizeof(char))];
|
||||
} __attribute__ ((packed));
|
||||
|
||||
#define XID2_LENGTH (sizeof(struct xid2))
|
||||
|
||||
struct th_header {
|
||||
__u8 th_seg;
|
||||
__u8 th_ch_flag;
|
||||
#define TH_HAS_PDU 0xf0
|
||||
#define TH_IS_XID 0x01
|
||||
#define TH_SWEEP_REQ 0xfe
|
||||
#define TH_SWEEP_RESP 0xff
|
||||
__u8 th_blk_flag;
|
||||
#define TH_DATA_IS_XID 0x80
|
||||
#define TH_RETRY 0x40
|
||||
#define TH_DISCONTACT 0xc0
|
||||
#define TH_SEG_BLK 0x20
|
||||
#define TH_LAST_SEG 0x10
|
||||
#define TH_PDU_PART 0x08
|
||||
__u8 th_is_xid; /* is 0x01 if this is XID */
|
||||
__u32 th_seq_num;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
struct th_addon {
|
||||
__u32 th_last_seq;
|
||||
__u32 th_resvd;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
struct th_sweep {
|
||||
struct th_header th;
|
||||
struct th_addon sw;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
#define TH_HEADER_LENGTH (sizeof(struct th_header))
|
||||
#define TH_SWEEP_LENGTH (sizeof(struct th_sweep))
|
||||
|
||||
#define PDU_LAST 0x80
|
||||
#define PDU_CNTL 0x40
|
||||
#define PDU_FIRST 0x20
|
||||
|
||||
struct pdu {
|
||||
__u32 pdu_offset;
|
||||
__u8 pdu_flag;
|
||||
__u8 pdu_proto; /* 0x01 is APPN SNA */
|
||||
__u16 pdu_seq;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
#define PDU_HEADER_LENGTH (sizeof(struct pdu))
|
||||
|
||||
struct qllc {
|
||||
__u8 qllc_address;
|
||||
#define QLLC_REQ 0xFF
|
||||
#define QLLC_RESP 0x00
|
||||
__u8 qllc_commands;
|
||||
#define QLLC_DISCONNECT 0x53
|
||||
#define QLLC_UNSEQACK 0x73
|
||||
#define QLLC_SETMODE 0x93
|
||||
#define QLLC_EXCHID 0xBF
|
||||
} __attribute__ ((packed));
|
||||
|
||||
|
||||
/*
|
||||
* Definition of one MPC group
|
||||
*/
|
||||
|
||||
#define MAX_MPCGCHAN 10
|
||||
#define MPC_XID_TIMEOUT_VALUE 10000
|
||||
#define MPC_CHANNEL_ADD 0
|
||||
#define MPC_CHANNEL_REMOVE 1
|
||||
#define MPC_CHANNEL_ATTN 2
|
||||
#define XSIDE 1
|
||||
#define YSIDE 0
|
||||
|
||||
struct mpcg_info {
|
||||
struct sk_buff *skb;
|
||||
struct channel *ch;
|
||||
struct xid2 *xid;
|
||||
struct th_sweep *sweep;
|
||||
struct th_header *th;
|
||||
};
|
||||
|
||||
struct mpc_group {
|
||||
struct tasklet_struct mpc_tasklet;
|
||||
struct tasklet_struct mpc_tasklet2;
|
||||
int changed_side;
|
||||
int saved_state;
|
||||
int channels_terminating;
|
||||
int out_of_sequence;
|
||||
int flow_off_called;
|
||||
int port_num;
|
||||
int port_persist;
|
||||
int alloc_called;
|
||||
__u32 xid2_adj_id;
|
||||
__u8 xid2_tgnum;
|
||||
__u32 xid2_sender_id;
|
||||
int num_channel_paths;
|
||||
int active_channels[2];
|
||||
__u16 group_max_buflen;
|
||||
int outstanding_xid2;
|
||||
int outstanding_xid7;
|
||||
int outstanding_xid7_p2;
|
||||
int sweep_req_pend_num;
|
||||
int sweep_rsp_pend_num;
|
||||
struct sk_buff *xid_skb;
|
||||
char *xid_skb_data;
|
||||
struct th_header *xid_th;
|
||||
struct xid2 *xid;
|
||||
char *xid_id;
|
||||
struct th_header *rcvd_xid_th;
|
||||
struct sk_buff *rcvd_xid_skb;
|
||||
char *rcvd_xid_data;
|
||||
__u8 in_sweep;
|
||||
__u8 roll;
|
||||
struct xid2 *saved_xid2;
|
||||
void (*allochanfunc)(int, int);
|
||||
int allocchan_callback_retries;
|
||||
void (*estconnfunc)(int, int, int);
|
||||
int estconn_callback_retries;
|
||||
int estconn_called;
|
||||
int xidnogood;
|
||||
int send_qllc_disc;
|
||||
fsm_timer timer;
|
||||
fsm_instance *fsm; /* group xid fsm */
|
||||
};
|
||||
|
||||
#ifdef DEBUGDATA
|
||||
void ctcmpc_dumpit(char *buf, int len);
|
||||
#else
|
||||
static inline void ctcmpc_dumpit(char *buf, int len)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef DEBUGDATA
|
||||
/*
|
||||
* Dump header and first 16 bytes of an sk_buff for debugging purposes.
|
||||
*
|
||||
* skb The struct sk_buff to dump.
|
||||
* offset Offset relative to skb-data, where to start the dump.
|
||||
*/
|
||||
void ctcmpc_dump_skb(struct sk_buff *skb, int offset);
|
||||
#else
|
||||
static inline void ctcmpc_dump_skb(struct sk_buff *skb, int offset)
|
||||
{}
|
||||
#endif
|
||||
|
||||
static inline void ctcmpc_dump32(char *buf, int len)
|
||||
{
|
||||
if (len < 32)
|
||||
ctcmpc_dumpit(buf, len);
|
||||
else
|
||||
ctcmpc_dumpit(buf, 32);
|
||||
}
|
||||
|
||||
int ctcmpc_open(struct net_device *);
|
||||
void ctcm_ccw_check_rc(struct channel *, int, char *);
|
||||
void mpc_group_ready(unsigned long adev);
|
||||
int mpc_channel_action(struct channel *ch, int direction, int action);
|
||||
void mpc_action_send_discontact(unsigned long thischan);
|
||||
void mpc_action_discontact(fsm_instance *fi, int event, void *arg);
|
||||
void ctcmpc_bh(unsigned long thischan);
|
||||
#endif
|
||||
/* --- This is the END my friend --- */
|
|
@ -0,0 +1,210 @@
|
|||
/*
|
||||
* drivers/s390/net/ctcm_sysfs.c
|
||||
*
|
||||
* Copyright IBM Corp. 2007, 2007
|
||||
* Authors: Peter Tiedemann (ptiedem@de.ibm.com)
|
||||
*
|
||||
*/
|
||||
|
||||
#undef DEBUG
|
||||
#undef DEBUGDATA
|
||||
#undef DEBUGCCW
|
||||
|
||||
#include <linux/sysfs.h>
|
||||
#include "ctcm_main.h"
|
||||
|
||||
/*
|
||||
* sysfs attributes
|
||||
*/
|
||||
|
||||
static ssize_t ctcm_buffer_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct ctcm_priv *priv = dev_get_drvdata(dev);
|
||||
|
||||
if (!priv)
|
||||
return -ENODEV;
|
||||
return sprintf(buf, "%d\n", priv->buffer_size);
|
||||
}
|
||||
|
||||
static ssize_t ctcm_buffer_write(struct device *dev,
|
||||
struct device_attribute *attr, const char *buf, size_t count)
|
||||
{
|
||||
struct net_device *ndev;
|
||||
int bs1;
|
||||
struct ctcm_priv *priv = dev_get_drvdata(dev);
|
||||
|
||||
if (!(priv && priv->channel[READ] &&
|
||||
(ndev = priv->channel[READ]->netdev))) {
|
||||
CTCM_DBF_TEXT(SETUP, CTC_DBF_ERROR, "bfnondev");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
sscanf(buf, "%u", &bs1);
|
||||
if (bs1 > CTCM_BUFSIZE_LIMIT)
|
||||
goto einval;
|
||||
if (bs1 < (576 + LL_HEADER_LENGTH + 2))
|
||||
goto einval;
|
||||
priv->buffer_size = bs1; /* just to overwrite the default */
|
||||
|
||||
if ((ndev->flags & IFF_RUNNING) &&
|
||||
(bs1 < (ndev->mtu + LL_HEADER_LENGTH + 2)))
|
||||
goto einval;
|
||||
|
||||
priv->channel[READ]->max_bufsize = bs1;
|
||||
priv->channel[WRITE]->max_bufsize = bs1;
|
||||
if (!(ndev->flags & IFF_RUNNING))
|
||||
ndev->mtu = bs1 - LL_HEADER_LENGTH - 2;
|
||||
priv->channel[READ]->flags |= CHANNEL_FLAGS_BUFSIZE_CHANGED;
|
||||
priv->channel[WRITE]->flags |= CHANNEL_FLAGS_BUFSIZE_CHANGED;
|
||||
|
||||
CTCM_DBF_DEV(SETUP, ndev, buf);
|
||||
return count;
|
||||
|
||||
einval:
|
||||
CTCM_DBF_DEV(SETUP, ndev, "buff_err");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static void ctcm_print_statistics(struct ctcm_priv *priv)
|
||||
{
|
||||
char *sbuf;
|
||||
char *p;
|
||||
|
||||
if (!priv)
|
||||
return;
|
||||
sbuf = kmalloc(2048, GFP_KERNEL);
|
||||
if (sbuf == NULL)
|
||||
return;
|
||||
p = sbuf;
|
||||
|
||||
p += sprintf(p, " Device FSM state: %s\n",
|
||||
fsm_getstate_str(priv->fsm));
|
||||
p += sprintf(p, " RX channel FSM state: %s\n",
|
||||
fsm_getstate_str(priv->channel[READ]->fsm));
|
||||
p += sprintf(p, " TX channel FSM state: %s\n",
|
||||
fsm_getstate_str(priv->channel[WRITE]->fsm));
|
||||
p += sprintf(p, " Max. TX buffer used: %ld\n",
|
||||
priv->channel[WRITE]->prof.maxmulti);
|
||||
p += sprintf(p, " Max. chained SKBs: %ld\n",
|
||||
priv->channel[WRITE]->prof.maxcqueue);
|
||||
p += sprintf(p, " TX single write ops: %ld\n",
|
||||
priv->channel[WRITE]->prof.doios_single);
|
||||
p += sprintf(p, " TX multi write ops: %ld\n",
|
||||
priv->channel[WRITE]->prof.doios_multi);
|
||||
p += sprintf(p, " Netto bytes written: %ld\n",
|
||||
priv->channel[WRITE]->prof.txlen);
|
||||
p += sprintf(p, " Max. TX IO-time: %ld\n",
|
||||
priv->channel[WRITE]->prof.tx_time);
|
||||
|
||||
printk(KERN_INFO "Statistics for %s:\n%s",
|
||||
priv->channel[WRITE]->netdev->name, sbuf);
|
||||
kfree(sbuf);
|
||||
return;
|
||||
}
|
||||
|
||||
static ssize_t stats_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct ctcm_priv *priv = dev_get_drvdata(dev);
|
||||
if (!priv)
|
||||
return -ENODEV;
|
||||
ctcm_print_statistics(priv);
|
||||
return sprintf(buf, "0\n");
|
||||
}
|
||||
|
||||
static ssize_t stats_write(struct device *dev, struct device_attribute *attr,
|
||||
const char *buf, size_t count)
|
||||
{
|
||||
struct ctcm_priv *priv = dev_get_drvdata(dev);
|
||||
if (!priv)
|
||||
return -ENODEV;
|
||||
/* Reset statistics */
|
||||
memset(&priv->channel[WRITE]->prof, 0,
|
||||
sizeof(priv->channel[WRITE]->prof));
|
||||
return count;
|
||||
}
|
||||
|
||||
static ssize_t ctcm_proto_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct ctcm_priv *priv = dev_get_drvdata(dev);
|
||||
if (!priv)
|
||||
return -ENODEV;
|
||||
|
||||
return sprintf(buf, "%d\n", priv->protocol);
|
||||
}
|
||||
|
||||
static ssize_t ctcm_proto_store(struct device *dev,
|
||||
struct device_attribute *attr, const char *buf, size_t count)
|
||||
{
|
||||
int value;
|
||||
struct ctcm_priv *priv = dev_get_drvdata(dev);
|
||||
|
||||
if (!priv)
|
||||
return -ENODEV;
|
||||
sscanf(buf, "%u", &value);
|
||||
if (!((value == CTCM_PROTO_S390) ||
|
||||
(value == CTCM_PROTO_LINUX) ||
|
||||
(value == CTCM_PROTO_MPC) ||
|
||||
(value == CTCM_PROTO_OS390)))
|
||||
return -EINVAL;
|
||||
priv->protocol = value;
|
||||
CTCM_DBF_DEV(SETUP, dev, buf);
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
static ssize_t ctcm_type_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct ccwgroup_device *cgdev;
|
||||
|
||||
cgdev = to_ccwgroupdev(dev);
|
||||
if (!cgdev)
|
||||
return -ENODEV;
|
||||
|
||||
return sprintf(buf, "%s\n",
|
||||
cu3088_type[cgdev->cdev[0]->id.driver_info]);
|
||||
}
|
||||
|
||||
static DEVICE_ATTR(buffer, 0644, ctcm_buffer_show, ctcm_buffer_write);
|
||||
static DEVICE_ATTR(protocol, 0644, ctcm_proto_show, ctcm_proto_store);
|
||||
static DEVICE_ATTR(type, 0444, ctcm_type_show, NULL);
|
||||
static DEVICE_ATTR(stats, 0644, stats_show, stats_write);
|
||||
|
||||
static struct attribute *ctcm_attr[] = {
|
||||
&dev_attr_protocol.attr,
|
||||
&dev_attr_type.attr,
|
||||
&dev_attr_buffer.attr,
|
||||
NULL,
|
||||
};
|
||||
|
||||
static struct attribute_group ctcm_attr_group = {
|
||||
.attrs = ctcm_attr,
|
||||
};
|
||||
|
||||
int ctcm_add_attributes(struct device *dev)
|
||||
{
|
||||
int rc;
|
||||
|
||||
rc = device_create_file(dev, &dev_attr_stats);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
void ctcm_remove_attributes(struct device *dev)
|
||||
{
|
||||
device_remove_file(dev, &dev_attr_stats);
|
||||
}
|
||||
|
||||
int ctcm_add_files(struct device *dev)
|
||||
{
|
||||
return sysfs_create_group(&dev->kobj, &ctcm_attr_group);
|
||||
}
|
||||
|
||||
void ctcm_remove_files(struct device *dev)
|
||||
{
|
||||
sysfs_remove_group(&dev->kobj, &ctcm_attr_group);
|
||||
}
|
||||
|
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
@ -1,270 +0,0 @@
|
|||
/*
|
||||
* CTC / ESCON network driver
|
||||
*
|
||||
* Copyright (C) 2001 IBM Deutschland Entwicklung GmbH, IBM Corporation
|
||||
* Author(s): Fritz Elfert (elfert@de.ibm.com, felfert@millenux.com)
|
||||
Peter Tiedemann (ptiedem@de.ibm.com)
|
||||
*
|
||||
*
|
||||
* Documentation used:
|
||||
* - Principles of Operation (IBM doc#: SA22-7201-06)
|
||||
* - Common IO/-Device Commands and Self Description (IBM doc#: SA22-7204-02)
|
||||
* - Common IO/-Device Commands and Self Description (IBM doc#: SN22-5535)
|
||||
* - ESCON Channel-to-Channel Adapter (IBM doc#: SA22-7203-00)
|
||||
* - ESCON I/O Interface (IBM doc#: SA22-7202-029
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _CTCMAIN_H_
|
||||
#define _CTCMAIN_H_
|
||||
|
||||
#include <asm/ccwdev.h>
|
||||
#include <asm/ccwgroup.h>
|
||||
|
||||
#include <linux/skbuff.h>
|
||||
#include <linux/netdevice.h>
|
||||
|
||||
#include "fsm.h"
|
||||
#include "cu3088.h"
|
||||
|
||||
|
||||
/**
|
||||
* CCW commands, used in this driver.
|
||||
*/
|
||||
#define CCW_CMD_WRITE 0x01
|
||||
#define CCW_CMD_READ 0x02
|
||||
#define CCW_CMD_SET_EXTENDED 0xc3
|
||||
#define CCW_CMD_PREPARE 0xe3
|
||||
|
||||
#define CTC_PROTO_S390 0
|
||||
#define CTC_PROTO_LINUX 1
|
||||
#define CTC_PROTO_OS390 3
|
||||
|
||||
#define CTC_BUFSIZE_LIMIT 65535
|
||||
#define CTC_BUFSIZE_DEFAULT 32768
|
||||
|
||||
#define CTC_TIMEOUT_5SEC 5000
|
||||
|
||||
#define CTC_INITIAL_BLOCKLEN 2
|
||||
|
||||
#define READ 0
|
||||
#define WRITE 1
|
||||
|
||||
#define CTC_ID_SIZE BUS_ID_SIZE+3
|
||||
|
||||
|
||||
struct ctc_profile {
|
||||
unsigned long maxmulti;
|
||||
unsigned long maxcqueue;
|
||||
unsigned long doios_single;
|
||||
unsigned long doios_multi;
|
||||
unsigned long txlen;
|
||||
unsigned long tx_time;
|
||||
struct timespec send_stamp;
|
||||
};
|
||||
|
||||
/**
|
||||
* Definition of one channel
|
||||
*/
|
||||
struct channel {
|
||||
|
||||
/**
|
||||
* Pointer to next channel in list.
|
||||
*/
|
||||
struct channel *next;
|
||||
char id[CTC_ID_SIZE];
|
||||
struct ccw_device *cdev;
|
||||
|
||||
/**
|
||||
* Type of this channel.
|
||||
* CTC/A or Escon for valid channels.
|
||||
*/
|
||||
enum channel_types type;
|
||||
|
||||
/**
|
||||
* Misc. flags. See CHANNEL_FLAGS_... below
|
||||
*/
|
||||
__u32 flags;
|
||||
|
||||
/**
|
||||
* The protocol of this channel
|
||||
*/
|
||||
__u16 protocol;
|
||||
|
||||
/**
|
||||
* I/O and irq related stuff
|
||||
*/
|
||||
struct ccw1 *ccw;
|
||||
struct irb *irb;
|
||||
|
||||
/**
|
||||
* RX/TX buffer size
|
||||
*/
|
||||
int max_bufsize;
|
||||
|
||||
/**
|
||||
* Transmit/Receive buffer.
|
||||
*/
|
||||
struct sk_buff *trans_skb;
|
||||
|
||||
/**
|
||||
* Universal I/O queue.
|
||||
*/
|
||||
struct sk_buff_head io_queue;
|
||||
|
||||
/**
|
||||
* TX queue for collecting skb's during busy.
|
||||
*/
|
||||
struct sk_buff_head collect_queue;
|
||||
|
||||
/**
|
||||
* Amount of data in collect_queue.
|
||||
*/
|
||||
int collect_len;
|
||||
|
||||
/**
|
||||
* spinlock for collect_queue and collect_len
|
||||
*/
|
||||
spinlock_t collect_lock;
|
||||
|
||||
/**
|
||||
* Timer for detecting unresposive
|
||||
* I/O operations.
|
||||
*/
|
||||
fsm_timer timer;
|
||||
|
||||
/**
|
||||
* Retry counter for misc. operations.
|
||||
*/
|
||||
int retry;
|
||||
|
||||
/**
|
||||
* The finite state machine of this channel
|
||||
*/
|
||||
fsm_instance *fsm;
|
||||
|
||||
/**
|
||||
* The corresponding net_device this channel
|
||||
* belongs to.
|
||||
*/
|
||||
struct net_device *netdev;
|
||||
|
||||
struct ctc_profile prof;
|
||||
|
||||
unsigned char *trans_skb_data;
|
||||
|
||||
__u16 logflags;
|
||||
};
|
||||
|
||||
#define CHANNEL_FLAGS_READ 0
|
||||
#define CHANNEL_FLAGS_WRITE 1
|
||||
#define CHANNEL_FLAGS_INUSE 2
|
||||
#define CHANNEL_FLAGS_BUFSIZE_CHANGED 4
|
||||
#define CHANNEL_FLAGS_FAILED 8
|
||||
#define CHANNEL_FLAGS_WAITIRQ 16
|
||||
#define CHANNEL_FLAGS_RWMASK 1
|
||||
#define CHANNEL_DIRECTION(f) (f & CHANNEL_FLAGS_RWMASK)
|
||||
|
||||
#define LOG_FLAG_ILLEGALPKT 1
|
||||
#define LOG_FLAG_ILLEGALSIZE 2
|
||||
#define LOG_FLAG_OVERRUN 4
|
||||
#define LOG_FLAG_NOMEM 8
|
||||
|
||||
#define CTC_LOGLEVEL_INFO 1
|
||||
#define CTC_LOGLEVEL_NOTICE 2
|
||||
#define CTC_LOGLEVEL_WARN 4
|
||||
#define CTC_LOGLEVEL_EMERG 8
|
||||
#define CTC_LOGLEVEL_ERR 16
|
||||
#define CTC_LOGLEVEL_DEBUG 32
|
||||
#define CTC_LOGLEVEL_CRIT 64
|
||||
|
||||
#define CTC_LOGLEVEL_DEFAULT \
|
||||
(CTC_LOGLEVEL_INFO | CTC_LOGLEVEL_NOTICE | CTC_LOGLEVEL_WARN | CTC_LOGLEVEL_CRIT)
|
||||
|
||||
#define CTC_LOGLEVEL_MAX ((CTC_LOGLEVEL_CRIT<<1)-1)
|
||||
|
||||
#define ctc_pr_debug(fmt, arg...) \
|
||||
do { if (loglevel & CTC_LOGLEVEL_DEBUG) printk(KERN_DEBUG fmt,##arg); } while (0)
|
||||
|
||||
#define ctc_pr_info(fmt, arg...) \
|
||||
do { if (loglevel & CTC_LOGLEVEL_INFO) printk(KERN_INFO fmt,##arg); } while (0)
|
||||
|
||||
#define ctc_pr_notice(fmt, arg...) \
|
||||
do { if (loglevel & CTC_LOGLEVEL_NOTICE) printk(KERN_NOTICE fmt,##arg); } while (0)
|
||||
|
||||
#define ctc_pr_warn(fmt, arg...) \
|
||||
do { if (loglevel & CTC_LOGLEVEL_WARN) printk(KERN_WARNING fmt,##arg); } while (0)
|
||||
|
||||
#define ctc_pr_emerg(fmt, arg...) \
|
||||
do { if (loglevel & CTC_LOGLEVEL_EMERG) printk(KERN_EMERG fmt,##arg); } while (0)
|
||||
|
||||
#define ctc_pr_err(fmt, arg...) \
|
||||
do { if (loglevel & CTC_LOGLEVEL_ERR) printk(KERN_ERR fmt,##arg); } while (0)
|
||||
|
||||
#define ctc_pr_crit(fmt, arg...) \
|
||||
do { if (loglevel & CTC_LOGLEVEL_CRIT) printk(KERN_CRIT fmt,##arg); } while (0)
|
||||
|
||||
struct ctc_priv {
|
||||
struct net_device_stats stats;
|
||||
unsigned long tbusy;
|
||||
/**
|
||||
* The finite state machine of this interface.
|
||||
*/
|
||||
fsm_instance *fsm;
|
||||
/**
|
||||
* The protocol of this device
|
||||
*/
|
||||
__u16 protocol;
|
||||
/**
|
||||
* Timer for restarting after I/O Errors
|
||||
*/
|
||||
fsm_timer restart_timer;
|
||||
|
||||
int buffer_size;
|
||||
|
||||
struct channel *channel[2];
|
||||
};
|
||||
|
||||
/**
|
||||
* Definition of our link level header.
|
||||
*/
|
||||
struct ll_header {
|
||||
__u16 length;
|
||||
__u16 type;
|
||||
__u16 unused;
|
||||
};
|
||||
#define LL_HEADER_LENGTH (sizeof(struct ll_header))
|
||||
|
||||
/**
|
||||
* Compatibility macros for busy handling
|
||||
* of network devices.
|
||||
*/
|
||||
static __inline__ void
|
||||
ctc_clear_busy(struct net_device * dev)
|
||||
{
|
||||
clear_bit(0, &(((struct ctc_priv *) dev->priv)->tbusy));
|
||||
netif_wake_queue(dev);
|
||||
}
|
||||
|
||||
static __inline__ int
|
||||
ctc_test_and_set_busy(struct net_device * dev)
|
||||
{
|
||||
netif_stop_queue(dev);
|
||||
return test_and_set_bit(0, &((struct ctc_priv *) dev->priv)->tbusy);
|
||||
}
|
||||
|
||||
#endif
|
|
@ -1,40 +1,38 @@
|
|||
#ifndef __QETH_H__
|
||||
#define __QETH_H__
|
||||
/*
|
||||
* drivers/s390/net/qeth_core.h
|
||||
*
|
||||
* Copyright IBM Corp. 2007
|
||||
* Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
|
||||
* Frank Pavlic <fpavlic@de.ibm.com>,
|
||||
* Thomas Spatzier <tspat@de.ibm.com>,
|
||||
* Frank Blaschka <frank.blaschka@de.ibm.com>
|
||||
*/
|
||||
|
||||
#ifndef __QETH_CORE_H__
|
||||
#define __QETH_CORE_H__
|
||||
|
||||
#include <linux/if.h>
|
||||
#include <linux/if_arp.h>
|
||||
|
||||
#include <linux/if_tr.h>
|
||||
#include <linux/trdevice.h>
|
||||
#include <linux/etherdevice.h>
|
||||
#include <linux/if_vlan.h>
|
||||
#include <linux/ctype.h>
|
||||
#include <linux/in6.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/seq_file.h>
|
||||
#include <linux/ethtool.h>
|
||||
|
||||
#include <net/ipv6.h>
|
||||
#include <linux/in6.h>
|
||||
#include <net/if_inet6.h>
|
||||
#include <net/addrconf.h>
|
||||
|
||||
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#include <asm/debug.h>
|
||||
#include <asm/qdio.h>
|
||||
#include <asm/ccwdev.h>
|
||||
#include <asm/ccwgroup.h>
|
||||
|
||||
#include "qeth_mpc.h"
|
||||
|
||||
#ifdef CONFIG_QETH_IPV6
|
||||
#define QETH_VERSION_IPV6 ":IPv6"
|
||||
#else
|
||||
#define QETH_VERSION_IPV6 ""
|
||||
#endif
|
||||
#ifdef CONFIG_QETH_VLAN
|
||||
#define QETH_VERSION_VLAN ":VLAN"
|
||||
#else
|
||||
#define QETH_VERSION_VLAN ""
|
||||
#endif
|
||||
#include "qeth_core_mpc.h"
|
||||
|
||||
/**
|
||||
* Debug Facility stuff
|
||||
|
@ -60,15 +58,14 @@
|
|||
#define QETH_DBF_CONTROL_NAME "qeth_control"
|
||||
#define QETH_DBF_CONTROL_LEN 256
|
||||
#define QETH_DBF_CONTROL_PAGES 8
|
||||
#define QETH_DBF_CONTROL_NR_AREAS 2
|
||||
#define QETH_DBF_CONTROL_NR_AREAS 1
|
||||
#define QETH_DBF_CONTROL_LEVEL 5
|
||||
|
||||
#define QETH_DBF_TRACE_NAME "qeth_trace"
|
||||
#define QETH_DBF_TRACE_LEN 8
|
||||
#define QETH_DBF_TRACE_PAGES 4
|
||||
#define QETH_DBF_TRACE_NR_AREAS 2
|
||||
#define QETH_DBF_TRACE_NR_AREAS 1
|
||||
#define QETH_DBF_TRACE_LEVEL 3
|
||||
extern debug_info_t *qeth_dbf_trace;
|
||||
|
||||
#define QETH_DBF_SENSE_NAME "qeth_sense"
|
||||
#define QETH_DBF_SENSE_LEN 64
|
||||
|
@ -79,7 +76,7 @@ extern debug_info_t *qeth_dbf_trace;
|
|||
#define QETH_DBF_QERR_NAME "qeth_qerr"
|
||||
#define QETH_DBF_QERR_LEN 8
|
||||
#define QETH_DBF_QERR_PAGES 2
|
||||
#define QETH_DBF_QERR_NR_AREAS 2
|
||||
#define QETH_DBF_QERR_NR_AREAS 1
|
||||
#define QETH_DBF_QERR_LEVEL 2
|
||||
|
||||
#define QETH_DBF_TEXT(name, level, text) \
|
||||
|
@ -92,60 +89,17 @@ extern debug_info_t *qeth_dbf_trace;
|
|||
debug_event(qeth_dbf_##name, level, (void *)(addr), len); \
|
||||
} while (0)
|
||||
|
||||
DECLARE_PER_CPU(char[256], qeth_dbf_txt_buf);
|
||||
|
||||
#define QETH_DBF_TEXT_(name,level,text...) \
|
||||
do { \
|
||||
char* dbf_txt_buf = get_cpu_var(qeth_dbf_txt_buf); \
|
||||
sprintf(dbf_txt_buf, text); \
|
||||
debug_text_event(qeth_dbf_##name,level,dbf_txt_buf); \
|
||||
put_cpu_var(qeth_dbf_txt_buf); \
|
||||
} while (0)
|
||||
|
||||
#define QETH_DBF_SPRINTF(name,level,text...) \
|
||||
do { \
|
||||
debug_sprintf_event(qeth_dbf_trace, level, ##text ); \
|
||||
debug_sprintf_event(qeth_dbf_trace, level, text ); \
|
||||
} while (0)
|
||||
/* Allow to sort out low debug levels early to avoid wasted sprints */
|
||||
static inline int qeth_dbf_passes(debug_info_t *dbf_grp, int level)
|
||||
{
|
||||
return (level <= dbf_grp->level);
|
||||
}
|
||||
|
||||
/**
|
||||
* some more debug stuff
|
||||
*/
|
||||
#define PRINTK_HEADER "qeth: "
|
||||
|
||||
#define HEXDUMP16(importance,header,ptr) \
|
||||
PRINT_##importance(header "%02x %02x %02x %02x %02x %02x %02x %02x " \
|
||||
"%02x %02x %02x %02x %02x %02x %02x %02x\n", \
|
||||
*(((char*)ptr)),*(((char*)ptr)+1),*(((char*)ptr)+2), \
|
||||
*(((char*)ptr)+3),*(((char*)ptr)+4),*(((char*)ptr)+5), \
|
||||
*(((char*)ptr)+6),*(((char*)ptr)+7),*(((char*)ptr)+8), \
|
||||
*(((char*)ptr)+9),*(((char*)ptr)+10),*(((char*)ptr)+11), \
|
||||
*(((char*)ptr)+12),*(((char*)ptr)+13), \
|
||||
*(((char*)ptr)+14),*(((char*)ptr)+15)); \
|
||||
PRINT_##importance(header "%02x %02x %02x %02x %02x %02x %02x %02x " \
|
||||
"%02x %02x %02x %02x %02x %02x %02x %02x\n", \
|
||||
*(((char*)ptr)+16),*(((char*)ptr)+17), \
|
||||
*(((char*)ptr)+18),*(((char*)ptr)+19), \
|
||||
*(((char*)ptr)+20),*(((char*)ptr)+21), \
|
||||
*(((char*)ptr)+22),*(((char*)ptr)+23), \
|
||||
*(((char*)ptr)+24),*(((char*)ptr)+25), \
|
||||
*(((char*)ptr)+26),*(((char*)ptr)+27), \
|
||||
*(((char*)ptr)+28),*(((char*)ptr)+29), \
|
||||
*(((char*)ptr)+30),*(((char*)ptr)+31));
|
||||
|
||||
static inline void
|
||||
qeth_hex_dump(unsigned char *buf, size_t len)
|
||||
{
|
||||
size_t i;
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
if (i && !(i % 16))
|
||||
printk("\n");
|
||||
printk("%02x ", *(buf + i));
|
||||
}
|
||||
printk("\n");
|
||||
}
|
||||
|
||||
#define SENSE_COMMAND_REJECT_BYTE 0
|
||||
#define SENSE_COMMAND_REJECT_FLAG 0x80
|
||||
#define SENSE_RESETTING_EVENT_BYTE 1
|
||||
|
@ -154,10 +108,6 @@ qeth_hex_dump(unsigned char *buf, size_t len)
|
|||
/*
|
||||
* Common IO related definitions
|
||||
*/
|
||||
extern struct device *qeth_root_dev;
|
||||
extern struct ccw_driver qeth_ccw_driver;
|
||||
extern struct ccwgroup_driver qeth_ccwgroup_driver;
|
||||
|
||||
#define CARD_RDEV(card) card->read.ccwdev
|
||||
#define CARD_WDEV(card) card->write.ccwdev
|
||||
#define CARD_DDEV(card) card->data.ccwdev
|
||||
|
@ -167,10 +117,6 @@ extern struct ccwgroup_driver qeth_ccwgroup_driver;
|
|||
#define CARD_DDEV_ID(card) card->data.ccwdev->dev.bus_id
|
||||
#define CHANNEL_ID(channel) channel->ccwdev->dev.bus_id
|
||||
|
||||
#define CARD_FROM_CDEV(cdev) (struct qeth_card *) \
|
||||
((struct ccwgroup_device *)cdev->dev.driver_data)\
|
||||
->dev.driver_data;
|
||||
|
||||
/**
|
||||
* card stuff
|
||||
*/
|
||||
|
@ -228,14 +174,14 @@ struct qeth_ipa_info {
|
|||
__u32 enabled_funcs;
|
||||
};
|
||||
|
||||
static inline int
|
||||
qeth_is_ipa_supported(struct qeth_ipa_info *ipa, enum qeth_ipa_funcs func)
|
||||
static inline int qeth_is_ipa_supported(struct qeth_ipa_info *ipa,
|
||||
enum qeth_ipa_funcs func)
|
||||
{
|
||||
return (ipa->supported_funcs & func);
|
||||
}
|
||||
|
||||
static inline int
|
||||
qeth_is_ipa_enabled(struct qeth_ipa_info *ipa, enum qeth_ipa_funcs func)
|
||||
static inline int qeth_is_ipa_enabled(struct qeth_ipa_info *ipa,
|
||||
enum qeth_ipa_funcs func)
|
||||
{
|
||||
return (ipa->supported_funcs & ipa->enabled_funcs & func);
|
||||
}
|
||||
|
@ -248,20 +194,16 @@ qeth_is_ipa_enabled(struct qeth_ipa_info *ipa, enum qeth_ipa_funcs func)
|
|||
qeth_is_ipa_supported(&c->options.ipa4, f)
|
||||
#define qeth_is_enabled(c, f) \
|
||||
qeth_is_ipa_enabled(&c->options.ipa4, f)
|
||||
#ifdef CONFIG_QETH_IPV6
|
||||
#define qeth_is_supported6(c, f) \
|
||||
qeth_is_ipa_supported(&c->options.ipa6, f)
|
||||
#define qeth_is_enabled6(c, f) \
|
||||
qeth_is_ipa_enabled(&c->options.ipa6, f)
|
||||
#else /* CONFIG_QETH_IPV6 */
|
||||
#define qeth_is_supported6(c,f) 0
|
||||
#define qeth_is_enabled6(c,f) 0
|
||||
#endif /* CONFIG_QETH_IPV6 */
|
||||
#define qeth_is_ipafunc_supported(c, prot, f) \
|
||||
(prot==QETH_PROT_IPV6)? qeth_is_supported6(c,f):qeth_is_supported(c,f)
|
||||
((prot == QETH_PROT_IPV6) ? \
|
||||
qeth_is_supported6(c, f) : qeth_is_supported(c, f))
|
||||
#define qeth_is_ipafunc_enabled(c, prot, f) \
|
||||
(prot==QETH_PROT_IPV6)? qeth_is_enabled6(c,f):qeth_is_enabled(c,f)
|
||||
|
||||
((prot == QETH_PROT_IPV6) ? \
|
||||
qeth_is_enabled6(c, f) : qeth_is_enabled(c, f))
|
||||
|
||||
#define QETH_IDX_FUNC_LEVEL_OSAE_ENA_IPAT 0x0101
|
||||
#define QETH_IDX_FUNC_LEVEL_OSAE_DIS_IPAT 0x0101
|
||||
|
@ -290,14 +232,10 @@ qeth_is_ipa_enabled(struct qeth_ipa_info *ipa, enum qeth_ipa_funcs func)
|
|||
/**
|
||||
* some more defs
|
||||
*/
|
||||
#define IF_NAME_LEN 16
|
||||
#define QETH_TX_TIMEOUT 100 * HZ
|
||||
#define QETH_RCD_TIMEOUT 60 * HZ
|
||||
#define QETH_HEADER_SIZE 32
|
||||
#define MAX_PORTNO 15
|
||||
#define QETH_FAKE_LL_LEN_ETH ETH_HLEN
|
||||
#define QETH_FAKE_LL_LEN_TR (sizeof(struct trh_hdr)-TR_MAXRIFLEN+sizeof(struct trllc))
|
||||
#define QETH_FAKE_LL_V6_ADDR_POS 24
|
||||
#define QETH_MAX_PORTNO 15
|
||||
|
||||
/*IPv6 address autoconfiguration stuff*/
|
||||
#define UNIQUE_ID_IF_CREATE_ADDR_FAILED 0xfffe
|
||||
|
@ -446,8 +384,7 @@ enum qeth_header_ids {
|
|||
#define QETH_HDR_EXT_CSUM_TRANSP_REQ 0x20
|
||||
#define QETH_HDR_EXT_UDP_TSO 0x40 /*bit off for TCP*/
|
||||
|
||||
static inline int
|
||||
qeth_is_last_sbale(struct qdio_buffer_element *sbale)
|
||||
static inline int qeth_is_last_sbale(struct qdio_buffer_element *sbale)
|
||||
{
|
||||
return (sbale->flags & SBAL_FLAGS_LAST_ENTRY);
|
||||
}
|
||||
|
@ -485,7 +422,6 @@ struct qeth_qdio_buffer_pool {
|
|||
|
||||
struct qeth_qdio_buffer {
|
||||
struct qdio_buffer *buffer;
|
||||
volatile enum qeth_qdio_buffer_states state;
|
||||
/* the buffer pool entry currently associated to this buffer */
|
||||
struct qeth_buffer_pool_entry *pool_entry;
|
||||
};
|
||||
|
@ -493,11 +429,7 @@ struct qeth_qdio_buffer {
|
|||
struct qeth_qdio_q {
|
||||
struct qdio_buffer qdio_bufs[QDIO_MAX_BUFFERS_PER_Q];
|
||||
struct qeth_qdio_buffer bufs[QDIO_MAX_BUFFERS_PER_Q];
|
||||
/*
|
||||
* buf_to_init means "buffer must be initialized by driver and must
|
||||
* be made available for hardware" -> state is set to EMPTY
|
||||
*/
|
||||
volatile int next_buf_to_init;
|
||||
int next_buf_to_init;
|
||||
} __attribute__ ((aligned(256)));
|
||||
|
||||
/* possible types of qeth large_send support */
|
||||
|
@ -510,7 +442,7 @@ enum qeth_large_send_types {
|
|||
struct qeth_qdio_out_buffer {
|
||||
struct qdio_buffer *buffer;
|
||||
atomic_t state;
|
||||
volatile int next_element_to_fill;
|
||||
int next_element_to_fill;
|
||||
struct sk_buff_head skb_list;
|
||||
struct list_head ctx_list;
|
||||
};
|
||||
|
@ -529,11 +461,11 @@ struct qeth_qdio_out_q {
|
|||
int queue_no;
|
||||
struct qeth_card *card;
|
||||
atomic_t state;
|
||||
volatile int do_pack;
|
||||
int do_pack;
|
||||
/*
|
||||
* index of buffer to be filled by driver; state EMPTY or PACKING
|
||||
*/
|
||||
volatile int next_buf_to_fill;
|
||||
int next_buf_to_fill;
|
||||
/*
|
||||
* number of buffers that are currently filled (PRIMED)
|
||||
* -> these buffers are hardware-owned
|
||||
|
@ -624,36 +556,6 @@ enum qeth_cmd_buffer_state {
|
|||
BUF_STATE_LOCKED,
|
||||
BUF_STATE_PROCESSED,
|
||||
};
|
||||
/**
|
||||
* IP address and multicast list
|
||||
*/
|
||||
struct qeth_ipaddr {
|
||||
struct list_head entry;
|
||||
enum qeth_ip_types type;
|
||||
enum qeth_ipa_setdelip_flags set_flags;
|
||||
enum qeth_ipa_setdelip_flags del_flags;
|
||||
int is_multicast;
|
||||
volatile int users;
|
||||
enum qeth_prot_versions proto;
|
||||
unsigned char mac[OSA_ADDR_LEN];
|
||||
union {
|
||||
struct {
|
||||
unsigned int addr;
|
||||
unsigned int mask;
|
||||
} a4;
|
||||
struct {
|
||||
struct in6_addr addr;
|
||||
unsigned int pfxlen;
|
||||
} a6;
|
||||
} u;
|
||||
};
|
||||
|
||||
struct qeth_ipato_entry {
|
||||
struct list_head entry;
|
||||
enum qeth_prot_versions proto;
|
||||
char addr[16];
|
||||
int mask_bits;
|
||||
};
|
||||
|
||||
struct qeth_ipato {
|
||||
int enabled;
|
||||
|
@ -672,7 +574,6 @@ struct qeth_cmd_buffer {
|
|||
void (*callback) (struct qeth_channel *, struct qeth_cmd_buffer *);
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* definition of a qeth channel, used for read and write
|
||||
*/
|
||||
|
@ -686,8 +587,8 @@ struct qeth_channel {
|
|||
/*command buffer for control data*/
|
||||
struct qeth_cmd_buffer iob[QETH_CMD_BUFFER_NO];
|
||||
atomic_t irq_pending;
|
||||
volatile int io_buf_no;
|
||||
volatile int buf_no;
|
||||
int io_buf_no;
|
||||
int buf_no;
|
||||
};
|
||||
|
||||
/**
|
||||
|
@ -717,7 +618,8 @@ struct qeth_seqno {
|
|||
struct qeth_reply {
|
||||
struct list_head list;
|
||||
wait_queue_head_t wait_q;
|
||||
int (*callback)(struct qeth_card *,struct qeth_reply *,unsigned long);
|
||||
int (*callback)(struct qeth_card *, struct qeth_reply *,
|
||||
unsigned long);
|
||||
u32 seqno;
|
||||
unsigned long offset;
|
||||
atomic_t received;
|
||||
|
@ -765,10 +667,8 @@ struct qeth_card_options {
|
|||
struct qeth_routing_info route4;
|
||||
struct qeth_ipa_info ipa4;
|
||||
struct qeth_ipa_info adp; /*Adapter parameters*/
|
||||
#ifdef CONFIG_QETH_IPV6
|
||||
struct qeth_routing_info route6;
|
||||
struct qeth_ipa_info ipa6;
|
||||
#endif /* QETH_IPV6 */
|
||||
enum qeth_checksum_types checksum_type;
|
||||
int broadcast_mode;
|
||||
int macaddr_mode;
|
||||
|
@ -785,9 +685,7 @@ struct qeth_card_options {
|
|||
* thread bits for qeth_card thread masks
|
||||
*/
|
||||
enum qeth_threads {
|
||||
QETH_SET_IP_THREAD = 1,
|
||||
QETH_RECOVER_THREAD = 2,
|
||||
QETH_SET_PROMISC_MODE_THREAD = 4,
|
||||
QETH_RECOVER_THREAD = 1,
|
||||
};
|
||||
|
||||
struct qeth_osn_info {
|
||||
|
@ -795,12 +693,34 @@ struct qeth_osn_info {
|
|||
int (*data_cb)(struct sk_buff *skb);
|
||||
};
|
||||
|
||||
enum qeth_discipline_id {
|
||||
QETH_DISCIPLINE_LAYER3 = 0,
|
||||
QETH_DISCIPLINE_LAYER2 = 1,
|
||||
};
|
||||
|
||||
struct qeth_discipline {
|
||||
qdio_handler_t *input_handler;
|
||||
qdio_handler_t *output_handler;
|
||||
int (*recover)(void *ptr);
|
||||
struct ccwgroup_driver *ccwgdriver;
|
||||
};
|
||||
|
||||
struct qeth_vlan_vid {
|
||||
struct list_head list;
|
||||
unsigned short vid;
|
||||
};
|
||||
|
||||
struct qeth_mc_mac {
|
||||
struct list_head list;
|
||||
__u8 mc_addr[MAX_ADDR_LEN];
|
||||
unsigned char mc_addrlen;
|
||||
};
|
||||
|
||||
struct qeth_card {
|
||||
struct list_head list;
|
||||
enum qeth_card_states state;
|
||||
int lan_online;
|
||||
spinlock_t lock;
|
||||
/*hardware and sysfs stuff*/
|
||||
struct ccwgroup_device *gdev;
|
||||
struct qeth_channel read;
|
||||
struct qeth_channel write;
|
||||
|
@ -815,15 +735,16 @@ struct qeth_card {
|
|||
struct qeth_card_options options;
|
||||
|
||||
wait_queue_head_t wait_q;
|
||||
#ifdef CONFIG_QETH_VLAN
|
||||
spinlock_t vlanlock;
|
||||
spinlock_t mclock;
|
||||
struct vlan_group *vlangrp;
|
||||
#endif
|
||||
struct list_head vid_list;
|
||||
struct list_head mc_list;
|
||||
struct work_struct kernel_thread_starter;
|
||||
spinlock_t thread_mask_lock;
|
||||
volatile unsigned long thread_start_mask;
|
||||
volatile unsigned long thread_allowed_mask;
|
||||
volatile unsigned long thread_running_mask;
|
||||
unsigned long thread_start_mask;
|
||||
unsigned long thread_allowed_mask;
|
||||
unsigned long thread_running_mask;
|
||||
spinlock_t ip_lock;
|
||||
struct list_head ip_list;
|
||||
struct list_head *ip_tbd_list;
|
||||
|
@ -833,8 +754,8 @@ struct qeth_card {
|
|||
struct qeth_qdio_info qdio;
|
||||
struct qeth_perf_stats perf_stats;
|
||||
int use_hard_stop;
|
||||
const struct header_ops *orig_header_ops;
|
||||
struct qeth_osn_info osn_info;
|
||||
struct qeth_discipline discipline;
|
||||
atomic_t force_alloc_skb;
|
||||
};
|
||||
|
||||
|
@ -843,58 +764,23 @@ struct qeth_card_list_struct {
|
|||
rwlock_t rwlock;
|
||||
};
|
||||
|
||||
extern struct qeth_card_list_struct qeth_card_list;
|
||||
|
||||
/*notifier list */
|
||||
struct qeth_notify_list_struct {
|
||||
struct list_head list;
|
||||
struct task_struct *task;
|
||||
int signum;
|
||||
};
|
||||
extern spinlock_t qeth_notify_lock;
|
||||
extern struct list_head qeth_notify_list;
|
||||
|
||||
/*some helper functions*/
|
||||
|
||||
#define QETH_CARD_IFNAME(card) (((card)->dev)? (card)->dev->name : "")
|
||||
|
||||
static inline __u8
|
||||
qeth_get_ipa_adp_type(enum qeth_link_types link_type)
|
||||
static inline struct qeth_card *CARD_FROM_CDEV(struct ccw_device *cdev)
|
||||
{
|
||||
switch (link_type) {
|
||||
case QETH_LINK_TYPE_HSTR:
|
||||
return 2;
|
||||
default:
|
||||
return 1;
|
||||
}
|
||||
struct qeth_card *card = dev_get_drvdata(&((struct ccwgroup_device *)
|
||||
dev_get_drvdata(&cdev->dev))->dev);
|
||||
return card;
|
||||
}
|
||||
|
||||
static inline struct sk_buff *
|
||||
qeth_realloc_headroom(struct qeth_card *card, struct sk_buff *skb, int size)
|
||||
static inline int qeth_get_micros(void)
|
||||
{
|
||||
struct sk_buff *new_skb = skb;
|
||||
|
||||
if (skb_headroom(skb) >= size)
|
||||
return skb;
|
||||
new_skb = skb_realloc_headroom(skb, size);
|
||||
if (!new_skb)
|
||||
PRINT_ERR("Could not realloc headroom for qeth_hdr "
|
||||
"on interface %s", QETH_CARD_IFNAME(card));
|
||||
return new_skb;
|
||||
return (int) (get_clock() >> 12);
|
||||
}
|
||||
|
||||
static inline struct sk_buff *
|
||||
qeth_pskb_unshare(struct sk_buff *skb, gfp_t pri)
|
||||
{
|
||||
struct sk_buff *nskb;
|
||||
if (!skb_cloned(skb))
|
||||
return skb;
|
||||
nskb = skb_copy(skb, pri);
|
||||
return nskb;
|
||||
}
|
||||
|
||||
static inline void *
|
||||
qeth_push_skb(struct qeth_card *card, struct sk_buff *skb, int size)
|
||||
static inline void *qeth_push_skb(struct qeth_card *card, struct sk_buff *skb,
|
||||
int size)
|
||||
{
|
||||
void *hdr;
|
||||
|
||||
|
@ -914,340 +800,117 @@ qeth_push_skb(struct qeth_card *card, struct sk_buff *skb, int size)
|
|||
return hdr;
|
||||
}
|
||||
|
||||
|
||||
static inline int
|
||||
qeth_get_hlen(__u8 link_type)
|
||||
static inline int qeth_get_ip_version(struct sk_buff *skb)
|
||||
{
|
||||
#ifdef CONFIG_QETH_IPV6
|
||||
switch (link_type) {
|
||||
case QETH_LINK_TYPE_HSTR:
|
||||
case QETH_LINK_TYPE_LANE_TR:
|
||||
return sizeof(struct qeth_hdr_tso) + TR_HLEN;
|
||||
default:
|
||||
#ifdef CONFIG_QETH_VLAN
|
||||
return sizeof(struct qeth_hdr_tso) + VLAN_ETH_HLEN;
|
||||
#else
|
||||
return sizeof(struct qeth_hdr_tso) + ETH_HLEN;
|
||||
#endif
|
||||
}
|
||||
#else /* CONFIG_QETH_IPV6 */
|
||||
#ifdef CONFIG_QETH_VLAN
|
||||
return sizeof(struct qeth_hdr_tso) + VLAN_HLEN;
|
||||
#else
|
||||
return sizeof(struct qeth_hdr_tso);
|
||||
#endif
|
||||
#endif /* CONFIG_QETH_IPV6 */
|
||||
}
|
||||
|
||||
static inline unsigned short
|
||||
qeth_get_netdev_flags(struct qeth_card *card)
|
||||
{
|
||||
if (card->options.layer2 &&
|
||||
(card->info.type == QETH_CARD_TYPE_OSAE))
|
||||
return 0;
|
||||
switch (card->info.type) {
|
||||
case QETH_CARD_TYPE_IQD:
|
||||
case QETH_CARD_TYPE_OSN:
|
||||
return IFF_NOARP;
|
||||
#ifdef CONFIG_QETH_IPV6
|
||||
default:
|
||||
return 0;
|
||||
#else
|
||||
default:
|
||||
return IFF_NOARP;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
static inline int
|
||||
qeth_get_initial_mtu_for_card(struct qeth_card * card)
|
||||
{
|
||||
switch (card->info.type) {
|
||||
case QETH_CARD_TYPE_UNKNOWN:
|
||||
return 1500;
|
||||
case QETH_CARD_TYPE_IQD:
|
||||
return card->info.max_mtu;
|
||||
case QETH_CARD_TYPE_OSAE:
|
||||
switch (card->info.link_type) {
|
||||
case QETH_LINK_TYPE_HSTR:
|
||||
case QETH_LINK_TYPE_LANE_TR:
|
||||
return 2000;
|
||||
default:
|
||||
return 1492;
|
||||
}
|
||||
default:
|
||||
return 1500;
|
||||
}
|
||||
}
|
||||
|
||||
static inline int
|
||||
qeth_get_max_mtu_for_card(int cardtype)
|
||||
{
|
||||
switch (cardtype) {
|
||||
|
||||
case QETH_CARD_TYPE_UNKNOWN:
|
||||
case QETH_CARD_TYPE_OSAE:
|
||||
case QETH_CARD_TYPE_OSN:
|
||||
return 61440;
|
||||
case QETH_CARD_TYPE_IQD:
|
||||
return 57344;
|
||||
default:
|
||||
return 1500;
|
||||
}
|
||||
}
|
||||
|
||||
static inline int
|
||||
qeth_get_mtu_out_of_mpc(int cardtype)
|
||||
{
|
||||
switch (cardtype) {
|
||||
case QETH_CARD_TYPE_IQD:
|
||||
return 1;
|
||||
switch (skb->protocol) {
|
||||
case ETH_P_IPV6:
|
||||
return 6;
|
||||
case ETH_P_IP:
|
||||
return 4;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static inline int
|
||||
qeth_get_mtu_outof_framesize(int framesize)
|
||||
{
|
||||
switch (framesize) {
|
||||
case 0x4000:
|
||||
return 8192;
|
||||
case 0x6000:
|
||||
return 16384;
|
||||
case 0xa000:
|
||||
return 32768;
|
||||
case 0xffff:
|
||||
return 57344;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
struct qeth_eddp_context;
|
||||
extern struct ccwgroup_driver qeth_l2_ccwgroup_driver;
|
||||
extern struct ccwgroup_driver qeth_l3_ccwgroup_driver;
|
||||
const char *qeth_get_cardname_short(struct qeth_card *);
|
||||
int qeth_realloc_buffer_pool(struct qeth_card *, int);
|
||||
int qeth_core_load_discipline(struct qeth_card *, enum qeth_discipline_id);
|
||||
void qeth_core_free_discipline(struct qeth_card *);
|
||||
int qeth_core_create_device_attributes(struct device *);
|
||||
void qeth_core_remove_device_attributes(struct device *);
|
||||
int qeth_core_create_osn_attributes(struct device *);
|
||||
void qeth_core_remove_osn_attributes(struct device *);
|
||||
|
||||
static inline int
|
||||
qeth_mtu_is_valid(struct qeth_card * card, int mtu)
|
||||
{
|
||||
switch (card->info.type) {
|
||||
case QETH_CARD_TYPE_OSAE:
|
||||
return ((mtu >= 576) && (mtu <= 61440));
|
||||
case QETH_CARD_TYPE_IQD:
|
||||
return ((mtu >= 576) &&
|
||||
(mtu <= card->info.max_mtu + 4096 - 32));
|
||||
case QETH_CARD_TYPE_OSN:
|
||||
case QETH_CARD_TYPE_UNKNOWN:
|
||||
default:
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
/* exports for qeth discipline device drivers */
|
||||
extern struct qeth_card_list_struct qeth_core_card_list;
|
||||
extern debug_info_t *qeth_dbf_setup;
|
||||
extern debug_info_t *qeth_dbf_data;
|
||||
extern debug_info_t *qeth_dbf_misc;
|
||||
extern debug_info_t *qeth_dbf_control;
|
||||
extern debug_info_t *qeth_dbf_trace;
|
||||
extern debug_info_t *qeth_dbf_sense;
|
||||
extern debug_info_t *qeth_dbf_qerr;
|
||||
|
||||
static inline int
|
||||
qeth_get_arphdr_type(int cardtype, int linktype)
|
||||
{
|
||||
switch (cardtype) {
|
||||
case QETH_CARD_TYPE_OSAE:
|
||||
case QETH_CARD_TYPE_OSN:
|
||||
switch (linktype) {
|
||||
case QETH_LINK_TYPE_LANE_TR:
|
||||
case QETH_LINK_TYPE_HSTR:
|
||||
return ARPHRD_IEEE802_TR;
|
||||
default:
|
||||
return ARPHRD_ETHER;
|
||||
}
|
||||
case QETH_CARD_TYPE_IQD:
|
||||
default:
|
||||
return ARPHRD_ETHER;
|
||||
}
|
||||
}
|
||||
void qeth_set_allowed_threads(struct qeth_card *, unsigned long , int);
|
||||
int qeth_threads_running(struct qeth_card *, unsigned long);
|
||||
int qeth_wait_for_threads(struct qeth_card *, unsigned long);
|
||||
int qeth_do_run_thread(struct qeth_card *, unsigned long);
|
||||
void qeth_clear_thread_start_bit(struct qeth_card *, unsigned long);
|
||||
void qeth_clear_thread_running_bit(struct qeth_card *, unsigned long);
|
||||
int qeth_core_hardsetup_card(struct qeth_card *);
|
||||
void qeth_print_status_message(struct qeth_card *);
|
||||
int qeth_init_qdio_queues(struct qeth_card *);
|
||||
int qeth_send_startlan(struct qeth_card *);
|
||||
int qeth_send_stoplan(struct qeth_card *);
|
||||
int qeth_send_ipa_cmd(struct qeth_card *, struct qeth_cmd_buffer *,
|
||||
int (*reply_cb)
|
||||
(struct qeth_card *, struct qeth_reply *, unsigned long),
|
||||
void *);
|
||||
struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *,
|
||||
enum qeth_ipa_cmds, enum qeth_prot_versions);
|
||||
int qeth_query_setadapterparms(struct qeth_card *);
|
||||
int qeth_check_qdio_errors(struct qdio_buffer *, unsigned int,
|
||||
unsigned int, const char *);
|
||||
void qeth_put_buffer_pool_entry(struct qeth_card *,
|
||||
struct qeth_buffer_pool_entry *);
|
||||
void qeth_queue_input_buffer(struct qeth_card *, int);
|
||||
struct sk_buff *qeth_core_get_next_skb(struct qeth_card *,
|
||||
struct qdio_buffer *, struct qdio_buffer_element **, int *,
|
||||
struct qeth_hdr **);
|
||||
void qeth_schedule_recovery(struct qeth_card *);
|
||||
void qeth_qdio_output_handler(struct ccw_device *, unsigned int,
|
||||
unsigned int, unsigned int,
|
||||
unsigned int, int, int,
|
||||
unsigned long);
|
||||
void qeth_clear_ipacmd_list(struct qeth_card *);
|
||||
int qeth_qdio_clear_card(struct qeth_card *, int);
|
||||
void qeth_clear_working_pool_list(struct qeth_card *);
|
||||
void qeth_clear_cmd_buffers(struct qeth_channel *);
|
||||
void qeth_clear_qdio_buffers(struct qeth_card *);
|
||||
void qeth_setadp_promisc_mode(struct qeth_card *);
|
||||
struct net_device_stats *qeth_get_stats(struct net_device *);
|
||||
int qeth_change_mtu(struct net_device *, int);
|
||||
int qeth_setadpparms_change_macaddr(struct qeth_card *);
|
||||
void qeth_tx_timeout(struct net_device *);
|
||||
void qeth_prepare_control_data(struct qeth_card *, int,
|
||||
struct qeth_cmd_buffer *);
|
||||
void qeth_release_buffer(struct qeth_channel *, struct qeth_cmd_buffer *);
|
||||
void qeth_prepare_ipa_cmd(struct qeth_card *, struct qeth_cmd_buffer *, char);
|
||||
struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *);
|
||||
int qeth_mdio_read(struct net_device *, int, int);
|
||||
int qeth_snmp_command(struct qeth_card *, char __user *);
|
||||
int qeth_set_large_send(struct qeth_card *, enum qeth_large_send_types);
|
||||
struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *, __u32, __u32);
|
||||
int qeth_default_setadapterparms_cb(struct qeth_card *, struct qeth_reply *,
|
||||
unsigned long);
|
||||
int qeth_send_control_data(struct qeth_card *, int, struct qeth_cmd_buffer *,
|
||||
int (*reply_cb)(struct qeth_card *, struct qeth_reply*, unsigned long),
|
||||
void *reply_param);
|
||||
int qeth_get_cast_type(struct qeth_card *, struct sk_buff *);
|
||||
int qeth_get_priority_queue(struct qeth_card *, struct sk_buff *, int, int);
|
||||
struct sk_buff *qeth_prepare_skb(struct qeth_card *, struct sk_buff *,
|
||||
struct qeth_hdr **);
|
||||
int qeth_get_elements_no(struct qeth_card *, void *, struct sk_buff *, int);
|
||||
int qeth_do_send_packet_fast(struct qeth_card *, struct qeth_qdio_out_q *,
|
||||
struct sk_buff *, struct qeth_hdr *, int,
|
||||
struct qeth_eddp_context *);
|
||||
int qeth_do_send_packet(struct qeth_card *, struct qeth_qdio_out_q *,
|
||||
struct sk_buff *, struct qeth_hdr *,
|
||||
int, struct qeth_eddp_context *);
|
||||
int qeth_core_get_stats_count(struct net_device *);
|
||||
void qeth_core_get_ethtool_stats(struct net_device *,
|
||||
struct ethtool_stats *, u64 *);
|
||||
void qeth_core_get_strings(struct net_device *, u32, u8 *);
|
||||
void qeth_core_get_drvinfo(struct net_device *, struct ethtool_drvinfo *);
|
||||
|
||||
static inline int
|
||||
qeth_get_micros(void)
|
||||
{
|
||||
return (int) (get_clock() >> 12);
|
||||
}
|
||||
|
||||
static inline int
|
||||
qeth_get_qdio_q_format(struct qeth_card *card)
|
||||
{
|
||||
switch (card->info.type) {
|
||||
case QETH_CARD_TYPE_IQD:
|
||||
return 2;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static inline int
|
||||
qeth_isxdigit(char * buf)
|
||||
{
|
||||
while (*buf) {
|
||||
if (!isxdigit(*buf++))
|
||||
return 0;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
static inline void
|
||||
qeth_ipaddr4_to_string(const __u8 *addr, char *buf)
|
||||
{
|
||||
sprintf(buf, "%i.%i.%i.%i", addr[0], addr[1], addr[2], addr[3]);
|
||||
}
|
||||
|
||||
static inline int
|
||||
qeth_string_to_ipaddr4(const char *buf, __u8 *addr)
|
||||
{
|
||||
int count = 0, rc = 0;
|
||||
int in[4];
|
||||
char c;
|
||||
|
||||
rc = sscanf(buf, "%u.%u.%u.%u%c",
|
||||
&in[0], &in[1], &in[2], &in[3], &c);
|
||||
if (rc != 4 && (rc != 5 || c != '\n'))
|
||||
return -EINVAL;
|
||||
for (count = 0; count < 4; count++) {
|
||||
if (in[count] > 255)
|
||||
return -EINVAL;
|
||||
addr[count] = in[count];
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void
|
||||
qeth_ipaddr6_to_string(const __u8 *addr, char *buf)
|
||||
{
|
||||
sprintf(buf, "%02x%02x:%02x%02x:%02x%02x:%02x%02x"
|
||||
":%02x%02x:%02x%02x:%02x%02x:%02x%02x",
|
||||
addr[0], addr[1], addr[2], addr[3],
|
||||
addr[4], addr[5], addr[6], addr[7],
|
||||
addr[8], addr[9], addr[10], addr[11],
|
||||
addr[12], addr[13], addr[14], addr[15]);
|
||||
}
|
||||
|
||||
static inline int
|
||||
qeth_string_to_ipaddr6(const char *buf, __u8 *addr)
|
||||
{
|
||||
const char *end, *end_tmp, *start;
|
||||
__u16 *in;
|
||||
char num[5];
|
||||
int num2, cnt, out, found, save_cnt;
|
||||
unsigned short in_tmp[8] = {0, };
|
||||
|
||||
cnt = out = found = save_cnt = num2 = 0;
|
||||
end = start = buf;
|
||||
in = (__u16 *) addr;
|
||||
memset(in, 0, 16);
|
||||
while (*end) {
|
||||
end = strchr(start,':');
|
||||
if (end == NULL) {
|
||||
end = buf + strlen(buf);
|
||||
if ((end_tmp = strchr(start, '\n')) != NULL)
|
||||
end = end_tmp;
|
||||
out = 1;
|
||||
}
|
||||
if ((end - start)) {
|
||||
memset(num, 0, 5);
|
||||
if ((end - start) > 4)
|
||||
return -EINVAL;
|
||||
memcpy(num, start, end - start);
|
||||
if (!qeth_isxdigit(num))
|
||||
return -EINVAL;
|
||||
sscanf(start, "%x", &num2);
|
||||
if (found)
|
||||
in_tmp[save_cnt++] = num2;
|
||||
else
|
||||
in[cnt++] = num2;
|
||||
if (out)
|
||||
break;
|
||||
} else {
|
||||
if (found)
|
||||
return -EINVAL;
|
||||
found = 1;
|
||||
}
|
||||
start = ++end;
|
||||
}
|
||||
if (cnt + save_cnt > 8)
|
||||
return -EINVAL;
|
||||
cnt = 7;
|
||||
while (save_cnt)
|
||||
in[cnt--] = in_tmp[--save_cnt];
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void
|
||||
qeth_ipaddr_to_string(enum qeth_prot_versions proto, const __u8 *addr,
|
||||
char *buf)
|
||||
{
|
||||
if (proto == QETH_PROT_IPV4)
|
||||
qeth_ipaddr4_to_string(addr, buf);
|
||||
else if (proto == QETH_PROT_IPV6)
|
||||
qeth_ipaddr6_to_string(addr, buf);
|
||||
}
|
||||
|
||||
static inline int
|
||||
qeth_string_to_ipaddr(const char *buf, enum qeth_prot_versions proto,
|
||||
__u8 *addr)
|
||||
{
|
||||
if (proto == QETH_PROT_IPV4)
|
||||
return qeth_string_to_ipaddr4(buf, addr);
|
||||
else if (proto == QETH_PROT_IPV6)
|
||||
return qeth_string_to_ipaddr6(buf, addr);
|
||||
else
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
extern int
|
||||
qeth_setrouting_v4(struct qeth_card *);
|
||||
extern int
|
||||
qeth_setrouting_v6(struct qeth_card *);
|
||||
|
||||
extern int
|
||||
qeth_add_ipato_entry(struct qeth_card *, struct qeth_ipato_entry *);
|
||||
|
||||
extern void
|
||||
qeth_del_ipato_entry(struct qeth_card *, enum qeth_prot_versions, u8 *, int);
|
||||
|
||||
extern int
|
||||
qeth_add_vipa(struct qeth_card *, enum qeth_prot_versions, const u8 *);
|
||||
|
||||
extern void
|
||||
qeth_del_vipa(struct qeth_card *, enum qeth_prot_versions, const u8 *);
|
||||
|
||||
extern int
|
||||
qeth_add_rxip(struct qeth_card *, enum qeth_prot_versions, const u8 *);
|
||||
|
||||
extern void
|
||||
qeth_del_rxip(struct qeth_card *, enum qeth_prot_versions, const u8 *);
|
||||
|
||||
extern int
|
||||
qeth_notifier_register(struct task_struct *, int );
|
||||
|
||||
extern int
|
||||
qeth_notifier_unregister(struct task_struct * );
|
||||
|
||||
extern void
|
||||
qeth_schedule_recovery(struct qeth_card *);
|
||||
|
||||
extern int
|
||||
qeth_realloc_buffer_pool(struct qeth_card *, int);
|
||||
|
||||
extern int
|
||||
qeth_set_large_send(struct qeth_card *, enum qeth_large_send_types);
|
||||
|
||||
extern void
|
||||
qeth_fill_header(struct qeth_card *, struct qeth_hdr *,
|
||||
struct sk_buff *, int, int);
|
||||
extern void
|
||||
qeth_flush_buffers(struct qeth_qdio_out_q *, int, int, int);
|
||||
|
||||
extern int
|
||||
qeth_osn_assist(struct net_device *, void *, int);
|
||||
|
||||
extern int
|
||||
qeth_osn_register(unsigned char *read_dev_no,
|
||||
struct net_device **,
|
||||
/* exports for OSN */
|
||||
int qeth_osn_assist(struct net_device *, void *, int);
|
||||
int qeth_osn_register(unsigned char *read_dev_no, struct net_device **,
|
||||
int (*assist_cb)(struct net_device *, void *),
|
||||
int (*data_cb)(struct sk_buff *));
|
||||
void qeth_osn_deregister(struct net_device *);
|
||||
|
||||
extern void
|
||||
qeth_osn_deregister(struct net_device *);
|
||||
|
||||
#endif /* __QETH_H__ */
|
||||
#endif /* __QETH_CORE_H__ */
|
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
@ -0,0 +1,266 @@
|
|||
/*
|
||||
* drivers/s390/net/qeth_core_mpc.c
|
||||
*
|
||||
* Copyright IBM Corp. 2007
|
||||
* Author(s): Frank Pavlic <fpavlic@de.ibm.com>,
|
||||
* Thomas Spatzier <tspat@de.ibm.com>,
|
||||
* Frank Blaschka <frank.blaschka@de.ibm.com>
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <asm/cio.h>
|
||||
#include "qeth_core_mpc.h"
|
||||
|
||||
unsigned char IDX_ACTIVATE_READ[] = {
|
||||
0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x19, 0x01, 0x01, 0x80, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0xc1,
|
||||
0xd3, 0xd3, 0xd6, 0xd3, 0xc5, 0x40, 0x00, 0x00,
|
||||
0x00, 0x00
|
||||
};
|
||||
|
||||
unsigned char IDX_ACTIVATE_WRITE[] = {
|
||||
0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x15, 0x01, 0x01, 0x80, 0x00, 0x00, 0x00, 0x00,
|
||||
0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0xc8, 0xc1,
|
||||
0xd3, 0xd3, 0xd6, 0xd3, 0xc5, 0x40, 0x00, 0x00,
|
||||
0x00, 0x00
|
||||
};
|
||||
|
||||
unsigned char CM_ENABLE[] = {
|
||||
0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
|
||||
0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0x63,
|
||||
0x10, 0x00, 0x00, 0x01,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x81, 0x7e, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x24, 0x00, 0x23,
|
||||
0x00, 0x00, 0x23, 0x05, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x01, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x40,
|
||||
0x00, 0x0c, 0x41, 0x02, 0x00, 0x17, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x0b, 0x04, 0x01,
|
||||
0x7e, 0x04, 0x05, 0x00, 0x01, 0x01, 0x0f,
|
||||
0x00,
|
||||
0x0c, 0x04, 0x02, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff
|
||||
};
|
||||
|
||||
unsigned char CM_SETUP[] = {
|
||||
0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
|
||||
0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0x64,
|
||||
0x10, 0x00, 0x00, 0x01,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x81, 0x7e, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x24, 0x00, 0x24,
|
||||
0x00, 0x00, 0x24, 0x05, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x01, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x40,
|
||||
0x00, 0x0c, 0x41, 0x04, 0x00, 0x18, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x09, 0x04, 0x04,
|
||||
0x05, 0x00, 0x01, 0x01, 0x11,
|
||||
0x00, 0x09, 0x04,
|
||||
0x05, 0x05, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x06,
|
||||
0x04, 0x06, 0xc8, 0x00
|
||||
};
|
||||
|
||||
unsigned char ULP_ENABLE[] = {
|
||||
0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0x6b,
|
||||
0x10, 0x00, 0x00, 0x01,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x41, 0x7e, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x24, 0x00, 0x2b,
|
||||
0x00, 0x00, 0x2b, 0x05, 0x20, 0x01, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x01, 0x00, 0x00, 0x2b, 0x00, 0x00, 0x00, 0x40,
|
||||
0x00, 0x0c, 0x41, 0x02, 0x00, 0x1f, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x0b, 0x04, 0x01,
|
||||
0x03, 0x04, 0x05, 0x00, 0x01, 0x01, 0x12,
|
||||
0x00,
|
||||
0x14, 0x04, 0x0a, 0x00, 0x20, 0x00, 0x00, 0xff,
|
||||
0xff, 0x00, 0x08, 0xc8, 0xe8, 0xc4, 0xf1, 0xc7,
|
||||
0xf1, 0x00, 0x00
|
||||
};
|
||||
|
||||
unsigned char ULP_SETUP[] = {
|
||||
0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
|
||||
0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0x6c,
|
||||
0x10, 0x00, 0x00, 0x01,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x41, 0x7e, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02,
|
||||
0x00, 0x00, 0x00, 0x01, 0x00, 0x24, 0x00, 0x2c,
|
||||
0x00, 0x00, 0x2c, 0x05, 0x20, 0x01, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x01, 0x00, 0x00, 0x2c, 0x00, 0x00, 0x00, 0x40,
|
||||
0x00, 0x0c, 0x41, 0x04, 0x00, 0x20, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x09, 0x04, 0x04,
|
||||
0x05, 0x00, 0x01, 0x01, 0x14,
|
||||
0x00, 0x09, 0x04,
|
||||
0x05, 0x05, 0x30, 0x01, 0x00, 0x00,
|
||||
0x00, 0x06,
|
||||
0x04, 0x06, 0x40, 0x00,
|
||||
0x00, 0x08, 0x04, 0x0b,
|
||||
0x00, 0x00, 0x00, 0x00
|
||||
};
|
||||
|
||||
unsigned char DM_ACT[] = {
|
||||
0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05,
|
||||
0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0x55,
|
||||
0x10, 0x00, 0x00, 0x01,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x41, 0x7e, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x02, 0x00, 0x24, 0x00, 0x15,
|
||||
0x00, 0x00, 0x2c, 0x05, 0x20, 0x01, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x01, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x40,
|
||||
0x00, 0x0c, 0x43, 0x60, 0x00, 0x09, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x09, 0x04, 0x04,
|
||||
0x05, 0x40, 0x01, 0x01, 0x00
|
||||
};
|
||||
|
||||
unsigned char IPA_PDU_HEADER[] = {
|
||||
0x00, 0xe0, 0x00, 0x00, 0x77, 0x77, 0x77, 0x77,
|
||||
0x00, 0x00, 0x00, 0x14, 0x00, 0x00,
|
||||
(IPA_PDU_HEADER_SIZE+sizeof(struct qeth_ipa_cmd)) / 256,
|
||||
(IPA_PDU_HEADER_SIZE+sizeof(struct qeth_ipa_cmd)) % 256,
|
||||
0x10, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
|
||||
0xc1, 0x03, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x24,
|
||||
sizeof(struct qeth_ipa_cmd) / 256,
|
||||
sizeof(struct qeth_ipa_cmd) % 256,
|
||||
0x00,
|
||||
sizeof(struct qeth_ipa_cmd) / 256,
|
||||
sizeof(struct qeth_ipa_cmd) % 256,
|
||||
0x05,
|
||||
0x77, 0x77, 0x77, 0x77,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x01, 0x00,
|
||||
sizeof(struct qeth_ipa_cmd) / 256,
|
||||
sizeof(struct qeth_ipa_cmd) % 256,
|
||||
0x00, 0x00, 0x00, 0x40,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(IPA_PDU_HEADER);
|
||||
|
||||
unsigned char WRITE_CCW[] = {
|
||||
0x01, CCW_FLAG_SLI, 0, 0,
|
||||
0, 0, 0, 0
|
||||
};
|
||||
|
||||
unsigned char READ_CCW[] = {
|
||||
0x02, CCW_FLAG_SLI, 0, 0,
|
||||
0, 0, 0, 0
|
||||
};
|
||||
|
||||
|
||||
struct ipa_rc_msg {
|
||||
enum qeth_ipa_return_codes rc;
|
||||
char *msg;
|
||||
};
|
||||
|
||||
static struct ipa_rc_msg qeth_ipa_rc_msg[] = {
|
||||
{IPA_RC_SUCCESS, "success"},
|
||||
{IPA_RC_NOTSUPP, "Command not supported"},
|
||||
{IPA_RC_IP_TABLE_FULL, "Add Addr IP Table Full - ipv6"},
|
||||
{IPA_RC_UNKNOWN_ERROR, "IPA command failed - reason unknown"},
|
||||
{IPA_RC_UNSUPPORTED_COMMAND, "Command not supported"},
|
||||
{IPA_RC_DUP_IPV6_REMOTE, "ipv6 address already registered remote"},
|
||||
{IPA_RC_DUP_IPV6_HOME, "ipv6 address already registered"},
|
||||
{IPA_RC_UNREGISTERED_ADDR, "Address not registered"},
|
||||
{IPA_RC_NO_ID_AVAILABLE, "No identifiers available"},
|
||||
{IPA_RC_ID_NOT_FOUND, "Identifier not found"},
|
||||
{IPA_RC_INVALID_IP_VERSION, "IP version incorrect"},
|
||||
{IPA_RC_LAN_FRAME_MISMATCH, "LAN and frame mismatch"},
|
||||
{IPA_RC_L2_UNSUPPORTED_CMD, "Unsupported layer 2 command"},
|
||||
{IPA_RC_L2_DUP_MAC, "Duplicate MAC address"},
|
||||
{IPA_RC_L2_ADDR_TABLE_FULL, "Layer2 address table full"},
|
||||
{IPA_RC_L2_DUP_LAYER3_MAC, "Duplicate with layer 3 MAC"},
|
||||
{IPA_RC_L2_GMAC_NOT_FOUND, "GMAC not found"},
|
||||
{IPA_RC_L2_MAC_NOT_FOUND, "L2 mac address not found"},
|
||||
{IPA_RC_L2_INVALID_VLAN_ID, "L2 invalid vlan id"},
|
||||
{IPA_RC_L2_DUP_VLAN_ID, "L2 duplicate vlan id"},
|
||||
{IPA_RC_L2_VLAN_ID_NOT_FOUND, "L2 vlan id not found"},
|
||||
{IPA_RC_DATA_MISMATCH, "Data field mismatch (v4/v6 mixed)"},
|
||||
{IPA_RC_INVALID_MTU_SIZE, "Invalid MTU size"},
|
||||
{IPA_RC_INVALID_LANTYPE, "Invalid LAN type"},
|
||||
{IPA_RC_INVALID_LANNUM, "Invalid LAN num"},
|
||||
{IPA_RC_DUPLICATE_IP_ADDRESS, "Address already registered"},
|
||||
{IPA_RC_IP_ADDR_TABLE_FULL, "IP address table full"},
|
||||
{IPA_RC_LAN_PORT_STATE_ERROR, "LAN port state error"},
|
||||
{IPA_RC_SETIP_NO_STARTLAN, "Setip no startlan received"},
|
||||
{IPA_RC_SETIP_ALREADY_RECEIVED, "Setip already received"},
|
||||
{IPA_RC_IP_ADDR_ALREADY_USED, "IP address already in use on LAN"},
|
||||
{IPA_RC_MULTICAST_FULL, "No task available, multicast full"},
|
||||
{IPA_RC_SETIP_INVALID_VERSION, "SETIP invalid IP version"},
|
||||
{IPA_RC_UNSUPPORTED_SUBCMD, "Unsupported assist subcommand"},
|
||||
{IPA_RC_ARP_ASSIST_NO_ENABLE, "Only partial success, no enable"},
|
||||
{IPA_RC_PRIMARY_ALREADY_DEFINED, "Primary already defined"},
|
||||
{IPA_RC_SECOND_ALREADY_DEFINED, "Secondary already defined"},
|
||||
{IPA_RC_INVALID_SETRTG_INDICATOR, "Invalid SETRTG indicator"},
|
||||
{IPA_RC_MC_ADDR_ALREADY_DEFINED, "Multicast address already defined"},
|
||||
{IPA_RC_LAN_OFFLINE, "STRTLAN_LAN_DISABLED - LAN offline"},
|
||||
{IPA_RC_INVALID_IP_VERSION2, "Invalid IP version"},
|
||||
{IPA_RC_FFFF, "Unknown Error"}
|
||||
};
|
||||
|
||||
|
||||
|
||||
char *qeth_get_ipa_msg(enum qeth_ipa_return_codes rc)
|
||||
{
|
||||
int x = 0;
|
||||
qeth_ipa_rc_msg[sizeof(qeth_ipa_rc_msg) /
|
||||
sizeof(struct ipa_rc_msg) - 1].rc = rc;
|
||||
while (qeth_ipa_rc_msg[x].rc != rc)
|
||||
x++;
|
||||
return qeth_ipa_rc_msg[x].msg;
|
||||
}
|
||||
|
||||
|
||||
struct ipa_cmd_names {
|
||||
enum qeth_ipa_cmds cmd;
|
||||
char *name;
|
||||
};
|
||||
|
||||
static struct ipa_cmd_names qeth_ipa_cmd_names[] = {
|
||||
{IPA_CMD_STARTLAN, "startlan"},
|
||||
{IPA_CMD_STOPLAN, "stoplan"},
|
||||
{IPA_CMD_SETVMAC, "setvmac"},
|
||||
{IPA_CMD_DELVMAC, "delvmca"},
|
||||
{IPA_CMD_SETGMAC, "setgmac"},
|
||||
{IPA_CMD_DELGMAC, "delgmac"},
|
||||
{IPA_CMD_SETVLAN, "setvlan"},
|
||||
{IPA_CMD_DELVLAN, "delvlan"},
|
||||
{IPA_CMD_SETCCID, "setccid"},
|
||||
{IPA_CMD_DELCCID, "delccid"},
|
||||
{IPA_CMD_MODCCID, "modccid"},
|
||||
{IPA_CMD_SETIP, "setip"},
|
||||
{IPA_CMD_QIPASSIST, "qipassist"},
|
||||
{IPA_CMD_SETASSPARMS, "setassparms"},
|
||||
{IPA_CMD_SETIPM, "setipm"},
|
||||
{IPA_CMD_DELIPM, "delipm"},
|
||||
{IPA_CMD_SETRTG, "setrtg"},
|
||||
{IPA_CMD_DELIP, "delip"},
|
||||
{IPA_CMD_SETADAPTERPARMS, "setadapterparms"},
|
||||
{IPA_CMD_SET_DIAG_ASS, "set_diag_ass"},
|
||||
{IPA_CMD_CREATE_ADDR, "create_addr"},
|
||||
{IPA_CMD_DESTROY_ADDR, "destroy_addr"},
|
||||
{IPA_CMD_REGISTER_LOCAL_ADDR, "register_local_addr"},
|
||||
{IPA_CMD_UNREGISTER_LOCAL_ADDR, "unregister_local_addr"},
|
||||
{IPA_CMD_UNKNOWN, "unknown"},
|
||||
};
|
||||
|
||||
char *qeth_get_ipa_cmd_name(enum qeth_ipa_cmds cmd)
|
||||
{
|
||||
int x = 0;
|
||||
qeth_ipa_cmd_names[
|
||||
sizeof(qeth_ipa_cmd_names) /
|
||||
sizeof(struct ipa_cmd_names)-1].cmd = cmd;
|
||||
while (qeth_ipa_cmd_names[x].cmd != cmd)
|
||||
x++;
|
||||
return qeth_ipa_cmd_names[x].name;
|
||||
}
|
|
@ -1,16 +1,14 @@
|
|||
/*
|
||||
* linux/drivers/s390/net/qeth_mpc.h
|
||||
*
|
||||
* Linux on zSeries OSA Express and HiperSockets support
|
||||
*
|
||||
* Copyright 2000,2003 IBM Corporation
|
||||
* Author(s): Utz Bacher <utz.bacher@de.ibm.com>
|
||||
* Thomas Spatzier <tspat@de.ibm.com>
|
||||
* Frank Pavlic <fpavlic@de.ibm.com>
|
||||
* drivers/s390/net/qeth_core_mpc.h
|
||||
*
|
||||
* Copyright IBM Corp. 2007
|
||||
* Author(s): Frank Pavlic <fpavlic@de.ibm.com>,
|
||||
* Thomas Spatzier <tspat@de.ibm.com>,
|
||||
* Frank Blaschka <frank.blaschka@de.ibm.com>
|
||||
*/
|
||||
#ifndef __QETH_MPC_H__
|
||||
#define __QETH_MPC_H__
|
||||
|
||||
#ifndef __QETH_CORE_MPC_H__
|
||||
#define __QETH_CORE_MPC_H__
|
||||
|
||||
#include <asm/qeth.h>
|
||||
|
||||
|
@ -93,7 +91,8 @@ enum qeth_checksum_types {
|
|||
*/
|
||||
#define RESET_ROUTING_FLAG 0x10 /* indicate that routing type shall be set */
|
||||
enum qeth_routing_types {
|
||||
NO_ROUTER = 0, /* TODO: set to bit flag used in IPA Command */
|
||||
/* TODO: set to bit flag used in IPA Command */
|
||||
NO_ROUTER = 0,
|
||||
PRIMARY_ROUTER = 1,
|
||||
SECONDARY_ROUTER = 2,
|
||||
MULTICAST_ROUTER = 3,
|
||||
|
@ -233,14 +232,14 @@ enum qeth_ipa_setdelip_flags {
|
|||
|
||||
/* SETADAPTER IPA Command: ****************************************************/
|
||||
enum qeth_ipa_setadp_cmd {
|
||||
IPA_SETADP_QUERY_COMMANDS_SUPPORTED = 0x01,
|
||||
IPA_SETADP_ALTER_MAC_ADDRESS = 0x02,
|
||||
IPA_SETADP_ADD_DELETE_GROUP_ADDRESS = 0x04,
|
||||
IPA_SETADP_ADD_DELETE_FUNCTIONAL_ADDR = 0x08,
|
||||
IPA_SETADP_SET_ADDRESSING_MODE = 0x10,
|
||||
IPA_SETADP_SET_CONFIG_PARMS = 0x20,
|
||||
IPA_SETADP_SET_CONFIG_PARMS_EXTENDED = 0x40,
|
||||
IPA_SETADP_SET_BROADCAST_MODE = 0x80,
|
||||
IPA_SETADP_QUERY_COMMANDS_SUPPORTED = 0x0001,
|
||||
IPA_SETADP_ALTER_MAC_ADDRESS = 0x0002,
|
||||
IPA_SETADP_ADD_DELETE_GROUP_ADDRESS = 0x0004,
|
||||
IPA_SETADP_ADD_DELETE_FUNCTIONAL_ADDR = 0x0008,
|
||||
IPA_SETADP_SET_ADDRESSING_MODE = 0x0010,
|
||||
IPA_SETADP_SET_CONFIG_PARMS = 0x0020,
|
||||
IPA_SETADP_SET_CONFIG_PARMS_EXTENDED = 0x0040,
|
||||
IPA_SETADP_SET_BROADCAST_MODE = 0x0080,
|
||||
IPA_SETADP_SEND_OSA_MESSAGE = 0x0100,
|
||||
IPA_SETADP_SET_SNMP_CONTROL = 0x0200,
|
||||
IPA_SETADP_QUERY_CARD_INFO = 0x0400,
|
||||
|
@ -397,26 +396,11 @@ struct qeth_ipacmd_setadpparms {
|
|||
} data;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
/* IPFRAME IPA Command: ***************************************************/
|
||||
/* TODO: define in analogy to commands define above */
|
||||
|
||||
/* ADD_ADDR_ENTRY IPA Command: ********************************************/
|
||||
/* TODO: define in analogy to commands define above */
|
||||
|
||||
/* DELETE_ADDR_ENTRY IPA Command: *****************************************/
|
||||
/* TODO: define in analogy to commands define above */
|
||||
|
||||
/* CREATE_ADDR IPA Command: ***********************************************/
|
||||
struct qeth_create_destroy_address {
|
||||
__u8 unique_id[8];
|
||||
} __attribute__ ((packed));
|
||||
|
||||
/* REGISTER_LOCAL_ADDR IPA Command: ***************************************/
|
||||
/* TODO: define in analogy to commands define above */
|
||||
|
||||
/* UNREGISTER_LOCAL_ADDR IPA Command: *************************************/
|
||||
/* TODO: define in analogy to commands define above */
|
||||
|
||||
/* Header for each IPA command */
|
||||
struct qeth_ipacmd_hdr {
|
||||
__u8 command;
|
||||
|
@ -463,10 +447,8 @@ enum qeth_ipa_arp_return_codes {
|
|||
};
|
||||
|
||||
|
||||
extern char *
|
||||
qeth_get_ipa_msg(enum qeth_ipa_return_codes rc);
|
||||
extern char *
|
||||
qeth_get_ipa_cmd_name(enum qeth_ipa_cmds cmd);
|
||||
extern char *qeth_get_ipa_msg(enum qeth_ipa_return_codes rc);
|
||||
extern char *qeth_get_ipa_cmd_name(enum qeth_ipa_cmds cmd);
|
||||
|
||||
#define QETH_SETASS_BASE_LEN (sizeof(struct qeth_ipacmd_hdr) + \
|
||||
sizeof(struct qeth_ipacmd_setassparms_hdr))
|
||||
|
@ -557,6 +539,7 @@ extern unsigned char IDX_ACTIVATE_READ[];
|
|||
extern unsigned char IDX_ACTIVATE_WRITE[];
|
||||
|
||||
#define IDX_ACTIVATE_SIZE 0x22
|
||||
#define QETH_IDX_ACT_PNO(buffer) (buffer+0x0b)
|
||||
#define QETH_IDX_ACT_ISSUER_RM_TOKEN(buffer) (buffer + 0x0c)
|
||||
#define QETH_IDX_NO_PORTNAME_REQUIRED(buffer) ((buffer)[0x0b] & 0x80)
|
||||
#define QETH_IDX_ACT_FUNC_LEVEL(buffer) (buffer + 0x10)
|
|
@ -1,13 +1,11 @@
|
|||
/*
|
||||
* linux/drivers/s390/net/qeth_eddp.c
|
||||
*
|
||||
* Enhanced Device Driver Packing (EDDP) support for the qeth driver.
|
||||
*
|
||||
* Copyright 2004 IBM Corporation
|
||||
*
|
||||
* Author(s): Thomas Spatzier <tspat@de.ibm.com>
|
||||
* drivers/s390/net/qeth_core_offl.c
|
||||
*
|
||||
* Copyright IBM Corp. 2007
|
||||
* Author(s): Thomas Spatzier <tspat@de.ibm.com>,
|
||||
* Frank Blaschka <frank.blaschka@de.ibm.com>
|
||||
*/
|
||||
|
||||
#include <linux/errno.h>
|
||||
#include <linux/ip.h>
|
||||
#include <linux/inetdevice.h>
|
||||
|
@ -18,13 +16,13 @@
|
|||
#include <linux/skbuff.h>
|
||||
|
||||
#include <net/ip.h>
|
||||
#include <net/ip6_checksum.h>
|
||||
|
||||
#include "qeth.h"
|
||||
#include "qeth_mpc.h"
|
||||
#include "qeth_eddp.h"
|
||||
#include "qeth_core.h"
|
||||
#include "qeth_core_mpc.h"
|
||||
#include "qeth_core_offl.h"
|
||||
|
||||
int
|
||||
qeth_eddp_check_buffers_for_context(struct qeth_qdio_out_q *queue,
|
||||
int qeth_eddp_check_buffers_for_context(struct qeth_qdio_out_q *queue,
|
||||
struct qeth_eddp_context *ctx)
|
||||
{
|
||||
int index = queue->next_buf_to_fill;
|
||||
|
@ -49,8 +47,7 @@ qeth_eddp_check_buffers_for_context(struct qeth_qdio_out_q *queue,
|
|||
return buffers_needed;
|
||||
}
|
||||
|
||||
static void
|
||||
qeth_eddp_free_context(struct qeth_eddp_context *ctx)
|
||||
static void qeth_eddp_free_context(struct qeth_eddp_context *ctx)
|
||||
{
|
||||
int i;
|
||||
|
||||
|
@ -63,21 +60,19 @@ qeth_eddp_free_context(struct qeth_eddp_context *ctx)
|
|||
}
|
||||
|
||||
|
||||
static inline void
|
||||
qeth_eddp_get_context(struct qeth_eddp_context *ctx)
|
||||
static void qeth_eddp_get_context(struct qeth_eddp_context *ctx)
|
||||
{
|
||||
atomic_inc(&ctx->refcnt);
|
||||
}
|
||||
|
||||
void
|
||||
qeth_eddp_put_context(struct qeth_eddp_context *ctx)
|
||||
void qeth_eddp_put_context(struct qeth_eddp_context *ctx)
|
||||
{
|
||||
if (atomic_dec_return(&ctx->refcnt) == 0)
|
||||
qeth_eddp_free_context(ctx);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(qeth_eddp_put_context);
|
||||
|
||||
void
|
||||
qeth_eddp_buf_release_contexts(struct qeth_qdio_out_buffer *buf)
|
||||
void qeth_eddp_buf_release_contexts(struct qeth_qdio_out_buffer *buf)
|
||||
{
|
||||
struct qeth_eddp_context_reference *ref;
|
||||
|
||||
|
@ -91,8 +86,7 @@ qeth_eddp_buf_release_contexts(struct qeth_qdio_out_buffer *buf)
|
|||
}
|
||||
}
|
||||
|
||||
static int
|
||||
qeth_eddp_buf_ref_context(struct qeth_qdio_out_buffer *buf,
|
||||
static int qeth_eddp_buf_ref_context(struct qeth_qdio_out_buffer *buf,
|
||||
struct qeth_eddp_context *ctx)
|
||||
{
|
||||
struct qeth_eddp_context_reference *ref;
|
||||
|
@ -107,10 +101,8 @@ qeth_eddp_buf_ref_context(struct qeth_qdio_out_buffer *buf,
|
|||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
qeth_eddp_fill_buffer(struct qeth_qdio_out_q *queue,
|
||||
struct qeth_eddp_context *ctx,
|
||||
int index)
|
||||
int qeth_eddp_fill_buffer(struct qeth_qdio_out_q *queue,
|
||||
struct qeth_eddp_context *ctx, int index)
|
||||
{
|
||||
struct qeth_qdio_out_buffer *buf = NULL;
|
||||
struct qdio_buffer *buffer;
|
||||
|
@ -198,8 +190,7 @@ out:
|
|||
return flush_cnt;
|
||||
}
|
||||
|
||||
static void
|
||||
qeth_eddp_create_segment_hdrs(struct qeth_eddp_context *ctx,
|
||||
static void qeth_eddp_create_segment_hdrs(struct qeth_eddp_context *ctx,
|
||||
struct qeth_eddp_data *eddp, int data_len)
|
||||
{
|
||||
u8 *page;
|
||||
|
@ -258,9 +249,8 @@ qeth_eddp_create_segment_hdrs(struct qeth_eddp_context *ctx,
|
|||
ctx->offset += eddp->thl;
|
||||
}
|
||||
|
||||
static void
|
||||
qeth_eddp_copy_data_tcp(char *dst, struct qeth_eddp_data *eddp, int len,
|
||||
__wsum *hcsum)
|
||||
static void qeth_eddp_copy_data_tcp(char *dst, struct qeth_eddp_data *eddp,
|
||||
int len, __wsum *hcsum)
|
||||
{
|
||||
struct skb_frag_struct *frag;
|
||||
int left_in_frag;
|
||||
|
@ -278,16 +268,17 @@ qeth_eddp_copy_data_tcp(char *dst, struct qeth_eddp_data *eddp, int len,
|
|||
while (len > 0) {
|
||||
if (eddp->frag < 0) {
|
||||
/* we're in skb->data */
|
||||
left_in_frag = (eddp->skb->len - eddp->skb->data_len)
|
||||
left_in_frag = (eddp->skb->len -
|
||||
eddp->skb->data_len)
|
||||
- eddp->skb_offset;
|
||||
src = eddp->skb->data + eddp->skb_offset;
|
||||
} else {
|
||||
frag = &skb_shinfo(eddp->skb)->
|
||||
frags[eddp->frag];
|
||||
frag = &skb_shinfo(eddp->skb)->frags[
|
||||
eddp->frag];
|
||||
left_in_frag = frag->size - eddp->frag_offset;
|
||||
src = (u8 *)(
|
||||
(page_to_pfn(frag->page) << PAGE_SHIFT)+
|
||||
frag->page_offset + eddp->frag_offset);
|
||||
src = (u8 *)((page_to_pfn(frag->page) <<
|
||||
PAGE_SHIFT) + frag->page_offset +
|
||||
eddp->frag_offset);
|
||||
}
|
||||
if (left_in_frag <= 0) {
|
||||
eddp->frag++;
|
||||
|
@ -305,10 +296,8 @@ qeth_eddp_copy_data_tcp(char *dst, struct qeth_eddp_data *eddp, int len,
|
|||
}
|
||||
}
|
||||
|
||||
static void
|
||||
qeth_eddp_create_segment_data_tcp(struct qeth_eddp_context *ctx,
|
||||
struct qeth_eddp_data *eddp, int data_len,
|
||||
__wsum hcsum)
|
||||
static void qeth_eddp_create_segment_data_tcp(struct qeth_eddp_context *ctx,
|
||||
struct qeth_eddp_data *eddp, int data_len, __wsum hcsum)
|
||||
{
|
||||
u8 *page;
|
||||
int page_remainder;
|
||||
|
@ -352,8 +341,8 @@ qeth_eddp_create_segment_data_tcp(struct qeth_eddp_context *ctx,
|
|||
((struct tcphdr *)eddp->th_in_ctx)->check = csum_fold(hcsum);
|
||||
}
|
||||
|
||||
static __wsum
|
||||
qeth_eddp_check_tcp4_hdr(struct qeth_eddp_data *eddp, int data_len)
|
||||
static __wsum qeth_eddp_check_tcp4_hdr(struct qeth_eddp_data *eddp,
|
||||
int data_len)
|
||||
{
|
||||
__wsum phcsum; /* pseudo header checksum */
|
||||
|
||||
|
@ -366,8 +355,8 @@ qeth_eddp_check_tcp4_hdr(struct qeth_eddp_data *eddp, int data_len)
|
|||
return csum_partial((u8 *)&eddp->th, eddp->thl, phcsum);
|
||||
}
|
||||
|
||||
static __wsum
|
||||
qeth_eddp_check_tcp6_hdr(struct qeth_eddp_data *eddp, int data_len)
|
||||
static __wsum qeth_eddp_check_tcp6_hdr(struct qeth_eddp_data *eddp,
|
||||
int data_len)
|
||||
{
|
||||
__be32 proto;
|
||||
__wsum phcsum; /* pseudo header checksum */
|
||||
|
@ -384,8 +373,8 @@ qeth_eddp_check_tcp6_hdr(struct qeth_eddp_data *eddp, int data_len)
|
|||
return phcsum;
|
||||
}
|
||||
|
||||
static struct qeth_eddp_data *
|
||||
qeth_eddp_create_eddp_data(struct qeth_hdr *qh, u8 *nh, u8 nhl, u8 *th, u8 thl)
|
||||
static struct qeth_eddp_data *qeth_eddp_create_eddp_data(struct qeth_hdr *qh,
|
||||
u8 *nh, u8 nhl, u8 *th, u8 thl)
|
||||
{
|
||||
struct qeth_eddp_data *eddp;
|
||||
|
||||
|
@ -402,8 +391,7 @@ qeth_eddp_create_eddp_data(struct qeth_hdr *qh, u8 *nh, u8 nhl, u8 *th, u8 thl)
|
|||
return eddp;
|
||||
}
|
||||
|
||||
static void
|
||||
__qeth_eddp_fill_context_tcp(struct qeth_eddp_context *ctx,
|
||||
static void __qeth_eddp_fill_context_tcp(struct qeth_eddp_context *ctx,
|
||||
struct qeth_eddp_data *eddp)
|
||||
{
|
||||
struct tcphdr *tcph;
|
||||
|
@ -414,10 +402,8 @@ __qeth_eddp_fill_context_tcp(struct qeth_eddp_context *ctx,
|
|||
eddp->skb_offset = sizeof(struct qeth_hdr) + eddp->nhl + eddp->thl;
|
||||
if (eddp->qh.hdr.l2.id == QETH_HEADER_TYPE_LAYER2) {
|
||||
eddp->skb_offset += sizeof(struct ethhdr);
|
||||
#ifdef CONFIG_QETH_VLAN
|
||||
if (eddp->mac.h_proto == __constant_htons(ETH_P_8021Q))
|
||||
eddp->skb_offset += VLAN_HLEN;
|
||||
#endif /* CONFIG_QETH_VLAN */
|
||||
}
|
||||
tcph = tcp_hdr(eddp->skb);
|
||||
while (eddp->skb_offset < eddp->skb->len) {
|
||||
|
@ -427,10 +413,8 @@ __qeth_eddp_fill_context_tcp(struct qeth_eddp_context *ctx,
|
|||
if (eddp->qh.hdr.l2.id == QETH_HEADER_TYPE_LAYER2) {
|
||||
eddp->qh.hdr.l2.pkt_length = data_len + ETH_HLEN +
|
||||
eddp->nhl + eddp->thl;
|
||||
#ifdef CONFIG_QETH_VLAN
|
||||
if (eddp->mac.h_proto == __constant_htons(ETH_P_8021Q))
|
||||
eddp->qh.hdr.l2.pkt_length += VLAN_HLEN;
|
||||
#endif /* CONFIG_QETH_VLAN */
|
||||
} else
|
||||
eddp->qh.hdr.l3.length = data_len + eddp->nhl +
|
||||
eddp->thl;
|
||||
|
@ -443,7 +427,8 @@ __qeth_eddp_fill_context_tcp(struct qeth_eddp_context *ctx,
|
|||
ip_fast_csum((u8 *)&eddp->nh.ip4.h,
|
||||
eddp->nh.ip4.h.ihl);
|
||||
} else
|
||||
eddp->nh.ip6.h.payload_len = htons(data_len + eddp->thl);
|
||||
eddp->nh.ip6.h.payload_len = htons(data_len +
|
||||
eddp->thl);
|
||||
/* prepare tcp hdr */
|
||||
if (data_len == (eddp->skb->len - eddp->skb_offset)) {
|
||||
/* last segment -> set FIN and PSH flags */
|
||||
|
@ -462,12 +447,12 @@ __qeth_eddp_fill_context_tcp(struct qeth_eddp_context *ctx,
|
|||
/* prepare headers for next round */
|
||||
if (eddp->skb->protocol == htons(ETH_P_IP))
|
||||
eddp->nh.ip4.h.id = htons(ntohs(eddp->nh.ip4.h.id) + 1);
|
||||
eddp->th.tcp.h.seq = htonl(ntohl(eddp->th.tcp.h.seq) + data_len);
|
||||
eddp->th.tcp.h.seq = htonl(ntohl(eddp->th.tcp.h.seq) +
|
||||
data_len);
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
qeth_eddp_fill_context_tcp(struct qeth_eddp_context *ctx,
|
||||
static int qeth_eddp_fill_context_tcp(struct qeth_eddp_context *ctx,
|
||||
struct sk_buff *skb, struct qeth_hdr *qhdr)
|
||||
{
|
||||
struct qeth_eddp_data *eddp = NULL;
|
||||
|
@ -494,12 +479,10 @@ qeth_eddp_fill_context_tcp(struct qeth_eddp_context *ctx,
|
|||
if (qhdr->hdr.l2.id == QETH_HEADER_TYPE_LAYER2) {
|
||||
skb_set_mac_header(skb, sizeof(struct qeth_hdr));
|
||||
memcpy(&eddp->mac, eth_hdr(skb), ETH_HLEN);
|
||||
#ifdef CONFIG_QETH_VLAN
|
||||
if (eddp->mac.h_proto == __constant_htons(ETH_P_8021Q)) {
|
||||
eddp->vlan[0] = skb->protocol;
|
||||
eddp->vlan[1] = htons(vlan_tx_tag_get(skb));
|
||||
}
|
||||
#endif /* CONFIG_QETH_VLAN */
|
||||
}
|
||||
/* the next flags will only be set on the last segment */
|
||||
eddp->th.tcp.h.fin = 0;
|
||||
|
@ -511,9 +494,8 @@ qeth_eddp_fill_context_tcp(struct qeth_eddp_context *ctx,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
qeth_eddp_calc_num_pages(struct qeth_eddp_context *ctx, struct sk_buff *skb,
|
||||
int hdr_len)
|
||||
static void qeth_eddp_calc_num_pages(struct qeth_eddp_context *ctx,
|
||||
struct sk_buff *skb, int hdr_len)
|
||||
{
|
||||
int skbs_per_page;
|
||||
|
||||
|
@ -535,9 +517,8 @@ qeth_eddp_calc_num_pages(struct qeth_eddp_context *ctx, struct sk_buff *skb,
|
|||
(skb_shinfo(skb)->gso_segs + 1);
|
||||
}
|
||||
|
||||
static struct qeth_eddp_context *
|
||||
qeth_eddp_create_context_generic(struct qeth_card *card, struct sk_buff *skb,
|
||||
int hdr_len)
|
||||
static struct qeth_eddp_context *qeth_eddp_create_context_generic(
|
||||
struct qeth_card *card, struct sk_buff *skb, int hdr_len)
|
||||
{
|
||||
struct qeth_eddp_context *ctx = NULL;
|
||||
u8 *addr;
|
||||
|
@ -564,14 +545,13 @@ qeth_eddp_create_context_generic(struct qeth_card *card, struct sk_buff *skb,
|
|||
return NULL;
|
||||
}
|
||||
for (i = 0; i < ctx->num_pages; ++i) {
|
||||
addr = (u8 *)__get_free_page(GFP_ATOMIC);
|
||||
addr = (u8 *)get_zeroed_page(GFP_ATOMIC);
|
||||
if (addr == NULL) {
|
||||
QETH_DBF_TEXT(trace, 2, "ceddpcn3");
|
||||
ctx->num_pages = i;
|
||||
qeth_eddp_free_context(ctx);
|
||||
return NULL;
|
||||
}
|
||||
memset(addr, 0, PAGE_SIZE);
|
||||
ctx->pages[i] = addr;
|
||||
}
|
||||
ctx->elements = kcalloc(ctx->num_elements,
|
||||
|
@ -587,8 +567,8 @@ qeth_eddp_create_context_generic(struct qeth_card *card, struct sk_buff *skb,
|
|||
return ctx;
|
||||
}
|
||||
|
||||
static struct qeth_eddp_context *
|
||||
qeth_eddp_create_context_tcp(struct qeth_card *card, struct sk_buff *skb,
|
||||
static struct qeth_eddp_context *qeth_eddp_create_context_tcp(
|
||||
struct qeth_card *card, struct sk_buff *skb,
|
||||
struct qeth_hdr *qhdr)
|
||||
{
|
||||
struct qeth_eddp_context *ctx = NULL;
|
||||
|
@ -619,9 +599,9 @@ qeth_eddp_create_context_tcp(struct qeth_card *card, struct sk_buff *skb,
|
|||
return ctx;
|
||||
}
|
||||
|
||||
struct qeth_eddp_context *
|
||||
qeth_eddp_create_context(struct qeth_card *card, struct sk_buff *skb,
|
||||
struct qeth_hdr *qhdr, unsigned char sk_protocol)
|
||||
struct qeth_eddp_context *qeth_eddp_create_context(struct qeth_card *card,
|
||||
struct sk_buff *skb, struct qeth_hdr *qhdr,
|
||||
unsigned char sk_protocol)
|
||||
{
|
||||
QETH_DBF_TEXT(trace, 5, "creddpc");
|
||||
switch (sk_protocol) {
|
||||
|
@ -632,3 +612,90 @@ qeth_eddp_create_context(struct qeth_card *card, struct sk_buff *skb,
|
|||
}
|
||||
return NULL;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(qeth_eddp_create_context);
|
||||
|
||||
void qeth_tso_fill_header(struct qeth_card *card, struct qeth_hdr *qhdr,
|
||||
struct sk_buff *skb)
|
||||
{
|
||||
struct qeth_hdr_tso *hdr = (struct qeth_hdr_tso *)qhdr;
|
||||
struct tcphdr *tcph = tcp_hdr(skb);
|
||||
struct iphdr *iph = ip_hdr(skb);
|
||||
struct ipv6hdr *ip6h = ipv6_hdr(skb);
|
||||
|
||||
QETH_DBF_TEXT(trace, 5, "tsofhdr");
|
||||
|
||||
/*fix header to TSO values ...*/
|
||||
hdr->hdr.hdr.l3.id = QETH_HEADER_TYPE_TSO;
|
||||
/*set values which are fix for the first approach ...*/
|
||||
hdr->ext.hdr_tot_len = (__u16) sizeof(struct qeth_hdr_ext_tso);
|
||||
hdr->ext.imb_hdr_no = 1;
|
||||
hdr->ext.hdr_type = 1;
|
||||
hdr->ext.hdr_version = 1;
|
||||
hdr->ext.hdr_len = 28;
|
||||
/*insert non-fix values */
|
||||
hdr->ext.mss = skb_shinfo(skb)->gso_size;
|
||||
hdr->ext.dg_hdr_len = (__u16)(iph->ihl*4 + tcph->doff*4);
|
||||
hdr->ext.payload_len = (__u16)(skb->len - hdr->ext.dg_hdr_len -
|
||||
sizeof(struct qeth_hdr_tso));
|
||||
tcph->check = 0;
|
||||
if (skb->protocol == ETH_P_IPV6) {
|
||||
ip6h->payload_len = 0;
|
||||
tcph->check = ~csum_ipv6_magic(&ip6h->saddr, &ip6h->daddr,
|
||||
0, IPPROTO_TCP, 0);
|
||||
} else {
|
||||
/*OSA want us to set these values ...*/
|
||||
tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
|
||||
0, IPPROTO_TCP, 0);
|
||||
iph->tot_len = 0;
|
||||
iph->check = 0;
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(qeth_tso_fill_header);
|
||||
|
||||
void qeth_tx_csum(struct sk_buff *skb)
|
||||
{
|
||||
int tlen;
|
||||
if (skb->protocol == htons(ETH_P_IP)) {
|
||||
tlen = ntohs(ip_hdr(skb)->tot_len) - (ip_hdr(skb)->ihl << 2);
|
||||
switch (ip_hdr(skb)->protocol) {
|
||||
case IPPROTO_TCP:
|
||||
tcp_hdr(skb)->check = 0;
|
||||
tcp_hdr(skb)->check = csum_tcpudp_magic(
|
||||
ip_hdr(skb)->saddr, ip_hdr(skb)->daddr,
|
||||
tlen, ip_hdr(skb)->protocol,
|
||||
skb_checksum(skb, skb_transport_offset(skb),
|
||||
tlen, 0));
|
||||
break;
|
||||
case IPPROTO_UDP:
|
||||
udp_hdr(skb)->check = 0;
|
||||
udp_hdr(skb)->check = csum_tcpudp_magic(
|
||||
ip_hdr(skb)->saddr, ip_hdr(skb)->daddr,
|
||||
tlen, ip_hdr(skb)->protocol,
|
||||
skb_checksum(skb, skb_transport_offset(skb),
|
||||
tlen, 0));
|
||||
break;
|
||||
}
|
||||
} else if (skb->protocol == htons(ETH_P_IPV6)) {
|
||||
switch (ipv6_hdr(skb)->nexthdr) {
|
||||
case IPPROTO_TCP:
|
||||
tcp_hdr(skb)->check = 0;
|
||||
tcp_hdr(skb)->check = csum_ipv6_magic(
|
||||
&ipv6_hdr(skb)->saddr, &ipv6_hdr(skb)->daddr,
|
||||
ipv6_hdr(skb)->payload_len,
|
||||
ipv6_hdr(skb)->nexthdr,
|
||||
skb_checksum(skb, skb_transport_offset(skb),
|
||||
ipv6_hdr(skb)->payload_len, 0));
|
||||
break;
|
||||
case IPPROTO_UDP:
|
||||
udp_hdr(skb)->check = 0;
|
||||
udp_hdr(skb)->check = csum_ipv6_magic(
|
||||
&ipv6_hdr(skb)->saddr, &ipv6_hdr(skb)->daddr,
|
||||
ipv6_hdr(skb)->payload_len,
|
||||
ipv6_hdr(skb)->nexthdr,
|
||||
skb_checksum(skb, skb_transport_offset(skb),
|
||||
ipv6_hdr(skb)->payload_len, 0));
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(qeth_tx_csum);
|
|
@ -1,15 +1,13 @@
|
|||
/*
|
||||
* linux/drivers/s390/net/qeth_eddp.h
|
||||
*
|
||||
* Header file for qeth enhanced device driver packing.
|
||||
*
|
||||
* Copyright 2004 IBM Corporation
|
||||
*
|
||||
* Author(s): Thomas Spatzier <tspat@de.ibm.com>
|
||||
* drivers/s390/net/qeth_core_offl.h
|
||||
*
|
||||
* Copyright IBM Corp. 2007
|
||||
* Author(s): Thomas Spatzier <tspat@de.ibm.com>,
|
||||
* Frank Blaschka <frank.blaschka@de.ibm.com>
|
||||
*/
|
||||
#ifndef __QETH_EDDP_H__
|
||||
#define __QETH_EDDP_H__
|
||||
|
||||
#ifndef __QETH_CORE_OFFL_H__
|
||||
#define __QETH_CORE_OFFL_H__
|
||||
|
||||
struct qeth_eddp_element {
|
||||
u32 flags;
|
||||
|
@ -33,25 +31,6 @@ struct qeth_eddp_context_reference {
|
|||
struct qeth_eddp_context *ctx;
|
||||
};
|
||||
|
||||
extern struct qeth_eddp_context *
|
||||
qeth_eddp_create_context(struct qeth_card *,struct sk_buff *,
|
||||
struct qeth_hdr *, unsigned char);
|
||||
|
||||
extern void
|
||||
qeth_eddp_put_context(struct qeth_eddp_context *);
|
||||
|
||||
extern int
|
||||
qeth_eddp_fill_buffer(struct qeth_qdio_out_q *,struct qeth_eddp_context *,int);
|
||||
|
||||
extern void
|
||||
qeth_eddp_buf_release_contexts(struct qeth_qdio_out_buffer *);
|
||||
|
||||
extern int
|
||||
qeth_eddp_check_buffers_for_context(struct qeth_qdio_out_q *,
|
||||
struct qeth_eddp_context *);
|
||||
/*
|
||||
* Data used for fragmenting a IP packet.
|
||||
*/
|
||||
struct qeth_eddp_data {
|
||||
struct qeth_hdr qh;
|
||||
struct ethhdr mac;
|
||||
|
@ -81,4 +60,17 @@ struct qeth_eddp_data {
|
|||
int frag_offset;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
#endif /* __QETH_EDDP_H__ */
|
||||
extern struct qeth_eddp_context *qeth_eddp_create_context(struct qeth_card *,
|
||||
struct sk_buff *, struct qeth_hdr *, unsigned char);
|
||||
extern void qeth_eddp_put_context(struct qeth_eddp_context *);
|
||||
extern int qeth_eddp_fill_buffer(struct qeth_qdio_out_q *,
|
||||
struct qeth_eddp_context *, int);
|
||||
extern void qeth_eddp_buf_release_contexts(struct qeth_qdio_out_buffer *);
|
||||
extern int qeth_eddp_check_buffers_for_context(struct qeth_qdio_out_q *,
|
||||
struct qeth_eddp_context *);
|
||||
|
||||
void qeth_tso_fill_header(struct qeth_card *, struct qeth_hdr *,
|
||||
struct sk_buff *);
|
||||
void qeth_tx_csum(struct sk_buff *skb);
|
||||
|
||||
#endif /* __QETH_CORE_EDDP_H__ */
|
|
@ -0,0 +1,651 @@
|
|||
/*
|
||||
* drivers/s390/net/qeth_core_sys.c
|
||||
*
|
||||
* Copyright IBM Corp. 2007
|
||||
* Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
|
||||
* Frank Pavlic <fpavlic@de.ibm.com>,
|
||||
* Thomas Spatzier <tspat@de.ibm.com>,
|
||||
* Frank Blaschka <frank.blaschka@de.ibm.com>
|
||||
*/
|
||||
|
||||
#include <linux/list.h>
|
||||
#include <linux/rwsem.h>
|
||||
#include <asm/ebcdic.h>
|
||||
|
||||
#include "qeth_core.h"
|
||||
|
||||
static ssize_t qeth_dev_state_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct qeth_card *card = dev_get_drvdata(dev);
|
||||
if (!card)
|
||||
return -EINVAL;
|
||||
|
||||
switch (card->state) {
|
||||
case CARD_STATE_DOWN:
|
||||
return sprintf(buf, "DOWN\n");
|
||||
case CARD_STATE_HARDSETUP:
|
||||
return sprintf(buf, "HARDSETUP\n");
|
||||
case CARD_STATE_SOFTSETUP:
|
||||
return sprintf(buf, "SOFTSETUP\n");
|
||||
case CARD_STATE_UP:
|
||||
if (card->lan_online)
|
||||
return sprintf(buf, "UP (LAN ONLINE)\n");
|
||||
else
|
||||
return sprintf(buf, "UP (LAN OFFLINE)\n");
|
||||
case CARD_STATE_RECOVER:
|
||||
return sprintf(buf, "RECOVER\n");
|
||||
default:
|
||||
return sprintf(buf, "UNKNOWN\n");
|
||||
}
|
||||
}
|
||||
|
||||
static DEVICE_ATTR(state, 0444, qeth_dev_state_show, NULL);
|
||||
|
||||
static ssize_t qeth_dev_chpid_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct qeth_card *card = dev_get_drvdata(dev);
|
||||
if (!card)
|
||||
return -EINVAL;
|
||||
|
||||
return sprintf(buf, "%02X\n", card->info.chpid);
|
||||
}
|
||||
|
||||
static DEVICE_ATTR(chpid, 0444, qeth_dev_chpid_show, NULL);
|
||||
|
||||
static ssize_t qeth_dev_if_name_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct qeth_card *card = dev_get_drvdata(dev);
|
||||
if (!card)
|
||||
return -EINVAL;
|
||||
return sprintf(buf, "%s\n", QETH_CARD_IFNAME(card));
|
||||
}
|
||||
|
||||
static DEVICE_ATTR(if_name, 0444, qeth_dev_if_name_show, NULL);
|
||||
|
||||
static ssize_t qeth_dev_card_type_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct qeth_card *card = dev_get_drvdata(dev);
|
||||
if (!card)
|
||||
return -EINVAL;
|
||||
|
||||
return sprintf(buf, "%s\n", qeth_get_cardname_short(card));
|
||||
}
|
||||
|
||||
static DEVICE_ATTR(card_type, 0444, qeth_dev_card_type_show, NULL);
|
||||
|
||||
static inline const char *qeth_get_bufsize_str(struct qeth_card *card)
|
||||
{
|
||||
if (card->qdio.in_buf_size == 16384)
|
||||
return "16k";
|
||||
else if (card->qdio.in_buf_size == 24576)
|
||||
return "24k";
|
||||
else if (card->qdio.in_buf_size == 32768)
|
||||
return "32k";
|
||||
else if (card->qdio.in_buf_size == 40960)
|
||||
return "40k";
|
||||
else
|
||||
return "64k";
|
||||
}
|
||||
|
||||
static ssize_t qeth_dev_inbuf_size_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct qeth_card *card = dev_get_drvdata(dev);
|
||||
if (!card)
|
||||
return -EINVAL;
|
||||
|
||||
return sprintf(buf, "%s\n", qeth_get_bufsize_str(card));
|
||||
}
|
||||
|
||||
static DEVICE_ATTR(inbuf_size, 0444, qeth_dev_inbuf_size_show, NULL);
|
||||
|
||||
static ssize_t qeth_dev_portno_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct qeth_card *card = dev_get_drvdata(dev);
|
||||
if (!card)
|
||||
return -EINVAL;
|
||||
|
||||
return sprintf(buf, "%i\n", card->info.portno);
|
||||
}
|
||||
|
||||
static ssize_t qeth_dev_portno_store(struct device *dev,
|
||||
struct device_attribute *attr, const char *buf, size_t count)
|
||||
{
|
||||
struct qeth_card *card = dev_get_drvdata(dev);
|
||||
char *tmp;
|
||||
unsigned int portno;
|
||||
|
||||
if (!card)
|
||||
return -EINVAL;
|
||||
|
||||
if ((card->state != CARD_STATE_DOWN) &&
|
||||
(card->state != CARD_STATE_RECOVER))
|
||||
return -EPERM;
|
||||
|
||||
portno = simple_strtoul(buf, &tmp, 16);
|
||||
if (portno > QETH_MAX_PORTNO) {
|
||||
PRINT_WARN("portno 0x%X is out of range\n", portno);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
card->info.portno = portno;
|
||||
return count;
|
||||
}
|
||||
|
||||
static DEVICE_ATTR(portno, 0644, qeth_dev_portno_show, qeth_dev_portno_store);
|
||||
|
||||
static ssize_t qeth_dev_portname_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct qeth_card *card = dev_get_drvdata(dev);
|
||||
char portname[9] = {0, };
|
||||
|
||||
if (!card)
|
||||
return -EINVAL;
|
||||
|
||||
if (card->info.portname_required) {
|
||||
memcpy(portname, card->info.portname + 1, 8);
|
||||
EBCASC(portname, 8);
|
||||
return sprintf(buf, "%s\n", portname);
|
||||
} else
|
||||
return sprintf(buf, "no portname required\n");
|
||||
}
|
||||
|
||||
static ssize_t qeth_dev_portname_store(struct device *dev,
|
||||
struct device_attribute *attr, const char *buf, size_t count)
|
||||
{
|
||||
struct qeth_card *card = dev_get_drvdata(dev);
|
||||
char *tmp;
|
||||
int i;
|
||||
|
||||
if (!card)
|
||||
return -EINVAL;
|
||||
|
||||
if ((card->state != CARD_STATE_DOWN) &&
|
||||
(card->state != CARD_STATE_RECOVER))
|
||||
return -EPERM;
|
||||
|
||||
tmp = strsep((char **) &buf, "\n");
|
||||
if ((strlen(tmp) > 8) || (strlen(tmp) == 0))
|
||||
return -EINVAL;
|
||||
|
||||
card->info.portname[0] = strlen(tmp);
|
||||
/* for beauty reasons */
|
||||
for (i = 1; i < 9; i++)
|
||||
card->info.portname[i] = ' ';
|
||||
strcpy(card->info.portname + 1, tmp);
|
||||
ASCEBC(card->info.portname + 1, 8);
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
static DEVICE_ATTR(portname, 0644, qeth_dev_portname_show,
|
||||
qeth_dev_portname_store);
|
||||
|
||||
static ssize_t qeth_dev_prioqing_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct qeth_card *card = dev_get_drvdata(dev);
|
||||
|
||||
if (!card)
|
||||
return -EINVAL;
|
||||
|
||||
switch (card->qdio.do_prio_queueing) {
|
||||
case QETH_PRIO_Q_ING_PREC:
|
||||
return sprintf(buf, "%s\n", "by precedence");
|
||||
case QETH_PRIO_Q_ING_TOS:
|
||||
return sprintf(buf, "%s\n", "by type of service");
|
||||
default:
|
||||
return sprintf(buf, "always queue %i\n",
|
||||
card->qdio.default_out_queue);
|
||||
}
|
||||
}
|
||||
|
||||
static ssize_t qeth_dev_prioqing_store(struct device *dev,
|
||||
struct device_attribute *attr, const char *buf, size_t count)
|
||||
{
|
||||
struct qeth_card *card = dev_get_drvdata(dev);
|
||||
char *tmp;
|
||||
|
||||
if (!card)
|
||||
return -EINVAL;
|
||||
|
||||
if ((card->state != CARD_STATE_DOWN) &&
|
||||
(card->state != CARD_STATE_RECOVER))
|
||||
return -EPERM;
|
||||
|
||||
/* check if 1920 devices are supported ,
|
||||
* if though we have to permit priority queueing
|
||||
*/
|
||||
if (card->qdio.no_out_queues == 1) {
|
||||
PRINT_WARN("Priority queueing disabled due "
|
||||
"to hardware limitations!\n");
|
||||
card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
|
||||
return -EPERM;
|
||||
}
|
||||
|
||||
tmp = strsep((char **) &buf, "\n");
|
||||
if (!strcmp(tmp, "prio_queueing_prec"))
|
||||
card->qdio.do_prio_queueing = QETH_PRIO_Q_ING_PREC;
|
||||
else if (!strcmp(tmp, "prio_queueing_tos"))
|
||||
card->qdio.do_prio_queueing = QETH_PRIO_Q_ING_TOS;
|
||||
else if (!strcmp(tmp, "no_prio_queueing:0")) {
|
||||
card->qdio.do_prio_queueing = QETH_NO_PRIO_QUEUEING;
|
||||
card->qdio.default_out_queue = 0;
|
||||
} else if (!strcmp(tmp, "no_prio_queueing:1")) {
|
||||
card->qdio.do_prio_queueing = QETH_NO_PRIO_QUEUEING;
|
||||
card->qdio.default_out_queue = 1;
|
||||
} else if (!strcmp(tmp, "no_prio_queueing:2")) {
|
||||
card->qdio.do_prio_queueing = QETH_NO_PRIO_QUEUEING;
|
||||
card->qdio.default_out_queue = 2;
|
||||
} else if (!strcmp(tmp, "no_prio_queueing:3")) {
|
||||
card->qdio.do_prio_queueing = QETH_NO_PRIO_QUEUEING;
|
||||
card->qdio.default_out_queue = 3;
|
||||
} else if (!strcmp(tmp, "no_prio_queueing")) {
|
||||
card->qdio.do_prio_queueing = QETH_NO_PRIO_QUEUEING;
|
||||
card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
|
||||
} else {
|
||||
PRINT_WARN("Unknown queueing type '%s'\n", tmp);
|
||||
return -EINVAL;
|
||||
}
|
||||
return count;
|
||||
}
|
||||
|
||||
static DEVICE_ATTR(priority_queueing, 0644, qeth_dev_prioqing_show,
|
||||
qeth_dev_prioqing_store);
|
||||
|
||||
static ssize_t qeth_dev_bufcnt_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct qeth_card *card = dev_get_drvdata(dev);
|
||||
|
||||
if (!card)
|
||||
return -EINVAL;
|
||||
|
||||
return sprintf(buf, "%i\n", card->qdio.in_buf_pool.buf_count);
|
||||
}
|
||||
|
||||
static ssize_t qeth_dev_bufcnt_store(struct device *dev,
|
||||
struct device_attribute *attr, const char *buf, size_t count)
|
||||
{
|
||||
struct qeth_card *card = dev_get_drvdata(dev);
|
||||
char *tmp;
|
||||
int cnt, old_cnt;
|
||||
int rc;
|
||||
|
||||
if (!card)
|
||||
return -EINVAL;
|
||||
|
||||
if ((card->state != CARD_STATE_DOWN) &&
|
||||
(card->state != CARD_STATE_RECOVER))
|
||||
return -EPERM;
|
||||
|
||||
old_cnt = card->qdio.in_buf_pool.buf_count;
|
||||
cnt = simple_strtoul(buf, &tmp, 10);
|
||||
cnt = (cnt < QETH_IN_BUF_COUNT_MIN) ? QETH_IN_BUF_COUNT_MIN :
|
||||
((cnt > QETH_IN_BUF_COUNT_MAX) ? QETH_IN_BUF_COUNT_MAX : cnt);
|
||||
if (old_cnt != cnt) {
|
||||
rc = qeth_realloc_buffer_pool(card, cnt);
|
||||
if (rc)
|
||||
PRINT_WARN("Error (%d) while setting "
|
||||
"buffer count.\n", rc);
|
||||
}
|
||||
return count;
|
||||
}
|
||||
|
||||
static DEVICE_ATTR(buffer_count, 0644, qeth_dev_bufcnt_show,
|
||||
qeth_dev_bufcnt_store);
|
||||
|
||||
static ssize_t qeth_dev_recover_store(struct device *dev,
|
||||
struct device_attribute *attr, const char *buf, size_t count)
|
||||
{
|
||||
struct qeth_card *card = dev_get_drvdata(dev);
|
||||
char *tmp;
|
||||
int i;
|
||||
|
||||
if (!card)
|
||||
return -EINVAL;
|
||||
|
||||
if (card->state != CARD_STATE_UP)
|
||||
return -EPERM;
|
||||
|
||||
i = simple_strtoul(buf, &tmp, 16);
|
||||
if (i == 1)
|
||||
qeth_schedule_recovery(card);
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
static DEVICE_ATTR(recover, 0200, NULL, qeth_dev_recover_store);
|
||||
|
||||
static ssize_t qeth_dev_performance_stats_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct qeth_card *card = dev_get_drvdata(dev);
|
||||
|
||||
if (!card)
|
||||
return -EINVAL;
|
||||
|
||||
return sprintf(buf, "%i\n", card->options.performance_stats ? 1:0);
|
||||
}
|
||||
|
||||
static ssize_t qeth_dev_performance_stats_store(struct device *dev,
|
||||
struct device_attribute *attr, const char *buf, size_t count)
|
||||
{
|
||||
struct qeth_card *card = dev_get_drvdata(dev);
|
||||
char *tmp;
|
||||
int i;
|
||||
|
||||
if (!card)
|
||||
return -EINVAL;
|
||||
|
||||
i = simple_strtoul(buf, &tmp, 16);
|
||||
if ((i == 0) || (i == 1)) {
|
||||
if (i == card->options.performance_stats)
|
||||
return count;
|
||||
card->options.performance_stats = i;
|
||||
if (i == 0)
|
||||
memset(&card->perf_stats, 0,
|
||||
sizeof(struct qeth_perf_stats));
|
||||
card->perf_stats.initial_rx_packets = card->stats.rx_packets;
|
||||
card->perf_stats.initial_tx_packets = card->stats.tx_packets;
|
||||
} else {
|
||||
PRINT_WARN("performance_stats: write 0 or 1 to this file!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
return count;
|
||||
}
|
||||
|
||||
static DEVICE_ATTR(performance_stats, 0644, qeth_dev_performance_stats_show,
|
||||
qeth_dev_performance_stats_store);
|
||||
|
||||
static ssize_t qeth_dev_layer2_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct qeth_card *card = dev_get_drvdata(dev);
|
||||
|
||||
if (!card)
|
||||
return -EINVAL;
|
||||
|
||||
return sprintf(buf, "%i\n", card->options.layer2 ? 1:0);
|
||||
}
|
||||
|
||||
static ssize_t qeth_dev_layer2_store(struct device *dev,
|
||||
struct device_attribute *attr, const char *buf, size_t count)
|
||||
{
|
||||
struct qeth_card *card = dev_get_drvdata(dev);
|
||||
char *tmp;
|
||||
int i, rc;
|
||||
enum qeth_discipline_id newdis;
|
||||
|
||||
if (!card)
|
||||
return -EINVAL;
|
||||
|
||||
if (((card->state != CARD_STATE_DOWN) &&
|
||||
(card->state != CARD_STATE_RECOVER)))
|
||||
return -EPERM;
|
||||
|
||||
i = simple_strtoul(buf, &tmp, 16);
|
||||
switch (i) {
|
||||
case 0:
|
||||
newdis = QETH_DISCIPLINE_LAYER3;
|
||||
break;
|
||||
case 1:
|
||||
newdis = QETH_DISCIPLINE_LAYER2;
|
||||
break;
|
||||
default:
|
||||
PRINT_WARN("layer2: write 0 or 1 to this file!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (card->options.layer2 == newdis) {
|
||||
return count;
|
||||
} else {
|
||||
if (card->discipline.ccwgdriver) {
|
||||
card->discipline.ccwgdriver->remove(card->gdev);
|
||||
qeth_core_free_discipline(card);
|
||||
}
|
||||
}
|
||||
|
||||
rc = qeth_core_load_discipline(card, newdis);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
rc = card->discipline.ccwgdriver->probe(card->gdev);
|
||||
if (rc)
|
||||
return rc;
|
||||
return count;
|
||||
}
|
||||
|
||||
static DEVICE_ATTR(layer2, 0644, qeth_dev_layer2_show,
|
||||
qeth_dev_layer2_store);
|
||||
|
||||
static ssize_t qeth_dev_large_send_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct qeth_card *card = dev_get_drvdata(dev);
|
||||
|
||||
if (!card)
|
||||
return -EINVAL;
|
||||
|
||||
switch (card->options.large_send) {
|
||||
case QETH_LARGE_SEND_NO:
|
||||
return sprintf(buf, "%s\n", "no");
|
||||
case QETH_LARGE_SEND_EDDP:
|
||||
return sprintf(buf, "%s\n", "EDDP");
|
||||
case QETH_LARGE_SEND_TSO:
|
||||
return sprintf(buf, "%s\n", "TSO");
|
||||
default:
|
||||
return sprintf(buf, "%s\n", "N/A");
|
||||
}
|
||||
}
|
||||
|
||||
static ssize_t qeth_dev_large_send_store(struct device *dev,
|
||||
struct device_attribute *attr, const char *buf, size_t count)
|
||||
{
|
||||
struct qeth_card *card = dev_get_drvdata(dev);
|
||||
enum qeth_large_send_types type;
|
||||
int rc = 0;
|
||||
char *tmp;
|
||||
|
||||
if (!card)
|
||||
return -EINVAL;
|
||||
tmp = strsep((char **) &buf, "\n");
|
||||
if (!strcmp(tmp, "no")) {
|
||||
type = QETH_LARGE_SEND_NO;
|
||||
} else if (!strcmp(tmp, "EDDP")) {
|
||||
type = QETH_LARGE_SEND_EDDP;
|
||||
} else if (!strcmp(tmp, "TSO")) {
|
||||
type = QETH_LARGE_SEND_TSO;
|
||||
} else {
|
||||
PRINT_WARN("large_send: invalid mode %s!\n", tmp);
|
||||
return -EINVAL;
|
||||
}
|
||||
if (card->options.large_send == type)
|
||||
return count;
|
||||
rc = qeth_set_large_send(card, type);
|
||||
if (rc)
|
||||
return rc;
|
||||
return count;
|
||||
}
|
||||
|
||||
static DEVICE_ATTR(large_send, 0644, qeth_dev_large_send_show,
|
||||
qeth_dev_large_send_store);
|
||||
|
||||
static ssize_t qeth_dev_blkt_show(char *buf, struct qeth_card *card, int value)
|
||||
{
|
||||
|
||||
if (!card)
|
||||
return -EINVAL;
|
||||
|
||||
return sprintf(buf, "%i\n", value);
|
||||
}
|
||||
|
||||
static ssize_t qeth_dev_blkt_store(struct qeth_card *card,
|
||||
const char *buf, size_t count, int *value, int max_value)
|
||||
{
|
||||
char *tmp;
|
||||
int i;
|
||||
|
||||
if (!card)
|
||||
return -EINVAL;
|
||||
|
||||
if ((card->state != CARD_STATE_DOWN) &&
|
||||
(card->state != CARD_STATE_RECOVER))
|
||||
return -EPERM;
|
||||
|
||||
i = simple_strtoul(buf, &tmp, 10);
|
||||
if (i <= max_value) {
|
||||
*value = i;
|
||||
} else {
|
||||
PRINT_WARN("blkt total time: write values between"
|
||||
" 0 and %d to this file!\n", max_value);
|
||||
return -EINVAL;
|
||||
}
|
||||
return count;
|
||||
}
|
||||
|
||||
static ssize_t qeth_dev_blkt_total_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct qeth_card *card = dev_get_drvdata(dev);
|
||||
|
||||
return qeth_dev_blkt_show(buf, card, card->info.blkt.time_total);
|
||||
}
|
||||
|
||||
static ssize_t qeth_dev_blkt_total_store(struct device *dev,
|
||||
struct device_attribute *attr, const char *buf, size_t count)
|
||||
{
|
||||
struct qeth_card *card = dev_get_drvdata(dev);
|
||||
|
||||
return qeth_dev_blkt_store(card, buf, count,
|
||||
&card->info.blkt.time_total, 1000);
|
||||
}
|
||||
|
||||
|
||||
|
||||
static DEVICE_ATTR(total, 0644, qeth_dev_blkt_total_show,
|
||||
qeth_dev_blkt_total_store);
|
||||
|
||||
static ssize_t qeth_dev_blkt_inter_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct qeth_card *card = dev_get_drvdata(dev);
|
||||
|
||||
return qeth_dev_blkt_show(buf, card, card->info.blkt.inter_packet);
|
||||
}
|
||||
|
||||
static ssize_t qeth_dev_blkt_inter_store(struct device *dev,
|
||||
struct device_attribute *attr, const char *buf, size_t count)
|
||||
{
|
||||
struct qeth_card *card = dev_get_drvdata(dev);
|
||||
|
||||
return qeth_dev_blkt_store(card, buf, count,
|
||||
&card->info.blkt.inter_packet, 100);
|
||||
}
|
||||
|
||||
static DEVICE_ATTR(inter, 0644, qeth_dev_blkt_inter_show,
|
||||
qeth_dev_blkt_inter_store);
|
||||
|
||||
static ssize_t qeth_dev_blkt_inter_jumbo_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct qeth_card *card = dev_get_drvdata(dev);
|
||||
|
||||
return qeth_dev_blkt_show(buf, card,
|
||||
card->info.blkt.inter_packet_jumbo);
|
||||
}
|
||||
|
||||
static ssize_t qeth_dev_blkt_inter_jumbo_store(struct device *dev,
|
||||
struct device_attribute *attr, const char *buf, size_t count)
|
||||
{
|
||||
struct qeth_card *card = dev_get_drvdata(dev);
|
||||
|
||||
return qeth_dev_blkt_store(card, buf, count,
|
||||
&card->info.blkt.inter_packet_jumbo, 100);
|
||||
}
|
||||
|
||||
static DEVICE_ATTR(inter_jumbo, 0644, qeth_dev_blkt_inter_jumbo_show,
|
||||
qeth_dev_blkt_inter_jumbo_store);
|
||||
|
||||
static struct attribute *qeth_blkt_device_attrs[] = {
|
||||
&dev_attr_total.attr,
|
||||
&dev_attr_inter.attr,
|
||||
&dev_attr_inter_jumbo.attr,
|
||||
NULL,
|
||||
};
|
||||
|
||||
static struct attribute_group qeth_device_blkt_group = {
|
||||
.name = "blkt",
|
||||
.attrs = qeth_blkt_device_attrs,
|
||||
};
|
||||
|
||||
static struct attribute *qeth_device_attrs[] = {
|
||||
&dev_attr_state.attr,
|
||||
&dev_attr_chpid.attr,
|
||||
&dev_attr_if_name.attr,
|
||||
&dev_attr_card_type.attr,
|
||||
&dev_attr_inbuf_size.attr,
|
||||
&dev_attr_portno.attr,
|
||||
&dev_attr_portname.attr,
|
||||
&dev_attr_priority_queueing.attr,
|
||||
&dev_attr_buffer_count.attr,
|
||||
&dev_attr_recover.attr,
|
||||
&dev_attr_performance_stats.attr,
|
||||
&dev_attr_layer2.attr,
|
||||
&dev_attr_large_send.attr,
|
||||
NULL,
|
||||
};
|
||||
|
||||
static struct attribute_group qeth_device_attr_group = {
|
||||
.attrs = qeth_device_attrs,
|
||||
};
|
||||
|
||||
static struct attribute *qeth_osn_device_attrs[] = {
|
||||
&dev_attr_state.attr,
|
||||
&dev_attr_chpid.attr,
|
||||
&dev_attr_if_name.attr,
|
||||
&dev_attr_card_type.attr,
|
||||
&dev_attr_buffer_count.attr,
|
||||
&dev_attr_recover.attr,
|
||||
NULL,
|
||||
};
|
||||
|
||||
static struct attribute_group qeth_osn_device_attr_group = {
|
||||
.attrs = qeth_osn_device_attrs,
|
||||
};
|
||||
|
||||
int qeth_core_create_device_attributes(struct device *dev)
|
||||
{
|
||||
int ret;
|
||||
ret = sysfs_create_group(&dev->kobj, &qeth_device_attr_group);
|
||||
if (ret)
|
||||
return ret;
|
||||
ret = sysfs_create_group(&dev->kobj, &qeth_device_blkt_group);
|
||||
if (ret)
|
||||
sysfs_remove_group(&dev->kobj, &qeth_device_attr_group);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void qeth_core_remove_device_attributes(struct device *dev)
|
||||
{
|
||||
sysfs_remove_group(&dev->kobj, &qeth_device_attr_group);
|
||||
sysfs_remove_group(&dev->kobj, &qeth_device_blkt_group);
|
||||
}
|
||||
|
||||
int qeth_core_create_osn_attributes(struct device *dev)
|
||||
{
|
||||
return sysfs_create_group(&dev->kobj, &qeth_osn_device_attr_group);
|
||||
}
|
||||
|
||||
void qeth_core_remove_osn_attributes(struct device *dev)
|
||||
{
|
||||
sysfs_remove_group(&dev->kobj, &qeth_osn_device_attr_group);
|
||||
return;
|
||||
}
|
|
@ -1,168 +0,0 @@
|
|||
/*
|
||||
* linux/drivers/s390/net/qeth_fs.h
|
||||
*
|
||||
* Linux on zSeries OSA Express and HiperSockets support.
|
||||
*
|
||||
* This header file contains definitions related to sysfs and procfs.
|
||||
*
|
||||
* Copyright 2000,2003 IBM Corporation
|
||||
* Author(s): Thomas Spatzier <tspat@de.ibm.com>
|
||||
*
|
||||
*/
|
||||
#ifndef __QETH_FS_H__
|
||||
#define __QETH_FS_H__
|
||||
|
||||
#ifdef CONFIG_PROC_FS
|
||||
extern int
|
||||
qeth_create_procfs_entries(void);
|
||||
|
||||
extern void
|
||||
qeth_remove_procfs_entries(void);
|
||||
#else
|
||||
static inline int
|
||||
qeth_create_procfs_entries(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void
|
||||
qeth_remove_procfs_entries(void)
|
||||
{
|
||||
}
|
||||
#endif /* CONFIG_PROC_FS */
|
||||
|
||||
extern int
|
||||
qeth_create_device_attributes(struct device *dev);
|
||||
|
||||
extern void
|
||||
qeth_remove_device_attributes(struct device *dev);
|
||||
|
||||
extern int
|
||||
qeth_create_device_attributes_osn(struct device *dev);
|
||||
|
||||
extern void
|
||||
qeth_remove_device_attributes_osn(struct device *dev);
|
||||
|
||||
extern int
|
||||
qeth_create_driver_attributes(void);
|
||||
|
||||
extern void
|
||||
qeth_remove_driver_attributes(void);
|
||||
|
||||
/*
|
||||
* utility functions used in qeth_proc.c and qeth_sys.c
|
||||
*/
|
||||
|
||||
static inline const char *
|
||||
qeth_get_checksum_str(struct qeth_card *card)
|
||||
{
|
||||
if (card->options.checksum_type == SW_CHECKSUMMING)
|
||||
return "sw";
|
||||
else if (card->options.checksum_type == HW_CHECKSUMMING)
|
||||
return "hw";
|
||||
else
|
||||
return "no";
|
||||
}
|
||||
|
||||
static inline const char *
|
||||
qeth_get_prioq_str(struct qeth_card *card, char *buf)
|
||||
{
|
||||
if (card->qdio.do_prio_queueing == QETH_NO_PRIO_QUEUEING)
|
||||
sprintf(buf, "always_q_%i", card->qdio.default_out_queue);
|
||||
else
|
||||
strcpy(buf, (card->qdio.do_prio_queueing ==
|
||||
QETH_PRIO_Q_ING_PREC)?
|
||||
"by_prec." : "by_ToS");
|
||||
return buf;
|
||||
}
|
||||
|
||||
static inline const char *
|
||||
qeth_get_bufsize_str(struct qeth_card *card)
|
||||
{
|
||||
if (card->qdio.in_buf_size == 16384)
|
||||
return "16k";
|
||||
else if (card->qdio.in_buf_size == 24576)
|
||||
return "24k";
|
||||
else if (card->qdio.in_buf_size == 32768)
|
||||
return "32k";
|
||||
else if (card->qdio.in_buf_size == 40960)
|
||||
return "40k";
|
||||
else
|
||||
return "64k";
|
||||
}
|
||||
|
||||
static inline const char *
|
||||
qeth_get_cardname(struct qeth_card *card)
|
||||
{
|
||||
if (card->info.guestlan) {
|
||||
switch (card->info.type) {
|
||||
case QETH_CARD_TYPE_OSAE:
|
||||
return " Guest LAN QDIO";
|
||||
case QETH_CARD_TYPE_IQD:
|
||||
return " Guest LAN Hiper";
|
||||
default:
|
||||
return " unknown";
|
||||
}
|
||||
} else {
|
||||
switch (card->info.type) {
|
||||
case QETH_CARD_TYPE_OSAE:
|
||||
return " OSD Express";
|
||||
case QETH_CARD_TYPE_IQD:
|
||||
return " HiperSockets";
|
||||
case QETH_CARD_TYPE_OSN:
|
||||
return " OSN QDIO";
|
||||
default:
|
||||
return " unknown";
|
||||
}
|
||||
}
|
||||
return " n/a";
|
||||
}
|
||||
|
||||
/* max length to be returned: 14 */
|
||||
static inline const char *
|
||||
qeth_get_cardname_short(struct qeth_card *card)
|
||||
{
|
||||
if (card->info.guestlan){
|
||||
switch (card->info.type){
|
||||
case QETH_CARD_TYPE_OSAE:
|
||||
return "GuestLAN QDIO";
|
||||
case QETH_CARD_TYPE_IQD:
|
||||
return "GuestLAN Hiper";
|
||||
default:
|
||||
return "unknown";
|
||||
}
|
||||
} else {
|
||||
switch (card->info.type) {
|
||||
case QETH_CARD_TYPE_OSAE:
|
||||
switch (card->info.link_type) {
|
||||
case QETH_LINK_TYPE_FAST_ETH:
|
||||
return "OSD_100";
|
||||
case QETH_LINK_TYPE_HSTR:
|
||||
return "HSTR";
|
||||
case QETH_LINK_TYPE_GBIT_ETH:
|
||||
return "OSD_1000";
|
||||
case QETH_LINK_TYPE_10GBIT_ETH:
|
||||
return "OSD_10GIG";
|
||||
case QETH_LINK_TYPE_LANE_ETH100:
|
||||
return "OSD_FE_LANE";
|
||||
case QETH_LINK_TYPE_LANE_TR:
|
||||
return "OSD_TR_LANE";
|
||||
case QETH_LINK_TYPE_LANE_ETH1000:
|
||||
return "OSD_GbE_LANE";
|
||||
case QETH_LINK_TYPE_LANE:
|
||||
return "OSD_ATM_LANE";
|
||||
default:
|
||||
return "OSD_Express";
|
||||
}
|
||||
case QETH_CARD_TYPE_IQD:
|
||||
return "HiperSockets";
|
||||
case QETH_CARD_TYPE_OSN:
|
||||
return "OSN";
|
||||
default:
|
||||
return "unknown";
|
||||
}
|
||||
}
|
||||
return "n/a";
|
||||
}
|
||||
|
||||
#endif /* __QETH_FS_H__ */
|
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
@ -0,0 +1,76 @@
|
|||
/*
|
||||
* drivers/s390/net/qeth_l3.h
|
||||
*
|
||||
* Copyright IBM Corp. 2007
|
||||
* Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
|
||||
* Frank Pavlic <fpavlic@de.ibm.com>,
|
||||
* Thomas Spatzier <tspat@de.ibm.com>,
|
||||
* Frank Blaschka <frank.blaschka@de.ibm.com>
|
||||
*/
|
||||
|
||||
#ifndef __QETH_L3_H__
|
||||
#define __QETH_L3_H__
|
||||
|
||||
#include "qeth_core.h"
|
||||
|
||||
#define QETH_DBF_TEXT_(name, level, text...) \
|
||||
do { \
|
||||
if (qeth_dbf_passes(qeth_dbf_##name, level)) { \
|
||||
char *dbf_txt_buf = get_cpu_var(qeth_l3_dbf_txt_buf); \
|
||||
sprintf(dbf_txt_buf, text); \
|
||||
debug_text_event(qeth_dbf_##name, level, dbf_txt_buf); \
|
||||
put_cpu_var(qeth_l3_dbf_txt_buf); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
DECLARE_PER_CPU(char[256], qeth_l3_dbf_txt_buf);
|
||||
|
||||
struct qeth_ipaddr {
|
||||
struct list_head entry;
|
||||
enum qeth_ip_types type;
|
||||
enum qeth_ipa_setdelip_flags set_flags;
|
||||
enum qeth_ipa_setdelip_flags del_flags;
|
||||
int is_multicast;
|
||||
int users;
|
||||
enum qeth_prot_versions proto;
|
||||
unsigned char mac[OSA_ADDR_LEN];
|
||||
union {
|
||||
struct {
|
||||
unsigned int addr;
|
||||
unsigned int mask;
|
||||
} a4;
|
||||
struct {
|
||||
struct in6_addr addr;
|
||||
unsigned int pfxlen;
|
||||
} a6;
|
||||
} u;
|
||||
};
|
||||
|
||||
struct qeth_ipato_entry {
|
||||
struct list_head entry;
|
||||
enum qeth_prot_versions proto;
|
||||
char addr[16];
|
||||
int mask_bits;
|
||||
};
|
||||
|
||||
|
||||
void qeth_l3_ipaddr4_to_string(const __u8 *, char *);
|
||||
int qeth_l3_string_to_ipaddr4(const char *, __u8 *);
|
||||
void qeth_l3_ipaddr6_to_string(const __u8 *, char *);
|
||||
int qeth_l3_string_to_ipaddr6(const char *, __u8 *);
|
||||
void qeth_l3_ipaddr_to_string(enum qeth_prot_versions, const __u8 *, char *);
|
||||
int qeth_l3_string_to_ipaddr(const char *, enum qeth_prot_versions, __u8 *);
|
||||
int qeth_l3_create_device_attributes(struct device *);
|
||||
void qeth_l3_remove_device_attributes(struct device *);
|
||||
int qeth_l3_setrouting_v4(struct qeth_card *);
|
||||
int qeth_l3_setrouting_v6(struct qeth_card *);
|
||||
int qeth_l3_add_ipato_entry(struct qeth_card *, struct qeth_ipato_entry *);
|
||||
void qeth_l3_del_ipato_entry(struct qeth_card *, enum qeth_prot_versions,
|
||||
u8 *, int);
|
||||
int qeth_l3_add_vipa(struct qeth_card *, enum qeth_prot_versions, const u8 *);
|
||||
void qeth_l3_del_vipa(struct qeth_card *, enum qeth_prot_versions, const u8 *);
|
||||
int qeth_l3_add_rxip(struct qeth_card *, enum qeth_prot_versions, const u8 *);
|
||||
void qeth_l3_del_rxip(struct qeth_card *card, enum qeth_prot_versions,
|
||||
const u8 *);
|
||||
|
||||
#endif /* __QETH_L3_H__ */
|
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
@ -1,269 +0,0 @@
|
|||
/*
|
||||
* linux/drivers/s390/net/qeth_mpc.c
|
||||
*
|
||||
* Linux on zSeries OSA Express and HiperSockets support
|
||||
*
|
||||
* Copyright 2000,2003 IBM Corporation
|
||||
* Author(s): Frank Pavlic <fpavlic@de.ibm.com>
|
||||
* Thomas Spatzier <tspat@de.ibm.com>
|
||||
*
|
||||
*/
|
||||
#include <asm/cio.h>
|
||||
#include "qeth_mpc.h"
|
||||
|
||||
unsigned char IDX_ACTIVATE_READ[]={
|
||||
0x00,0x00,0x80,0x00, 0x00,0x00,0x00,0x00,
|
||||
0x19,0x01,0x01,0x80, 0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00, 0x00,0x00,0xc8,0xc1,
|
||||
0xd3,0xd3,0xd6,0xd3, 0xc5,0x40,0x00,0x00,
|
||||
0x00,0x00
|
||||
};
|
||||
|
||||
unsigned char IDX_ACTIVATE_WRITE[]={
|
||||
0x00,0x00,0x80,0x00, 0x00,0x00,0x00,0x00,
|
||||
0x15,0x01,0x01,0x80, 0x00,0x00,0x00,0x00,
|
||||
0xff,0xff,0x00,0x00, 0x00,0x00,0xc8,0xc1,
|
||||
0xd3,0xd3,0xd6,0xd3, 0xc5,0x40,0x00,0x00,
|
||||
0x00,0x00
|
||||
};
|
||||
|
||||
unsigned char CM_ENABLE[]={
|
||||
0x00,0xe0,0x00,0x00, 0x00,0x00,0x00,0x01,
|
||||
0x00,0x00,0x00,0x14, 0x00,0x00,0x00,0x63,
|
||||
0x10,0x00,0x00,0x01,
|
||||
0x00,0x00,0x00,0x00,
|
||||
0x81,0x7e,0x00,0x01, 0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00, 0x00,0x24,0x00,0x23,
|
||||
0x00,0x00,0x23,0x05, 0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,
|
||||
0x01,0x00,0x00,0x23, 0x00,0x00,0x00,0x40,
|
||||
0x00,0x0c,0x41,0x02, 0x00,0x17,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,
|
||||
0x00,0x0b,0x04,0x01,
|
||||
0x7e,0x04,0x05,0x00, 0x01,0x01,0x0f,
|
||||
0x00,
|
||||
0x0c,0x04,0x02,0xff, 0xff,0xff,0xff,0xff,
|
||||
0xff,0xff,0xff
|
||||
};
|
||||
|
||||
unsigned char CM_SETUP[]={
|
||||
0x00,0xe0,0x00,0x00, 0x00,0x00,0x00,0x02,
|
||||
0x00,0x00,0x00,0x14, 0x00,0x00,0x00,0x64,
|
||||
0x10,0x00,0x00,0x01,
|
||||
0x00,0x00,0x00,0x00,
|
||||
0x81,0x7e,0x00,0x01, 0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00, 0x00,0x24,0x00,0x24,
|
||||
0x00,0x00,0x24,0x05, 0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,
|
||||
0x01,0x00,0x00,0x24, 0x00,0x00,0x00,0x40,
|
||||
0x00,0x0c,0x41,0x04, 0x00,0x18,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,
|
||||
0x00,0x09,0x04,0x04,
|
||||
0x05,0x00,0x01,0x01, 0x11,
|
||||
0x00,0x09,0x04,
|
||||
0x05,0x05,0x00,0x00, 0x00,0x00,
|
||||
0x00,0x06,
|
||||
0x04,0x06,0xc8,0x00
|
||||
};
|
||||
|
||||
unsigned char ULP_ENABLE[]={
|
||||
0x00,0xe0,0x00,0x00, 0x00,0x00,0x00,0x03,
|
||||
0x00,0x00,0x00,0x14, 0x00,0x00,0x00,0x6b,
|
||||
0x10,0x00,0x00,0x01,
|
||||
0x00,0x00,0x00,0x00,
|
||||
0x41,0x7e,0x00,0x01, 0x00,0x00,0x00,0x01,
|
||||
0x00,0x00,0x00,0x00, 0x00,0x24,0x00,0x2b,
|
||||
0x00,0x00,0x2b,0x05, 0x20,0x01,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,
|
||||
0x01,0x00,0x00,0x2b, 0x00,0x00,0x00,0x40,
|
||||
0x00,0x0c,0x41,0x02, 0x00,0x1f,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,
|
||||
0x00,0x0b,0x04,0x01,
|
||||
0x03,0x04,0x05,0x00, 0x01,0x01,0x12,
|
||||
0x00,
|
||||
0x14,0x04,0x0a,0x00, 0x20,0x00,0x00,0xff,
|
||||
0xff,0x00,0x08,0xc8, 0xe8,0xc4,0xf1,0xc7,
|
||||
0xf1,0x00,0x00
|
||||
};
|
||||
|
||||
unsigned char ULP_SETUP[]={
|
||||
0x00,0xe0,0x00,0x00, 0x00,0x00,0x00,0x04,
|
||||
0x00,0x00,0x00,0x14, 0x00,0x00,0x00,0x6c,
|
||||
0x10,0x00,0x00,0x01,
|
||||
0x00,0x00,0x00,0x00,
|
||||
0x41,0x7e,0x00,0x01, 0x00,0x00,0x00,0x02,
|
||||
0x00,0x00,0x00,0x01, 0x00,0x24,0x00,0x2c,
|
||||
0x00,0x00,0x2c,0x05, 0x20,0x01,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,
|
||||
0x01,0x00,0x00,0x2c, 0x00,0x00,0x00,0x40,
|
||||
0x00,0x0c,0x41,0x04, 0x00,0x20,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,
|
||||
0x00,0x09,0x04,0x04,
|
||||
0x05,0x00,0x01,0x01, 0x14,
|
||||
0x00,0x09,0x04,
|
||||
0x05,0x05,0x30,0x01, 0x00,0x00,
|
||||
0x00,0x06,
|
||||
0x04,0x06,0x40,0x00,
|
||||
0x00,0x08,0x04,0x0b,
|
||||
0x00,0x00,0x00,0x00
|
||||
};
|
||||
|
||||
unsigned char DM_ACT[]={
|
||||
0x00,0xe0,0x00,0x00, 0x00,0x00,0x00,0x05,
|
||||
0x00,0x00,0x00,0x14, 0x00,0x00,0x00,0x55,
|
||||
0x10,0x00,0x00,0x01,
|
||||
0x00,0x00,0x00,0x00,
|
||||
0x41,0x7e,0x00,0x01, 0x00,0x00,0x00,0x03,
|
||||
0x00,0x00,0x00,0x02, 0x00,0x24,0x00,0x15,
|
||||
0x00,0x00,0x2c,0x05, 0x20,0x01,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,
|
||||
0x01,0x00,0x00,0x15, 0x00,0x00,0x00,0x40,
|
||||
0x00,0x0c,0x43,0x60, 0x00,0x09,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,
|
||||
0x00,0x09,0x04,0x04,
|
||||
0x05,0x40,0x01,0x01, 0x00
|
||||
};
|
||||
|
||||
unsigned char IPA_PDU_HEADER[]={
|
||||
0x00,0xe0,0x00,0x00, 0x77,0x77,0x77,0x77,
|
||||
0x00,0x00,0x00,0x14, 0x00,0x00,
|
||||
(IPA_PDU_HEADER_SIZE+sizeof(struct qeth_ipa_cmd))/256,
|
||||
(IPA_PDU_HEADER_SIZE+sizeof(struct qeth_ipa_cmd))%256,
|
||||
0x10,0x00,0x00,0x01, 0x00,0x00,0x00,0x00,
|
||||
0xc1,0x03,0x00,0x01, 0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00, 0x00,0x24,
|
||||
sizeof(struct qeth_ipa_cmd)/256,
|
||||
sizeof(struct qeth_ipa_cmd)%256,
|
||||
0x00,
|
||||
sizeof(struct qeth_ipa_cmd)/256,
|
||||
sizeof(struct qeth_ipa_cmd)%256,
|
||||
0x05,
|
||||
0x77,0x77,0x77,0x77,
|
||||
0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,
|
||||
0x01,0x00,
|
||||
sizeof(struct qeth_ipa_cmd)/256,
|
||||
sizeof(struct qeth_ipa_cmd)%256,
|
||||
0x00,0x00,0x00,0x40,
|
||||
};
|
||||
|
||||
unsigned char WRITE_CCW[]={
|
||||
0x01,CCW_FLAG_SLI,0,0,
|
||||
0,0,0,0
|
||||
};
|
||||
|
||||
unsigned char READ_CCW[]={
|
||||
0x02,CCW_FLAG_SLI,0,0,
|
||||
0,0,0,0
|
||||
};
|
||||
|
||||
|
||||
struct ipa_rc_msg {
|
||||
enum qeth_ipa_return_codes rc;
|
||||
char *msg;
|
||||
};
|
||||
|
||||
static struct ipa_rc_msg qeth_ipa_rc_msg[] = {
|
||||
{IPA_RC_SUCCESS, "success"},
|
||||
{IPA_RC_NOTSUPP, "Command not supported"},
|
||||
{IPA_RC_IP_TABLE_FULL, "Add Addr IP Table Full - ipv6"},
|
||||
{IPA_RC_UNKNOWN_ERROR, "IPA command failed - reason unknown"},
|
||||
{IPA_RC_UNSUPPORTED_COMMAND, "Command not supported"},
|
||||
{IPA_RC_DUP_IPV6_REMOTE,"ipv6 address already registered remote"},
|
||||
{IPA_RC_DUP_IPV6_HOME, "ipv6 address already registered"},
|
||||
{IPA_RC_UNREGISTERED_ADDR, "Address not registered"},
|
||||
{IPA_RC_NO_ID_AVAILABLE, "No identifiers available"},
|
||||
{IPA_RC_ID_NOT_FOUND, "Identifier not found"},
|
||||
{IPA_RC_INVALID_IP_VERSION, "IP version incorrect"},
|
||||
{IPA_RC_LAN_FRAME_MISMATCH, "LAN and frame mismatch"},
|
||||
{IPA_RC_L2_UNSUPPORTED_CMD, "Unsupported layer 2 command"},
|
||||
{IPA_RC_L2_DUP_MAC, "Duplicate MAC address"},
|
||||
{IPA_RC_L2_ADDR_TABLE_FULL, "Layer2 address table full"},
|
||||
{IPA_RC_L2_DUP_LAYER3_MAC, "Duplicate with layer 3 MAC"},
|
||||
{IPA_RC_L2_GMAC_NOT_FOUND, "GMAC not found"},
|
||||
{IPA_RC_L2_MAC_NOT_FOUND, "L2 mac address not found"},
|
||||
{IPA_RC_L2_INVALID_VLAN_ID, "L2 invalid vlan id"},
|
||||
{IPA_RC_L2_DUP_VLAN_ID, "L2 duplicate vlan id"},
|
||||
{IPA_RC_L2_VLAN_ID_NOT_FOUND, "L2 vlan id not found"},
|
||||
{IPA_RC_DATA_MISMATCH, "Data field mismatch (v4/v6 mixed)"},
|
||||
{IPA_RC_INVALID_MTU_SIZE, "Invalid MTU size"},
|
||||
{IPA_RC_INVALID_LANTYPE, "Invalid LAN type"},
|
||||
{IPA_RC_INVALID_LANNUM, "Invalid LAN num"},
|
||||
{IPA_RC_DUPLICATE_IP_ADDRESS, "Address already registered"},
|
||||
{IPA_RC_IP_ADDR_TABLE_FULL, "IP address table full"},
|
||||
{IPA_RC_LAN_PORT_STATE_ERROR, "LAN port state error"},
|
||||
{IPA_RC_SETIP_NO_STARTLAN, "Setip no startlan received"},
|
||||
{IPA_RC_SETIP_ALREADY_RECEIVED, "Setip already received"},
|
||||
{IPA_RC_IP_ADDR_ALREADY_USED, "IP address already in use on LAN"},
|
||||
{IPA_RC_MULTICAST_FULL, "No task available, multicast full"},
|
||||
{IPA_RC_SETIP_INVALID_VERSION, "SETIP invalid IP version"},
|
||||
{IPA_RC_UNSUPPORTED_SUBCMD, "Unsupported assist subcommand"},
|
||||
{IPA_RC_ARP_ASSIST_NO_ENABLE, "Only partial success, no enable"},
|
||||
{IPA_RC_PRIMARY_ALREADY_DEFINED,"Primary already defined"},
|
||||
{IPA_RC_SECOND_ALREADY_DEFINED, "Secondary already defined"},
|
||||
{IPA_RC_INVALID_SETRTG_INDICATOR,"Invalid SETRTG indicator"},
|
||||
{IPA_RC_MC_ADDR_ALREADY_DEFINED,"Multicast address already defined"},
|
||||
{IPA_RC_LAN_OFFLINE, "STRTLAN_LAN_DISABLED - LAN offline"},
|
||||
{IPA_RC_INVALID_IP_VERSION2, "Invalid IP version"},
|
||||
{IPA_RC_FFFF, "Unknown Error"}
|
||||
};
|
||||
|
||||
|
||||
|
||||
char *
|
||||
qeth_get_ipa_msg(enum qeth_ipa_return_codes rc)
|
||||
{
|
||||
int x = 0;
|
||||
qeth_ipa_rc_msg[sizeof(qeth_ipa_rc_msg) /
|
||||
sizeof(struct ipa_rc_msg) - 1].rc = rc;
|
||||
while(qeth_ipa_rc_msg[x].rc != rc)
|
||||
x++;
|
||||
return qeth_ipa_rc_msg[x].msg;
|
||||
}
|
||||
|
||||
|
||||
struct ipa_cmd_names {
|
||||
enum qeth_ipa_cmds cmd;
|
||||
char *name;
|
||||
};
|
||||
|
||||
static struct ipa_cmd_names qeth_ipa_cmd_names[] = {
|
||||
{IPA_CMD_STARTLAN, "startlan"},
|
||||
{IPA_CMD_STOPLAN, "stoplan"},
|
||||
{IPA_CMD_SETVMAC, "setvmac"},
|
||||
{IPA_CMD_DELVMAC, "delvmca"},
|
||||
{IPA_CMD_SETGMAC, "setgmac"},
|
||||
{IPA_CMD_DELGMAC, "delgmac"},
|
||||
{IPA_CMD_SETVLAN, "setvlan"},
|
||||
{IPA_CMD_DELVLAN, "delvlan"},
|
||||
{IPA_CMD_SETCCID, "setccid"},
|
||||
{IPA_CMD_DELCCID, "delccid"},
|
||||
{IPA_CMD_MODCCID, "setip"},
|
||||
{IPA_CMD_SETIP, "setip"},
|
||||
{IPA_CMD_QIPASSIST, "qipassist"},
|
||||
{IPA_CMD_SETASSPARMS, "setassparms"},
|
||||
{IPA_CMD_SETIPM, "setipm"},
|
||||
{IPA_CMD_DELIPM, "delipm"},
|
||||
{IPA_CMD_SETRTG, "setrtg"},
|
||||
{IPA_CMD_DELIP, "delip"},
|
||||
{IPA_CMD_SETADAPTERPARMS, "setadapterparms"},
|
||||
{IPA_CMD_SET_DIAG_ASS, "set_diag_ass"},
|
||||
{IPA_CMD_CREATE_ADDR, "create_addr"},
|
||||
{IPA_CMD_DESTROY_ADDR, "destroy_addr"},
|
||||
{IPA_CMD_REGISTER_LOCAL_ADDR, "register_local_addr"},
|
||||
{IPA_CMD_UNREGISTER_LOCAL_ADDR, "unregister_local_addr"},
|
||||
{IPA_CMD_UNKNOWN, "unknown"},
|
||||
};
|
||||
|
||||
char *
|
||||
qeth_get_ipa_cmd_name(enum qeth_ipa_cmds cmd)
|
||||
{
|
||||
int x = 0;
|
||||
qeth_ipa_cmd_names[
|
||||
sizeof(qeth_ipa_cmd_names)/
|
||||
sizeof(struct ipa_cmd_names)-1].cmd = cmd;
|
||||
while(qeth_ipa_cmd_names[x].cmd != cmd)
|
||||
x++;
|
||||
return qeth_ipa_cmd_names[x].name;
|
||||
}
|
||||
|
||||
|
|
@ -1,316 +0,0 @@
|
|||
/*
|
||||
*
|
||||
* linux/drivers/s390/net/qeth_fs.c
|
||||
*
|
||||
* Linux on zSeries OSA Express and HiperSockets support
|
||||
* This file contains code related to procfs.
|
||||
*
|
||||
* Copyright 2000,2003 IBM Corporation
|
||||
*
|
||||
* Author(s): Thomas Spatzier <tspat@de.ibm.com>
|
||||
*
|
||||
*/
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/proc_fs.h>
|
||||
#include <linux/seq_file.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/rwsem.h>
|
||||
|
||||
#include "qeth.h"
|
||||
#include "qeth_mpc.h"
|
||||
#include "qeth_fs.h"
|
||||
|
||||
/***** /proc/qeth *****/
|
||||
#define QETH_PROCFILE_NAME "qeth"
|
||||
static struct proc_dir_entry *qeth_procfile;
|
||||
|
||||
static int
|
||||
qeth_procfile_seq_match(struct device *dev, void *data)
|
||||
{
|
||||
return(dev ? 1 : 0);
|
||||
}
|
||||
|
||||
static void *
|
||||
qeth_procfile_seq_start(struct seq_file *s, loff_t *offset)
|
||||
{
|
||||
struct device *dev = NULL;
|
||||
loff_t nr = 0;
|
||||
|
||||
if (*offset == 0)
|
||||
return SEQ_START_TOKEN;
|
||||
while (1) {
|
||||
dev = driver_find_device(&qeth_ccwgroup_driver.driver, dev,
|
||||
NULL, qeth_procfile_seq_match);
|
||||
if (++nr == *offset)
|
||||
break;
|
||||
put_device(dev);
|
||||
}
|
||||
return dev;
|
||||
}
|
||||
|
||||
static void
|
||||
qeth_procfile_seq_stop(struct seq_file *s, void* it)
|
||||
{
|
||||
}
|
||||
|
||||
static void *
|
||||
qeth_procfile_seq_next(struct seq_file *s, void *it, loff_t *offset)
|
||||
{
|
||||
struct device *prev, *next;
|
||||
|
||||
if (it == SEQ_START_TOKEN)
|
||||
prev = NULL;
|
||||
else
|
||||
prev = (struct device *) it;
|
||||
next = driver_find_device(&qeth_ccwgroup_driver.driver,
|
||||
prev, NULL, qeth_procfile_seq_match);
|
||||
(*offset)++;
|
||||
return (void *) next;
|
||||
}
|
||||
|
||||
static inline const char *
|
||||
qeth_get_router_str(struct qeth_card *card, int ipv)
|
||||
{
|
||||
enum qeth_routing_types routing_type = NO_ROUTER;
|
||||
|
||||
if (ipv == 4) {
|
||||
routing_type = card->options.route4.type;
|
||||
} else {
|
||||
#ifdef CONFIG_QETH_IPV6
|
||||
routing_type = card->options.route6.type;
|
||||
#else
|
||||
return "n/a";
|
||||
#endif /* CONFIG_QETH_IPV6 */
|
||||
}
|
||||
|
||||
switch (routing_type){
|
||||
case PRIMARY_ROUTER:
|
||||
return "pri";
|
||||
case SECONDARY_ROUTER:
|
||||
return "sec";
|
||||
case MULTICAST_ROUTER:
|
||||
if (card->info.broadcast_capable == QETH_BROADCAST_WITHOUT_ECHO)
|
||||
return "mc+";
|
||||
return "mc";
|
||||
case PRIMARY_CONNECTOR:
|
||||
if (card->info.broadcast_capable == QETH_BROADCAST_WITHOUT_ECHO)
|
||||
return "p+c";
|
||||
return "p.c";
|
||||
case SECONDARY_CONNECTOR:
|
||||
if (card->info.broadcast_capable == QETH_BROADCAST_WITHOUT_ECHO)
|
||||
return "s+c";
|
||||
return "s.c";
|
||||
default: /* NO_ROUTER */
|
||||
return "no";
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
qeth_procfile_seq_show(struct seq_file *s, void *it)
|
||||
{
|
||||
struct device *device;
|
||||
struct qeth_card *card;
|
||||
char tmp[12]; /* for qeth_get_prioq_str */
|
||||
|
||||
if (it == SEQ_START_TOKEN){
|
||||
seq_printf(s, "devices CHPID interface "
|
||||
"cardtype port chksum prio-q'ing rtr4 "
|
||||
"rtr6 fsz cnt\n");
|
||||
seq_printf(s, "-------------------------- ----- ---------- "
|
||||
"-------------- ---- ------ ---------- ---- "
|
||||
"---- ----- -----\n");
|
||||
} else {
|
||||
device = (struct device *) it;
|
||||
card = device->driver_data;
|
||||
seq_printf(s, "%s/%s/%s x%02X %-10s %-14s %-4i ",
|
||||
CARD_RDEV_ID(card),
|
||||
CARD_WDEV_ID(card),
|
||||
CARD_DDEV_ID(card),
|
||||
card->info.chpid,
|
||||
QETH_CARD_IFNAME(card),
|
||||
qeth_get_cardname_short(card),
|
||||
card->info.portno);
|
||||
if (card->lan_online)
|
||||
seq_printf(s, "%-6s %-10s %-4s %-4s %-5s %-5i\n",
|
||||
qeth_get_checksum_str(card),
|
||||
qeth_get_prioq_str(card, tmp),
|
||||
qeth_get_router_str(card, 4),
|
||||
qeth_get_router_str(card, 6),
|
||||
qeth_get_bufsize_str(card),
|
||||
card->qdio.in_buf_pool.buf_count);
|
||||
else
|
||||
seq_printf(s, " +++ LAN OFFLINE +++\n");
|
||||
put_device(device);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct seq_operations qeth_procfile_seq_ops = {
|
||||
.start = qeth_procfile_seq_start,
|
||||
.stop = qeth_procfile_seq_stop,
|
||||
.next = qeth_procfile_seq_next,
|
||||
.show = qeth_procfile_seq_show,
|
||||
};
|
||||
|
||||
static int
|
||||
qeth_procfile_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
return seq_open(file, &qeth_procfile_seq_ops);
|
||||
}
|
||||
|
||||
static const struct file_operations qeth_procfile_fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.open = qeth_procfile_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = seq_release,
|
||||
};
|
||||
|
||||
/***** /proc/qeth_perf *****/
|
||||
#define QETH_PERF_PROCFILE_NAME "qeth_perf"
|
||||
static struct proc_dir_entry *qeth_perf_procfile;
|
||||
|
||||
static int
|
||||
qeth_perf_procfile_seq_show(struct seq_file *s, void *it)
|
||||
{
|
||||
struct device *device;
|
||||
struct qeth_card *card;
|
||||
|
||||
|
||||
if (it == SEQ_START_TOKEN)
|
||||
return 0;
|
||||
|
||||
device = (struct device *) it;
|
||||
card = device->driver_data;
|
||||
seq_printf(s, "For card with devnos %s/%s/%s (%s):\n",
|
||||
CARD_RDEV_ID(card),
|
||||
CARD_WDEV_ID(card),
|
||||
CARD_DDEV_ID(card),
|
||||
QETH_CARD_IFNAME(card)
|
||||
);
|
||||
if (!card->options.performance_stats)
|
||||
seq_printf(s, "Performance statistics are deactivated.\n");
|
||||
seq_printf(s, " Skb's/buffers received : %lu/%u\n"
|
||||
" Skb's/buffers sent : %lu/%u\n\n",
|
||||
card->stats.rx_packets -
|
||||
card->perf_stats.initial_rx_packets,
|
||||
card->perf_stats.bufs_rec,
|
||||
card->stats.tx_packets -
|
||||
card->perf_stats.initial_tx_packets,
|
||||
card->perf_stats.bufs_sent
|
||||
);
|
||||
seq_printf(s, " Skb's/buffers sent without packing : %lu/%u\n"
|
||||
" Skb's/buffers sent with packing : %u/%u\n\n",
|
||||
card->stats.tx_packets - card->perf_stats.initial_tx_packets
|
||||
- card->perf_stats.skbs_sent_pack,
|
||||
card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack,
|
||||
card->perf_stats.skbs_sent_pack,
|
||||
card->perf_stats.bufs_sent_pack
|
||||
);
|
||||
seq_printf(s, " Skbs sent in SG mode : %u\n"
|
||||
" Skb fragments sent in SG mode : %u\n\n",
|
||||
card->perf_stats.sg_skbs_sent,
|
||||
card->perf_stats.sg_frags_sent);
|
||||
seq_printf(s, " Skbs received in SG mode : %u\n"
|
||||
" Skb fragments received in SG mode : %u\n"
|
||||
" Page allocations for rx SG mode : %u\n\n",
|
||||
card->perf_stats.sg_skbs_rx,
|
||||
card->perf_stats.sg_frags_rx,
|
||||
card->perf_stats.sg_alloc_page_rx);
|
||||
seq_printf(s, " large_send tx (in Kbytes) : %u\n"
|
||||
" large_send count : %u\n\n",
|
||||
card->perf_stats.large_send_bytes >> 10,
|
||||
card->perf_stats.large_send_cnt);
|
||||
seq_printf(s, " Packing state changes no pkg.->packing : %u/%u\n"
|
||||
" Watermarks L/H : %i/%i\n"
|
||||
" Current buffer usage (outbound q's) : "
|
||||
"%i/%i/%i/%i\n\n",
|
||||
card->perf_stats.sc_dp_p, card->perf_stats.sc_p_dp,
|
||||
QETH_LOW_WATERMARK_PACK, QETH_HIGH_WATERMARK_PACK,
|
||||
atomic_read(&card->qdio.out_qs[0]->used_buffers),
|
||||
(card->qdio.no_out_queues > 1)?
|
||||
atomic_read(&card->qdio.out_qs[1]->used_buffers)
|
||||
: 0,
|
||||
(card->qdio.no_out_queues > 2)?
|
||||
atomic_read(&card->qdio.out_qs[2]->used_buffers)
|
||||
: 0,
|
||||
(card->qdio.no_out_queues > 3)?
|
||||
atomic_read(&card->qdio.out_qs[3]->used_buffers)
|
||||
: 0
|
||||
);
|
||||
seq_printf(s, " Inbound handler time (in us) : %u\n"
|
||||
" Inbound handler count : %u\n"
|
||||
" Inbound do_QDIO time (in us) : %u\n"
|
||||
" Inbound do_QDIO count : %u\n\n"
|
||||
" Outbound handler time (in us) : %u\n"
|
||||
" Outbound handler count : %u\n\n"
|
||||
" Outbound time (in us, incl QDIO) : %u\n"
|
||||
" Outbound count : %u\n"
|
||||
" Outbound do_QDIO time (in us) : %u\n"
|
||||
" Outbound do_QDIO count : %u\n\n",
|
||||
card->perf_stats.inbound_time,
|
||||
card->perf_stats.inbound_cnt,
|
||||
card->perf_stats.inbound_do_qdio_time,
|
||||
card->perf_stats.inbound_do_qdio_cnt,
|
||||
card->perf_stats.outbound_handler_time,
|
||||
card->perf_stats.outbound_handler_cnt,
|
||||
card->perf_stats.outbound_time,
|
||||
card->perf_stats.outbound_cnt,
|
||||
card->perf_stats.outbound_do_qdio_time,
|
||||
card->perf_stats.outbound_do_qdio_cnt
|
||||
);
|
||||
put_device(device);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct seq_operations qeth_perf_procfile_seq_ops = {
|
||||
.start = qeth_procfile_seq_start,
|
||||
.stop = qeth_procfile_seq_stop,
|
||||
.next = qeth_procfile_seq_next,
|
||||
.show = qeth_perf_procfile_seq_show,
|
||||
};
|
||||
|
||||
static int
|
||||
qeth_perf_procfile_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
return seq_open(file, &qeth_perf_procfile_seq_ops);
|
||||
}
|
||||
|
||||
static const struct file_operations qeth_perf_procfile_fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.open = qeth_perf_procfile_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = seq_release,
|
||||
};
|
||||
|
||||
int __init
|
||||
qeth_create_procfs_entries(void)
|
||||
{
|
||||
qeth_procfile = create_proc_entry(QETH_PROCFILE_NAME,
|
||||
S_IFREG | 0444, NULL);
|
||||
if (qeth_procfile)
|
||||
qeth_procfile->proc_fops = &qeth_procfile_fops;
|
||||
|
||||
qeth_perf_procfile = create_proc_entry(QETH_PERF_PROCFILE_NAME,
|
||||
S_IFREG | 0444, NULL);
|
||||
if (qeth_perf_procfile)
|
||||
qeth_perf_procfile->proc_fops = &qeth_perf_procfile_fops;
|
||||
|
||||
if (qeth_procfile &&
|
||||
qeth_perf_procfile)
|
||||
return 0;
|
||||
else
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
void __exit
|
||||
qeth_remove_procfs_entries(void)
|
||||
{
|
||||
if (qeth_procfile)
|
||||
remove_proc_entry(QETH_PROCFILE_NAME, NULL);
|
||||
if (qeth_perf_procfile)
|
||||
remove_proc_entry(QETH_PERF_PROCFILE_NAME, NULL);
|
||||
}
|
||||
|
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