Documentation: fpga: dfl: add descriptions for virtualization and new interfaces.
This patch adds virtualization support description for DFL based FPGA devices (based on PCIe SRIOV), and introductions to new interfaces added by new dfl private feature drivers. [mdf@kernel.org: Fixed up to make it work with new reStructuredText docs] Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Acked-by: Alan Tull <atull@kernel.org> Signed-off-by: Moritz Fischer <mdf@kernel.org>
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Wu Hao
Moritz Fischer
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cb3c2c47e3
Коммит
77a0ef488d
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@ -87,6 +87,8 @@ The following functions are exposed through ioctls:
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- Get driver API version (DFL_FPGA_GET_API_VERSION)
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- Check for extensions (DFL_FPGA_CHECK_EXTENSION)
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- Program bitstream (DFL_FPGA_FME_PORT_PR)
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- Assign port to PF (DFL_FPGA_FME_PORT_ASSIGN)
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- Release port from PF (DFL_FPGA_FME_PORT_RELEASE)
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More functions are exposed through sysfs
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(/sys/class/fpga_region/regionX/dfl-fme.n/):
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@ -102,6 +104,10 @@ More functions are exposed through sysfs
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one FPGA device may have more than one port, this sysfs interface indicates
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how many ports the FPGA device has.
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Global error reporting management (errors/)
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error reporting sysfs interfaces allow user to read errors detected by the
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hardware, and clear the logged errors.
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FIU - PORT
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==========
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@ -143,6 +149,10 @@ More functions are exposed through sysfs:
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Read Accelerator GUID (afu_id)
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afu_id indicates which PR bitstream is programmed to this AFU.
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Error reporting (errors/)
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error reporting sysfs interfaces allow user to read port/afu errors
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detected by the hardware, and clear the logged errors.
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DFL Framework Overview
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======================
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@ -218,6 +228,101 @@ the compat_id exposed by the target FPGA region. This check is usually done by
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userspace before calling the reconfiguration IOCTL.
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FPGA virtualization - PCIe SRIOV
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================================
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This section describes the virtualization support on DFL based FPGA device to
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enable accessing an accelerator from applications running in a virtual machine
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(VM). This section only describes the PCIe based FPGA device with SRIOV support.
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Features supported by the particular FPGA device are exposed through Device
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Feature Lists, as illustrated below:
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::
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+-------------------------------+ +-------------+
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| PF | | VF |
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+-------------------------------+ +-------------+
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^ ^ ^ ^
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| | | |
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+-----|------------|---------|--------------|-------+
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| | | | | |
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| +-----+ +-------+ +-------+ +-------+ |
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| | FME | | Port0 | | Port1 | | Port2 | |
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| +-----+ +-------+ +-------+ +-------+ |
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| ^ ^ ^ |
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| | | | |
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| +-------+ +------+ +-------+ |
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| | AFU | | AFU | | AFU | |
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| +-------+ +------+ +-------+ |
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| |
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| DFL based FPGA PCIe Device |
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+---------------------------------------------------+
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FME is always accessed through the physical function (PF).
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Ports (and related AFUs) are accessed via PF by default, but could be exposed
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through virtual function (VF) devices via PCIe SRIOV. Each VF only contains
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1 Port and 1 AFU for isolation. Users could assign individual VFs (accelerators)
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created via PCIe SRIOV interface, to virtual machines.
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The driver organization in virtualization case is illustrated below:
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::
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+-------++------++------+ |
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| FME || FME || FME | |
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| FPGA || FPGA || FPGA | |
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|Manager||Bridge||Region| |
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+-------++------++------+ |
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+-----------------------+ +--------+ | +--------+
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| FME | | AFU | | | AFU |
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| Module | | Module | | | Module |
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+-----------------------+ +--------+ | +--------+
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+-----------------------+ | +-----------------------+
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| FPGA Container Device | | | FPGA Container Device |
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| (FPGA Base Region) | | | (FPGA Base Region) |
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+-----------------------+ | +-----------------------+
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+------------------+ | +------------------+
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| FPGA PCIE Module | | Virtual | FPGA PCIE Module |
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+------------------+ Host | Machine +------------------+
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-------------------------------------- | ------------------------------
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+---------------+ | +---------------+
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| PCI PF Device | | | PCI VF Device |
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+---------------+ | +---------------+
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FPGA PCIe device driver is always loaded first once a FPGA PCIe PF or VF device
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is detected. It:
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* Finishes enumeration on both FPGA PCIe PF and VF device using common
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interfaces from DFL framework.
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* Supports SRIOV.
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The FME device driver plays a management role in this driver architecture, it
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provides ioctls to release Port from PF and assign Port to PF. After release
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a port from PF, then it's safe to expose this port through a VF via PCIe SRIOV
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sysfs interface.
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To enable accessing an accelerator from applications running in a VM, the
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respective AFU's port needs to be assigned to a VF using the following steps:
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#. The PF owns all AFU ports by default. Any port that needs to be
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reassigned to a VF must first be released through the
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DFL_FPGA_FME_PORT_RELEASE ioctl on the FME device.
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#. Once N ports are released from PF, then user can use command below
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to enable SRIOV and VFs. Each VF owns only one Port with AFU.
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::
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echo N > $PCI_DEVICE_PATH/sriov_numvfs
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#. Pass through the VFs to VMs
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#. The AFU under VF is accessible from applications in VM (using the
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same driver inside the VF).
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Note that an FME can't be assigned to a VF, thus PR and other management
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functions are only available via the PF.
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Device enumeration
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==================
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This section introduces how applications enumerate the fpga device from
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