ARM: imx6q: add clocks for gpmi-nand
Add clocks for gpmi-nand. Signed-off-by: Huang Shijie <shijie8@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Коммит
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@ -147,7 +147,7 @@ enum mx6q_clks {
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esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb,
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hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2,
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ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi,
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mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4,
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mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch,
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gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
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ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
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usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
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@ -357,6 +357,7 @@ int __init mx6q_clocks_init(void)
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clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28);
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clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30);
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clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
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clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
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clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16);
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clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
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clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20);
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@ -395,6 +396,11 @@ int __init mx6q_clocks_init(void)
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clk_register_clkdev(clk[twd], NULL, "smp_twd");
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clk_register_clkdev(clk[usboh3], NULL, "usboh3");
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clk_register_clkdev(clk[apbh_dma], NULL, "110000.dma-apbh");
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clk_register_clkdev(clk[per1_bch], "per1_bch", "112000.gpmi-nand");
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clk_register_clkdev(clk[gpmi_bch_apb], "gpmi_bch_apb", "112000.gpmi-nand");
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clk_register_clkdev(clk[gpmi_bch], "gpmi_bch", "112000.gpmi-nand");
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clk_register_clkdev(clk[gpmi_apb], "gpmi_apb", "112000.gpmi-nand");
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clk_register_clkdev(clk[gpmi_io], "gpmi_io", "112000.gpmi-nand");
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clk_register_clkdev(clk[uart_serial], "per", "2020000.serial");
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clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial");
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clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial");
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