Merge branch 'topic/dirn_remove' into for-linus
This commit is contained in:
Vinod Koul
Коммит
77ee1aacdd
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@ -335,6 +335,7 @@ struct sdma_desc {
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* @sdma: pointer to the SDMA engine for this channel
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* @channel: the channel number, matches dmaengine chan_id + 1
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* @direction: transfer type. Needed for setting SDMA script
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* @slave_config Slave configuration
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* @peripheral_type: Peripheral type. Needed for setting SDMA script
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* @event_id0: aka dma request line
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* @event_id1: for channels that use 2 events
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@ -362,6 +363,7 @@ struct sdma_channel {
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struct sdma_engine *sdma;
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unsigned int channel;
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enum dma_transfer_direction direction;
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struct dma_slave_config slave_config;
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enum sdma_peripheral_type peripheral_type;
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unsigned int event_id0;
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unsigned int event_id1;
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@ -440,6 +442,10 @@ struct sdma_engine {
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struct sdma_buffer_descriptor *bd0;
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};
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static int sdma_config_write(struct dma_chan *chan,
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struct dma_slave_config *dmaengine_cfg,
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enum dma_transfer_direction direction);
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static struct sdma_driver_data sdma_imx31 = {
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.chnenbl0 = SDMA_CHNENBL0_IMX31,
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.num_events = 32,
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@ -1104,18 +1110,6 @@ static int sdma_config_channel(struct dma_chan *chan)
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sdmac->shp_addr = 0;
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sdmac->per_addr = 0;
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if (sdmac->event_id0) {
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if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
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return -EINVAL;
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sdma_event_enable(sdmac, sdmac->event_id0);
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}
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if (sdmac->event_id1) {
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if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events)
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return -EINVAL;
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sdma_event_enable(sdmac, sdmac->event_id1);
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}
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switch (sdmac->peripheral_type) {
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case IMX_DMATYPE_DSP:
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sdma_config_ownership(sdmac, false, true, true);
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@ -1415,6 +1409,8 @@ static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
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struct scatterlist *sg;
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struct sdma_desc *desc;
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sdma_config_write(chan, &sdmac->slave_config, direction);
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desc = sdma_transfer_init(sdmac, direction, sg_len);
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if (!desc)
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goto err_out;
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@ -1499,6 +1495,8 @@ static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
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dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
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sdma_config_write(chan, &sdmac->slave_config, direction);
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desc = sdma_transfer_init(sdmac, direction, num_periods);
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if (!desc)
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goto err_out;
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@ -1554,17 +1552,18 @@ err_out:
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return NULL;
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}
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static int sdma_config(struct dma_chan *chan,
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struct dma_slave_config *dmaengine_cfg)
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static int sdma_config_write(struct dma_chan *chan,
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struct dma_slave_config *dmaengine_cfg,
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enum dma_transfer_direction direction)
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{
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struct sdma_channel *sdmac = to_sdma_chan(chan);
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if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
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if (direction == DMA_DEV_TO_MEM) {
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sdmac->per_address = dmaengine_cfg->src_addr;
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sdmac->watermark_level = dmaengine_cfg->src_maxburst *
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dmaengine_cfg->src_addr_width;
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sdmac->word_size = dmaengine_cfg->src_addr_width;
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} else if (dmaengine_cfg->direction == DMA_DEV_TO_DEV) {
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} else if (direction == DMA_DEV_TO_DEV) {
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sdmac->per_address2 = dmaengine_cfg->src_addr;
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sdmac->per_address = dmaengine_cfg->dst_addr;
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sdmac->watermark_level = dmaengine_cfg->src_maxburst &
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@ -1578,10 +1577,33 @@ static int sdma_config(struct dma_chan *chan,
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dmaengine_cfg->dst_addr_width;
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sdmac->word_size = dmaengine_cfg->dst_addr_width;
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}
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sdmac->direction = dmaengine_cfg->direction;
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sdmac->direction = direction;
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return sdma_config_channel(chan);
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}
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static int sdma_config(struct dma_chan *chan,
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struct dma_slave_config *dmaengine_cfg)
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{
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struct sdma_channel *sdmac = to_sdma_chan(chan);
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memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg));
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/* Set ENBLn earlier to make sure dma request triggered after that */
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if (sdmac->event_id0) {
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if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
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return -EINVAL;
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sdma_event_enable(sdmac, sdmac->event_id0);
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}
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if (sdmac->event_id1) {
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if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events)
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return -EINVAL;
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sdma_event_enable(sdmac, sdmac->event_id1);
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}
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return 0;
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}
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static enum dma_status sdma_tx_status(struct dma_chan *chan,
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dma_cookie_t cookie,
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struct dma_tx_state *txstate)
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@ -96,6 +96,7 @@ struct mmp_pdma_chan {
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struct dma_async_tx_descriptor desc;
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struct mmp_pdma_phy *phy;
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enum dma_transfer_direction dir;
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struct dma_slave_config slave_config;
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struct mmp_pdma_desc_sw *cyclic_first; /* first desc_sw if channel
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* is in cyclic mode */
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@ -140,6 +141,10 @@ struct mmp_pdma_device {
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#define to_mmp_pdma_dev(dmadev) \
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container_of(dmadev, struct mmp_pdma_device, device)
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static int mmp_pdma_config_write(struct dma_chan *dchan,
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struct dma_slave_config *cfg,
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enum dma_transfer_direction direction);
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static void set_desc(struct mmp_pdma_phy *phy, dma_addr_t addr)
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{
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u32 reg = (phy->idx << 4) + DDADR;
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@ -537,6 +542,8 @@ mmp_pdma_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
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chan->byte_align = false;
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mmp_pdma_config_write(dchan, &chan->slave_config, dir);
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for_each_sg(sgl, sg, sg_len, i) {
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addr = sg_dma_address(sg);
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avail = sg_dma_len(sgl);
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@ -619,6 +626,7 @@ mmp_pdma_prep_dma_cyclic(struct dma_chan *dchan,
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return NULL;
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chan = to_mmp_pdma_chan(dchan);
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mmp_pdma_config_write(dchan, &chan->slave_config, direction);
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switch (direction) {
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case DMA_MEM_TO_DEV:
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@ -684,8 +692,9 @@ fail:
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return NULL;
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}
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static int mmp_pdma_config(struct dma_chan *dchan,
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struct dma_slave_config *cfg)
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static int mmp_pdma_config_write(struct dma_chan *dchan,
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struct dma_slave_config *cfg,
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enum dma_transfer_direction direction)
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{
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struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
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u32 maxburst = 0, addr = 0;
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@ -694,12 +703,12 @@ static int mmp_pdma_config(struct dma_chan *dchan,
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if (!dchan)
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return -EINVAL;
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if (cfg->direction == DMA_DEV_TO_MEM) {
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if (direction == DMA_DEV_TO_MEM) {
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chan->dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC;
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maxburst = cfg->src_maxburst;
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width = cfg->src_addr_width;
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addr = cfg->src_addr;
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} else if (cfg->direction == DMA_MEM_TO_DEV) {
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} else if (direction == DMA_MEM_TO_DEV) {
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chan->dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG;
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maxburst = cfg->dst_maxburst;
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width = cfg->dst_addr_width;
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@ -720,7 +729,7 @@ static int mmp_pdma_config(struct dma_chan *dchan,
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else if (maxburst == 32)
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chan->dcmd |= DCMD_BURST32;
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chan->dir = cfg->direction;
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chan->dir = direction;
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chan->dev_addr = addr;
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/* FIXME: drivers should be ported over to use the filter
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* function. Once that's done, the following two lines can
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@ -732,6 +741,15 @@ static int mmp_pdma_config(struct dma_chan *dchan,
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return 0;
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}
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static int mmp_pdma_config(struct dma_chan *dchan,
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struct dma_slave_config *cfg)
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{
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struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
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memcpy(&chan->slave_config, cfg, sizeof(*cfg));
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return 0;
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}
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static int mmp_pdma_terminate_all(struct dma_chan *dchan)
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{
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struct mmp_pdma_chan *chan = to_mmp_pdma_chan(dchan);
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@ -448,6 +448,7 @@ struct dma_pl330_chan {
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/* DMA-mapped view of the FIFO; may differ if an IOMMU is present */
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dma_addr_t fifo_dma;
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enum dma_data_direction dir;
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struct dma_slave_config slave_config;
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/* for cyclic capability */
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bool cyclic;
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@ -542,6 +543,10 @@ struct _xfer_spec {
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struct dma_pl330_desc *desc;
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};
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static int pl330_config_write(struct dma_chan *chan,
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struct dma_slave_config *slave_config,
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enum dma_transfer_direction direction);
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static inline bool _queue_full(struct pl330_thread *thrd)
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{
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return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL;
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@ -2220,20 +2225,21 @@ static int fixup_burst_len(int max_burst_len, int quirks)
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return max_burst_len;
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}
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static int pl330_config(struct dma_chan *chan,
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struct dma_slave_config *slave_config)
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static int pl330_config_write(struct dma_chan *chan,
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struct dma_slave_config *slave_config,
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enum dma_transfer_direction direction)
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{
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struct dma_pl330_chan *pch = to_pchan(chan);
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pl330_unprep_slave_fifo(pch);
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if (slave_config->direction == DMA_MEM_TO_DEV) {
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if (direction == DMA_MEM_TO_DEV) {
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if (slave_config->dst_addr)
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pch->fifo_addr = slave_config->dst_addr;
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if (slave_config->dst_addr_width)
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pch->burst_sz = __ffs(slave_config->dst_addr_width);
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pch->burst_len = fixup_burst_len(slave_config->dst_maxburst,
|
||||
pch->dmac->quirks);
|
||||
} else if (slave_config->direction == DMA_DEV_TO_MEM) {
|
||||
} else if (direction == DMA_DEV_TO_MEM) {
|
||||
if (slave_config->src_addr)
|
||||
pch->fifo_addr = slave_config->src_addr;
|
||||
if (slave_config->src_addr_width)
|
||||
|
|
@ -2245,6 +2251,16 @@ static int pl330_config(struct dma_chan *chan,
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return 0;
|
||||
}
|
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|
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static int pl330_config(struct dma_chan *chan,
|
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struct dma_slave_config *slave_config)
|
||||
{
|
||||
struct dma_pl330_chan *pch = to_pchan(chan);
|
||||
|
||||
memcpy(&pch->slave_config, slave_config, sizeof(*slave_config));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pl330_terminate_all(struct dma_chan *chan)
|
||||
{
|
||||
struct dma_pl330_chan *pch = to_pchan(chan);
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@ -2661,6 +2677,8 @@ static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
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|||
return NULL;
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}
|
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|
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pl330_config_write(chan, &pch->slave_config, direction);
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|
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if (!pl330_prep_slave_fifo(pch, direction))
|
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return NULL;
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|
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@ -2815,6 +2833,8 @@ pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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|||
if (unlikely(!pch || !sgl || !sg_len))
|
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return NULL;
|
||||
|
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pl330_config_write(chan, &pch->slave_config, direction);
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|
||||
if (!pl330_prep_slave_fifo(pch, direction))
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return NULL;
|
||||
|
||||
|
|
|
|||
|
|
@ -442,6 +442,7 @@ struct d40_base;
|
|||
* @queue: Queued jobs.
|
||||
* @prepare_queue: Prepared jobs.
|
||||
* @dma_cfg: The client configuration of this dma channel.
|
||||
* @slave_config: DMA slave configuration.
|
||||
* @configured: whether the dma_cfg configuration is valid
|
||||
* @base: Pointer to the device instance struct.
|
||||
* @src_def_cfg: Default cfg register setting for src.
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||||
|
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@ -468,6 +469,7 @@ struct d40_chan {
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|||
struct list_head queue;
|
||||
struct list_head prepare_queue;
|
||||
struct stedma40_chan_cfg dma_cfg;
|
||||
struct dma_slave_config slave_config;
|
||||
bool configured;
|
||||
struct d40_base *base;
|
||||
/* Default register configurations */
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||||
|
|
@ -625,6 +627,10 @@ static void __iomem *chan_base(struct d40_chan *chan)
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|||
#define chan_err(d40c, format, arg...) \
|
||||
d40_err(chan2dev(d40c), format, ## arg)
|
||||
|
||||
static int d40_set_runtime_config_write(struct dma_chan *chan,
|
||||
struct dma_slave_config *config,
|
||||
enum dma_transfer_direction direction);
|
||||
|
||||
static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d,
|
||||
int lli_len)
|
||||
{
|
||||
|
|
@ -2216,6 +2222,8 @@ d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
|
|||
return NULL;
|
||||
}
|
||||
|
||||
d40_set_runtime_config_write(dchan, &chan->slave_config, direction);
|
||||
|
||||
spin_lock_irqsave(&chan->lock, flags);
|
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|
||||
desc = d40_prep_desc(chan, sg_src, sg_len, dma_flags);
|
||||
|
|
@ -2634,11 +2642,22 @@ dma40_config_to_halfchannel(struct d40_chan *d40c,
|
|||
return 0;
|
||||
}
|
||||
|
||||
/* Runtime reconfiguration extension */
|
||||
static int d40_set_runtime_config(struct dma_chan *chan,
|
||||
struct dma_slave_config *config)
|
||||
{
|
||||
struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
|
||||
|
||||
memcpy(&d40c->slave_config, config, sizeof(*config));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Runtime reconfiguration extension */
|
||||
static int d40_set_runtime_config_write(struct dma_chan *chan,
|
||||
struct dma_slave_config *config,
|
||||
enum dma_transfer_direction direction)
|
||||
{
|
||||
struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
|
||||
struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;
|
||||
enum dma_slave_buswidth src_addr_width, dst_addr_width;
|
||||
dma_addr_t config_addr;
|
||||
|
|
@ -2655,7 +2674,7 @@ static int d40_set_runtime_config(struct dma_chan *chan,
|
|||
dst_addr_width = config->dst_addr_width;
|
||||
dst_maxburst = config->dst_maxburst;
|
||||
|
||||
if (config->direction == DMA_DEV_TO_MEM) {
|
||||
if (direction == DMA_DEV_TO_MEM) {
|
||||
config_addr = config->src_addr;
|
||||
|
||||
if (cfg->dir != DMA_DEV_TO_MEM)
|
||||
|
|
@ -2671,7 +2690,7 @@ static int d40_set_runtime_config(struct dma_chan *chan,
|
|||
if (dst_maxburst == 0)
|
||||
dst_maxburst = src_maxburst;
|
||||
|
||||
} else if (config->direction == DMA_MEM_TO_DEV) {
|
||||
} else if (direction == DMA_MEM_TO_DEV) {
|
||||
config_addr = config->dst_addr;
|
||||
|
||||
if (cfg->dir != DMA_MEM_TO_DEV)
|
||||
|
|
@ -2689,7 +2708,7 @@ static int d40_set_runtime_config(struct dma_chan *chan,
|
|||
} else {
|
||||
dev_err(d40c->base->dev,
|
||||
"unrecognized channel direction %d\n",
|
||||
config->direction);
|
||||
direction);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
|
@ -2746,12 +2765,12 @@ static int d40_set_runtime_config(struct dma_chan *chan,
|
|||
|
||||
/* These settings will take precedence later */
|
||||
d40c->runtime_addr = config_addr;
|
||||
d40c->runtime_direction = config->direction;
|
||||
d40c->runtime_direction = direction;
|
||||
dev_dbg(d40c->base->dev,
|
||||
"configured channel %s for %s, data width %d/%d, "
|
||||
"maxburst %d/%d elements, LE, no flow control\n",
|
||||
dma_chan_name(chan),
|
||||
(config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX",
|
||||
(direction == DMA_DEV_TO_MEM) ? "RX" : "TX",
|
||||
src_addr_width, dst_addr_width,
|
||||
src_maxburst, dst_maxburst);
|
||||
|
||||
|
|
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|||
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