MIPS: AR7: Implement clock API
This patch makes the ar7 clock code implement the Linux clk API. Drivers using the various clocks available in the SoC are updated accordingly. Signed-off-by: Florian Fainelli <florian@openwrt.org> Acked-by: Wim Van Sebroeck <wim@iguana.be> To: linux-mips@linux-mips.org Cc: Wim Van Sebroeck <wim@iguana.be> Cc: netdev@vger.kernel.org Cc: David Miller <davem@davemloft.net> Patchwork: http://patchwork.linux-mips.org/patch/881/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Florian Fainelli
Ralf Baechle
Родитель
5f3c909881
Коммит
780019ddf0
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@ -1,6 +1,7 @@
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/*
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* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
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* Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
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* Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -24,6 +25,8 @@
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#include <linux/delay.h>
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#include <linux/gcd.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <asm/addrspace.h>
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#include <asm/mach-ar7/ar7.h>
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@ -94,12 +97,16 @@ struct tnetd7200_clocks {
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struct tnetd7200_clock usb;
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};
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int ar7_cpu_clock = 150000000;
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EXPORT_SYMBOL(ar7_cpu_clock);
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int ar7_bus_clock = 125000000;
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EXPORT_SYMBOL(ar7_bus_clock);
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int ar7_dsp_clock;
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EXPORT_SYMBOL(ar7_dsp_clock);
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static struct clk bus_clk = {
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.rate = 125000000,
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};
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static struct clk cpu_clk = {
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.rate = 150000000,
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};
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static struct clk dsp_clk;
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static struct clk vbus_clk;
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static void approximate(int base, int target, int *prediv,
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int *postdiv, int *mul)
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@ -185,7 +192,7 @@ static int tnetd7300_get_clock(u32 shift, struct tnetd7300_clock *clock,
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base_clock = AR7_XTAL_CLOCK;
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break;
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case BOOT_PLL_SOURCE_CPU:
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base_clock = ar7_cpu_clock;
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base_clock = cpu_clk.rate;
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break;
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}
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@ -212,11 +219,11 @@ static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock,
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u32 *bootcr, u32 frequency)
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{
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int prediv, postdiv, mul;
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int base_clock = ar7_bus_clock;
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int base_clock = bus_clk.rate;
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switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
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case BOOT_PLL_SOURCE_BUS:
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base_clock = ar7_bus_clock;
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base_clock = bus_clk.rate;
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break;
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case BOOT_PLL_SOURCE_REF:
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base_clock = AR7_REF_CLOCK;
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@ -225,7 +232,7 @@ static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock,
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base_clock = AR7_XTAL_CLOCK;
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break;
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case BOOT_PLL_SOURCE_CPU:
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base_clock = ar7_cpu_clock;
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base_clock = cpu_clk.rate;
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break;
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}
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@ -247,18 +254,18 @@ static void __init tnetd7300_init_clocks(void)
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ioremap_nocache(UR8_REGS_CLOCKS,
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sizeof(struct tnetd7300_clocks));
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ar7_bus_clock = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT,
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bus_clk.rate = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT,
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&clocks->bus, bootcr, AR7_AFE_CLOCK);
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if (*bootcr & BOOT_PLL_ASYNC_MODE)
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ar7_cpu_clock = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT,
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cpu_clk.rate = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT,
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&clocks->cpu, bootcr, AR7_AFE_CLOCK);
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else
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ar7_cpu_clock = ar7_bus_clock;
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cpu_clk.rate = bus_clk.rate;
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if (ar7_dsp_clock == 250000000)
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if (dsp_clk.rate == 250000000)
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tnetd7300_set_clock(DSP_PLL_SOURCE_SHIFT, &clocks->dsp,
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bootcr, ar7_dsp_clock);
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bootcr, dsp_clk.rate);
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iounmap(clocks);
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iounmap(bootcr);
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@ -343,20 +350,20 @@ static void __init tnetd7200_init_clocks(void)
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printk(KERN_INFO "Clocks: Setting DSP clock\n");
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calculate(dsp_base, TNETD7200_DEF_DSP_CLK,
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&dsp_prediv, &dsp_postdiv, &dsp_mul);
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ar7_bus_clock =
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bus_clk.rate =
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((dsp_base / dsp_prediv) * dsp_mul) / dsp_postdiv;
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tnetd7200_set_clock(dsp_base, &clocks->dsp,
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dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
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ar7_bus_clock);
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bus_clk.rate);
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printk(KERN_INFO "Clocks: Setting CPU clock\n");
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calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv,
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&cpu_postdiv, &cpu_mul);
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ar7_cpu_clock =
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cpu_clk.rate =
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((cpu_base / cpu_prediv) * cpu_mul) / cpu_postdiv;
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tnetd7200_set_clock(cpu_base, &clocks->cpu,
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cpu_prediv, cpu_postdiv, -1, cpu_mul,
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ar7_cpu_clock);
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cpu_clk.rate);
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} else
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if (*bootcr & BOOT_PLL_2TO1_MODE) {
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@ -365,48 +372,90 @@ static void __init tnetd7200_init_clocks(void)
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printk(KERN_INFO "Clocks: Setting CPU clock\n");
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calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv,
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&cpu_postdiv, &cpu_mul);
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ar7_cpu_clock = ((cpu_base / cpu_prediv) * cpu_mul)
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cpu_clk.rate = ((cpu_base / cpu_prediv) * cpu_mul)
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/ cpu_postdiv;
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tnetd7200_set_clock(cpu_base, &clocks->cpu,
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cpu_prediv, cpu_postdiv, -1, cpu_mul,
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ar7_cpu_clock);
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cpu_clk.rate);
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printk(KERN_INFO "Clocks: Setting DSP clock\n");
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calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv,
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&dsp_postdiv, &dsp_mul);
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ar7_bus_clock = ar7_cpu_clock / 2;
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bus_clk.rate = cpu_clk.rate / 2;
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tnetd7200_set_clock(dsp_base, &clocks->dsp,
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dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
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dsp_mul * 2, ar7_bus_clock);
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dsp_mul * 2, bus_clk.rate);
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} else {
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printk(KERN_INFO "Clocks: Sync 1:1 mode\n");
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printk(KERN_INFO "Clocks: Setting DSP clock\n");
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calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv,
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&dsp_postdiv, &dsp_mul);
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ar7_bus_clock = ((dsp_base / dsp_prediv) * dsp_mul)
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bus_clk.rate = ((dsp_base / dsp_prediv) * dsp_mul)
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/ dsp_postdiv;
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tnetd7200_set_clock(dsp_base, &clocks->dsp,
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dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
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dsp_mul * 2, ar7_bus_clock);
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dsp_mul * 2, bus_clk.rate);
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ar7_cpu_clock = ar7_bus_clock;
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cpu_clk.rate = bus_clk.rate;
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}
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printk(KERN_INFO "Clocks: Setting USB clock\n");
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usb_base = ar7_bus_clock;
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usb_base = bus_clk.rate;
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calculate(usb_base, TNETD7200_DEF_USB_CLK, &usb_prediv,
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&usb_postdiv, &usb_mul);
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tnetd7200_set_clock(usb_base, &clocks->usb,
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usb_prediv, usb_postdiv, -1, usb_mul,
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TNETD7200_DEF_USB_CLK);
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ar7_dsp_clock = ar7_cpu_clock;
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dsp_clk.rate = cpu_clk.rate;
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iounmap(clocks);
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iounmap(bootcr);
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}
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/*
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* Linux clock API
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*/
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int clk_enable(struct clk *clk)
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{
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return 0;
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}
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EXPORT_SYMBOL(clk_enable);
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void clk_disable(struct clk *clk)
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{
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}
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EXPORT_SYMBOL(clk_disable);
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unsigned long clk_get_rate(struct clk *clk)
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{
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return clk->rate;
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}
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EXPORT_SYMBOL(clk_get_rate);
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struct clk *clk_get(struct device *dev, const char *id)
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{
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if (!strcmp(id, "bus"))
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return &bus_clk;
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/* cpmac and vbus share the same rate */
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if (!strcmp(id, "cpmac"))
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return &vbus_clk;
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if (!strcmp(id, "cpu"))
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return &cpu_clk;
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if (!strcmp(id, "dsp"));
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return &dsp_clk;
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if (!strcmp(id, "vbus"))
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return &vbus_clk;
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return ERR_PTR(-ENOENT);
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}
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EXPORT_SYMBOL(clk_get);
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void clk_put(struct clk *clk)
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{
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}
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EXPORT_SYMBOL(clk_put);
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int __init ar7_init_clocks(void)
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{
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switch (ar7_chip_id()) {
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@ -415,12 +464,14 @@ int __init ar7_init_clocks(void)
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tnetd7200_init_clocks();
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break;
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case AR7_CHIP_7300:
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ar7_dsp_clock = tnetd7300_dsp_clock();
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dsp_clk.rate = tnetd7300_dsp_clock();
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tnetd7300_init_clocks();
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break;
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default:
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break;
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}
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/* adjust vbus clock rate */
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vbus_clk.rate = bus_clk.rate / 2;
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return 0;
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}
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@ -35,6 +35,7 @@
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#include <linux/phy.h>
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#include <linux/phy_fixed.h>
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#include <linux/gpio.h>
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#include <linux/clk.h>
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#include <asm/addrspace.h>
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#include <asm/mach-ar7/ar7.h>
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@ -507,13 +508,18 @@ static int __init ar7_register_devices(void)
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u32 *bootcr, val;
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#ifdef CONFIG_SERIAL_8250
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static struct uart_port uart_port[2] __initdata;
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struct clk *bus_clk;
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memset(uart_port, 0, sizeof(struct uart_port) * 2);
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bus_clk = clk_get(NULL, "bus");
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if (IS_ERR(bus_clk))
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panic("unable to get bus clk\n");
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uart_port[0].type = PORT_16550A;
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uart_port[0].line = 0;
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uart_port[0].irq = AR7_IRQ_UART0;
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uart_port[0].uartclk = ar7_bus_freq() / 2;
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uart_port[0].uartclk = clk_get_rate(bus_clk) / 2;
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uart_port[0].iotype = UPIO_MEM32;
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uart_port[0].mapbase = AR7_REGS_UART0;
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uart_port[0].membase = ioremap(uart_port[0].mapbase, 256);
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@ -528,7 +534,7 @@ static int __init ar7_register_devices(void)
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uart_port[1].type = PORT_16550A;
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uart_port[1].line = 1;
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uart_port[1].irq = AR7_IRQ_UART1;
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uart_port[1].uartclk = ar7_bus_freq() / 2;
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uart_port[1].uartclk = clk_get_rate(bus_clk) / 2;
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uart_port[1].iotype = UPIO_MEM32;
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uart_port[1].mapbase = UR8_REGS_UART1;
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uart_port[1].membase = ioremap(uart_port[1].mapbase, 256);
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@ -20,11 +20,21 @@
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#include <linux/init.h>
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#include <linux/time.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <asm/time.h>
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#include <asm/mach-ar7/ar7.h>
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void __init plat_time_init(void)
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{
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mips_hpt_frequency = ar7_cpu_freq() / 2;
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struct clk *cpu_clk;
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cpu_clk = clk_get(NULL, "cpu");
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if (IS_ERR(cpu_clk)) {
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printk(KERN_ERR "unable to get cpu clock\n");
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return;
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}
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mips_hpt_frequency = clk_get_rate(cpu_clk) / 2;
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}
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@ -105,26 +105,9 @@ static inline u8 ar7_chip_rev(void)
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return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff;
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}
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static inline int ar7_cpu_freq(void)
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{
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return ar7_cpu_clock;
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}
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static inline int ar7_bus_freq(void)
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{
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return ar7_bus_clock;
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}
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static inline int ar7_vbus_freq(void)
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{
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return ar7_bus_clock / 2;
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}
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#define ar7_cpmac_freq ar7_vbus_freq
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static inline int ar7_dsp_freq(void)
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{
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return ar7_dsp_clock;
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}
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struct clk {
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unsigned int rate;
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};
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static inline int ar7_has_high_cpmac(void)
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{
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@ -36,6 +36,7 @@
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#include <linux/phy_fixed.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/clk.h>
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#include <asm/gpio.h>
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#include <asm/atomic.h>
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@ -294,9 +295,16 @@ static int cpmac_mdio_write(struct mii_bus *bus, int phy_id,
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static int cpmac_mdio_reset(struct mii_bus *bus)
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{
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struct clk *cpmac_clk;
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cpmac_clk = clk_get(&bus->dev, "cpmac");
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if (IS_ERR(cpmac_clk)) {
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printk(KERN_ERR "unable to get cpmac clock\n");
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return -1;
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}
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ar7_device_reset(AR7_RESET_BIT_MDIO);
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cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE |
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MDIOC_CLKDIV(ar7_cpmac_freq() / 2200000 - 1));
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MDIOC_CLKDIV(clk_get_rate(cpmac_clk) / 2200000 - 1));
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return 0;
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}
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@ -34,6 +34,7 @@
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/uaccess.h>
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#include <linux/clk.h>
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#include <asm/addrspace.h>
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#include <asm/mach-ar7/ar7.h>
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@ -80,6 +81,8 @@ static struct resource *ar7_regs_wdt;
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/* Pointer to the remapped WDT IO space */
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static struct ar7_wdt *ar7_wdt;
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static struct clk *vbus_clk;
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static void ar7_wdt_kick(u32 value)
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{
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WRITE_REG(ar7_wdt->kick_lock, 0x5555);
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@ -138,17 +141,19 @@ static void ar7_wdt_disable(u32 value)
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static void ar7_wdt_update_margin(int new_margin)
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{
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u32 change;
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u32 vbus_rate;
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change = new_margin * (ar7_vbus_freq() / prescale_value);
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vbus_rate = clk_get_rate(vbus_clk);
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change = new_margin * (vbus_rate / prescale_value);
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if (change < 1)
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change = 1;
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if (change > 0xffff)
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change = 0xffff;
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ar7_wdt_change(change);
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margin = change * prescale_value / ar7_vbus_freq();
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margin = change * prescale_value / vbus_rate;
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printk(KERN_INFO DRVNAME
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": timer margin %d seconds (prescale %d, change %d, freq %d)\n",
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margin, prescale_value, change, ar7_vbus_freq());
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margin, prescale_value, change, vbus_rate);
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}
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static void ar7_wdt_enable_wdt(void)
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@ -298,6 +303,13 @@ static int __devinit ar7_wdt_probe(struct platform_device *pdev)
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goto out_mem_region;
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}
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vbus_clk = clk_get(NULL, "vbus");
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if (IS_ERR(vbus_clk)) {
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printk(KERN_ERR DRVNAME ": could not get vbus clock\n");
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rc = PTR_ERR(vbus_clk);
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goto out_mem_region;
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}
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ar7_wdt_disable_wdt();
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ar7_wdt_prescale(prescale_value);
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ar7_wdt_update_margin(margin);
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