perf test: Add selftest to test IBS invocation via core pmu events
IBS pmu can be invoked via fixed set of core pmu events with 'precise_ip' set to 1. Add a simple event open test for all these events. Without kernel fix: $ sudo ./perf test -vv 76 76: AMD IBS via core pmu : --- start --- test child forked, pid 6553 Using CPUID AuthenticAMD-25-1-1 type: 0x0, config: 0x0, fd: 3 - Pass type: 0x0, config: 0x1, fd: -1 - Pass type: 0x4, config: 0x76, fd: -1 - Fail type: 0x4, config: 0xc1, fd: -1 - Fail type: 0x4, config: 0x12, fd: -1 - Pass test child finished with -1 ---- end ---- AMD IBS via core pmu: FAILED! With kernel fix: $ sudo ./perf test -vv 76 76: AMD IBS via core pmu : --- start --- test child forked, pid 7526 Using CPUID AuthenticAMD-25-1-1 type: 0x0, config: 0x0, fd: 3 - Pass type: 0x0, config: 0x1, fd: -1 - Pass type: 0x4, config: 0x76, fd: 3 - Pass type: 0x4, config: 0xc1, fd: 3 - Pass type: 0x4, config: 0x12, fd: -1 - Pass test child finished with 0 ---- end ---- AMD IBS via core pmu: Ok Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20230504110003.2548-5-ravi.bangoria@amd.com
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@ -11,6 +11,7 @@ int test__intel_pt_pkt_decoder(struct test_suite *test, int subtest);
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int test__intel_pt_hybrid_compat(struct test_suite *test, int subtest);
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int test__bp_modify(struct test_suite *test, int subtest);
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int test__x86_sample_parsing(struct test_suite *test, int subtest);
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int test__amd_ibs_via_core_pmu(struct test_suite *test, int subtest);
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extern struct test_suite *arch_tests[];
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@ -5,3 +5,4 @@ perf-y += arch-tests.o
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perf-y += sample-parsing.o
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perf-$(CONFIG_AUXTRACE) += insn-x86.o intel-pt-test.o
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perf-$(CONFIG_X86_64) += bp-modify.o
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perf-y += amd-ibs-via-core-pmu.o
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@ -0,0 +1,71 @@
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// SPDX-License-Identifier: GPL-2.0
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#include "arch-tests.h"
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#include "linux/perf_event.h"
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#include "tests/tests.h"
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#include "pmu.h"
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#include "pmus.h"
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#include "../perf-sys.h"
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#include "debug.h"
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#define NR_SUB_TESTS 5
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static struct sub_tests {
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int type;
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unsigned long config;
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bool valid;
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} sub_tests[NR_SUB_TESTS] = {
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{ PERF_TYPE_HARDWARE, PERF_COUNT_HW_CPU_CYCLES, true },
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{ PERF_TYPE_HARDWARE, PERF_COUNT_HW_INSTRUCTIONS, false },
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{ PERF_TYPE_RAW, 0x076, true },
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{ PERF_TYPE_RAW, 0x0C1, true },
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{ PERF_TYPE_RAW, 0x012, false },
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};
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static int event_open(int type, unsigned long config)
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{
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struct perf_event_attr attr;
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memset(&attr, 0, sizeof(struct perf_event_attr));
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attr.type = type;
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attr.size = sizeof(struct perf_event_attr);
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attr.config = config;
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attr.disabled = 1;
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attr.precise_ip = 1;
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attr.sample_type = PERF_SAMPLE_IP | PERF_SAMPLE_TID;
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attr.sample_period = 100000;
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return sys_perf_event_open(&attr, -1, 0, -1, 0);
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}
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int test__amd_ibs_via_core_pmu(struct test_suite *test __maybe_unused,
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int subtest __maybe_unused)
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{
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struct perf_pmu *ibs_pmu;
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int ret = TEST_OK;
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int fd, i;
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if (list_empty(&pmus))
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perf_pmu__scan(NULL);
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ibs_pmu = perf_pmu__find("ibs_op");
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if (!ibs_pmu)
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return TEST_SKIP;
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for (i = 0; i < NR_SUB_TESTS; i++) {
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fd = event_open(sub_tests[i].type, sub_tests[i].config);
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pr_debug("type: 0x%x, config: 0x%lx, fd: %d - ", sub_tests[i].type,
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sub_tests[i].config, fd);
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if ((sub_tests[i].valid && fd == -1) ||
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(!sub_tests[i].valid && fd > 0)) {
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pr_debug("Fail\n");
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ret = TEST_FAIL;
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} else {
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pr_debug("Pass\n");
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}
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if (fd > 0)
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close(fd);
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}
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return ret;
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}
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@ -22,6 +22,7 @@ struct test_suite suite__intel_pt = {
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DEFINE_SUITE("x86 bp modify", bp_modify);
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#endif
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DEFINE_SUITE("x86 Sample parsing", x86_sample_parsing);
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DEFINE_SUITE("AMD IBS via core pmu", amd_ibs_via_core_pmu);
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struct test_suite *arch_tests[] = {
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#ifdef HAVE_DWARF_UNWIND_SUPPORT
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@ -35,5 +36,6 @@ struct test_suite *arch_tests[] = {
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&suite__bp_modify,
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#endif
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&suite__x86_sample_parsing,
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&suite__amd_ibs_via_core_pmu,
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NULL,
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};
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