sh: New atomic ops for SH-4A movli.l/movco.l
SH-4A implements LL/SC instructions, so we implement a simple set of atomic operations using these. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
Родитель
15f57a29a1
Коммит
781125ca58
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@ -22,49 +22,110 @@ typedef struct { volatile int counter; } atomic_t;
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* forward to code at the end of this object's .text section, then
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* branch back to restart the operation.
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*/
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static __inline__ void atomic_add(int i, atomic_t * v)
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static inline void atomic_add(int i, atomic_t *v)
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{
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#ifdef CONFIG_CPU_SH4A
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unsigned long tmp;
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__asm__ __volatile__ (
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"1: movli.l @%3, %0 ! atomic_add \n"
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" add %2, %0 \n"
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" movco.l %0, @%3 \n"
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" bf 1b \n"
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: "=&z" (tmp), "=r" (&v->counter)
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: "r" (i), "r" (&v->counter)
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: "t");
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#else
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unsigned long flags;
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local_irq_save(flags);
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*(long *)v += i;
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local_irq_restore(flags);
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#endif
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}
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static __inline__ void atomic_sub(int i, atomic_t *v)
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static inline void atomic_sub(int i, atomic_t *v)
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{
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#ifdef CONFIG_CPU_SH4A
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unsigned long tmp;
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__asm__ __volatile__ (
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"1: movli.l @%3, %0 ! atomic_sub \n"
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" sub %2, %0 \n"
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" movco.l %0, @%3 \n"
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" bf 1b \n"
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: "=&z" (tmp), "=r" (&v->counter)
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: "r" (i), "r" (&v->counter)
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: "t");
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#else
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unsigned long flags;
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local_irq_save(flags);
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*(long *)v -= i;
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local_irq_restore(flags);
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#endif
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}
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static __inline__ int atomic_add_return(int i, atomic_t * v)
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/*
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* SH-4A note:
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*
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* We basically get atomic_xxx_return() for free compared with
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* atomic_xxx(). movli.l/movco.l require r0 due to the instruction
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* encoding, so the retval is automatically set without having to
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* do any special work.
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*/
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static inline int atomic_add_return(int i, atomic_t *v)
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{
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unsigned long temp, flags;
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unsigned long temp;
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#ifdef CONFIG_CPU_SH4A
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__asm__ __volatile__ (
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"1: movli.l @%3, %0 ! atomic_add_return \n"
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" add %2, %0 \n"
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" movco.l %0, @%3 \n"
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" bf 1b \n"
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" synco \n"
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: "=&z" (temp), "=r" (&v->counter)
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: "r" (i), "r" (&v->counter)
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: "t");
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#else
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unsigned long flags;
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local_irq_save(flags);
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temp = *(long *)v;
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temp += i;
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*(long *)v = temp;
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local_irq_restore(flags);
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#endif
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return temp;
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}
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#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
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static __inline__ int atomic_sub_return(int i, atomic_t * v)
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static inline int atomic_sub_return(int i, atomic_t *v)
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{
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unsigned long temp, flags;
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unsigned long temp;
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#ifdef CONFIG_CPU_SH4A
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__asm__ __volatile__ (
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"1: movli.l @%3, %0 ! atomic_sub_return \n"
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" sub %2, %0 \n"
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" movco.l %0, @%3 \n"
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" bf 1b \n"
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" synco \n"
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: "=&z" (temp), "=r" (&v->counter)
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: "r" (i), "r" (&v->counter)
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: "t");
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#else
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unsigned long flags;
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local_irq_save(flags);
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temp = *(long *)v;
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temp -= i;
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*(long *)v = temp;
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local_irq_restore(flags);
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#endif
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return temp;
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}
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@ -119,22 +180,48 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u)
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}
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#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
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static __inline__ void atomic_clear_mask(unsigned int mask, atomic_t *v)
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static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
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{
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#ifdef CONFIG_CPU_SH4A
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unsigned long tmp;
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__asm__ __volatile__ (
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"1: movli.l @%3, %0 ! atomic_clear_mask \n"
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" and %2, %0 \n"
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" movco.l %0, @%3 \n"
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" bf 1b \n"
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: "=&z" (tmp), "=r" (&v->counter)
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: "r" (~mask), "r" (&v->counter)
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: "t");
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#else
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unsigned long flags;
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local_irq_save(flags);
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*(long *)v &= ~mask;
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local_irq_restore(flags);
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#endif
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}
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static __inline__ void atomic_set_mask(unsigned int mask, atomic_t *v)
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static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
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{
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#ifdef CONFIG_CPU_SH4A
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unsigned long tmp;
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__asm__ __volatile__ (
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"1: movli.l @%3, %0 ! atomic_set_mask \n"
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" or %2, %0 \n"
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" movco.l %0, @%3 \n"
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" bf 1b \n"
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: "=&z" (tmp), "=r" (&v->counter)
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: "r" (mask), "r" (&v->counter)
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: "t");
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#else
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unsigned long flags;
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local_irq_save(flags);
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*(long *)v |= mask;
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local_irq_restore(flags);
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#endif
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}
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/* Atomic operations are already serializing on SH */
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