sh: Tidy up the optional L2 probing, wire it up for SH7786.
This tidies up the L2 probing, as it may or may not be implemented on a CPU, regardless of whether it is supported. This converts the cvr validity checks from BUG_ON()'s to simply clearing the CPU_HAS_L2_CACHE flag and moving on with life. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Родитель
43909a9380
Коммит
7863d3f7ae
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@ -134,7 +134,7 @@ int __init detect_cpu_and_cache_system(void)
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boot_cpu_data.icache.ways = 4;
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boot_cpu_data.icache.ways = 4;
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boot_cpu_data.dcache.ways = 4;
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boot_cpu_data.dcache.ways = 4;
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boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
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boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
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CPU_HAS_LLSC | CPU_HAS_PTEAEX;
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CPU_HAS_LLSC | CPU_HAS_PTEAEX | CPU_HAS_L2_CACHE;
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break;
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break;
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case 0x3008:
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case 0x3008:
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boot_cpu_data.icache.ways = 4;
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boot_cpu_data.icache.ways = 4;
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@ -228,15 +228,21 @@ int __init detect_cpu_and_cache_system(void)
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}
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}
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/*
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/*
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* Setup the L2 cache desc
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*
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* SH-4A's have an optional PIPT L2.
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* SH-4A's have an optional PIPT L2.
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*/
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*/
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if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
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if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
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/* Bug if we can't decode the L2 info */
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/*
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BUG_ON(!(cvr & 0xf));
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* Verify that it really has something hooked up, this
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* is the safety net for CPUs that have optional L2
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/* Silicon and specifications have clearly never met.. */
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* support yet do not implement it.
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*/
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if ((cvr & 0xf) == 0)
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boot_cpu_data.flags &= ~CPU_HAS_L2_CACHE;
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else {
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/*
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* Silicon and specifications have clearly never
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* met..
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*/
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cvr ^= 0xf;
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cvr ^= 0xf;
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/*
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/*
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@ -247,8 +253,6 @@ int __init detect_cpu_and_cache_system(void)
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*/
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*/
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size = (cvr & 0xf) << 17;
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size = (cvr & 0xf) << 17;
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BUG_ON(!size);
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boot_cpu_data.scache.way_incr = (1 << 16);
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boot_cpu_data.scache.way_incr = (1 << 16);
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boot_cpu_data.scache.entry_shift = 5;
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boot_cpu_data.scache.entry_shift = 5;
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boot_cpu_data.scache.ways = 4;
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boot_cpu_data.scache.ways = 4;
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@ -266,6 +270,7 @@ int __init detect_cpu_and_cache_system(void)
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(boot_cpu_data.scache.sets *
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(boot_cpu_data.scache.sets *
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boot_cpu_data.scache.linesz);
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boot_cpu_data.scache.linesz);
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}
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}
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}
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return 0;
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return 0;
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}
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}
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