mmc: sdhci-pci-gli: Set SDR104's clock to 205MHz and enable SSC for GL975x
Set SDR104's clock to 205MHz and enable SSC for GL9750 and GL9755 Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> Link: https://lore.kernel.org/r/20200717033350.13006-1-benchuanggli@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Ben Chuang
Ulf Hansson
Родитель
90508658d7
Коммит
786d33c887
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@ -31,10 +31,18 @@
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#define SDHCI_GLI_9750_ALL_RST (BIT(24)|BIT(25)|BIT(28)|BIT(30))
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#define SDHCI_GLI_9750_PLL 0x864
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#define SDHCI_GLI_9750_PLL_LDIV GENMASK(9, 0)
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#define SDHCI_GLI_9750_PLL_PDIV GENMASK(14, 12)
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#define SDHCI_GLI_9750_PLL_DIR BIT(15)
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#define SDHCI_GLI_9750_PLL_TX2_INV BIT(23)
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#define SDHCI_GLI_9750_PLL_TX2_DLY GENMASK(22, 20)
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#define GLI_9750_PLL_TX2_INV_VALUE 0x1
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#define GLI_9750_PLL_TX2_DLY_VALUE 0x0
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#define SDHCI_GLI_9750_PLLSSC_STEP GENMASK(28, 24)
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#define SDHCI_GLI_9750_PLLSSC_EN BIT(31)
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#define SDHCI_GLI_9750_PLLSSC 0x86C
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#define SDHCI_GLI_9750_PLLSSC_PPM GENMASK(31, 16)
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#define SDHCI_GLI_9750_SW_CTRL 0x874
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#define SDHCI_GLI_9750_SW_CTRL_4 GENMASK(7, 6)
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@ -76,6 +84,21 @@
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#define PCIE_GLI_9763E_SCR 0x8E0
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#define GLI_9763E_SCR_AXI_REQ BIT(9)
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#define PCI_GLI_9755_WT 0x800
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#define PCI_GLI_9755_WT_EN BIT(0)
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#define GLI_9755_WT_EN_ON 0x1
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#define GLI_9755_WT_EN_OFF 0x0
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#define PCI_GLI_9755_PLL 0x64
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#define PCI_GLI_9755_PLL_LDIV GENMASK(9, 0)
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#define PCI_GLI_9755_PLL_PDIV GENMASK(14, 12)
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#define PCI_GLI_9755_PLL_DIR BIT(15)
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#define PCI_GLI_9755_PLLSSC_STEP GENMASK(28, 24)
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#define PCI_GLI_9755_PLLSSC_EN BIT(31)
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#define PCI_GLI_9755_PLLSSC 0x68
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#define PCI_GLI_9755_PLLSSC_PPM GENMASK(15, 0)
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#define GLI_MAX_TUNING_LOOP 40
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/* Genesys Logic chipset */
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@ -280,6 +303,84 @@ static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode)
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return 0;
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}
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static void gl9750_disable_ssc_pll(struct sdhci_host *host)
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{
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u32 pll;
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gl9750_wt_on(host);
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pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
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pll &= ~(SDHCI_GLI_9750_PLL_DIR | SDHCI_GLI_9750_PLLSSC_EN);
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sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
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gl9750_wt_off(host);
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}
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static void gl9750_set_pll(struct sdhci_host *host, u8 dir, u16 ldiv, u8 pdiv)
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{
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u32 pll;
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gl9750_wt_on(host);
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pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
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pll &= ~(SDHCI_GLI_9750_PLL_LDIV |
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SDHCI_GLI_9750_PLL_PDIV |
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SDHCI_GLI_9750_PLL_DIR);
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pll |= FIELD_PREP(SDHCI_GLI_9750_PLL_LDIV, ldiv) |
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FIELD_PREP(SDHCI_GLI_9750_PLL_PDIV, pdiv) |
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FIELD_PREP(SDHCI_GLI_9750_PLL_DIR, dir);
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sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
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gl9750_wt_off(host);
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/* wait for pll stable */
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mdelay(1);
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}
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static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm)
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{
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u32 pll;
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u32 ssc;
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gl9750_wt_on(host);
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pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
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ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC);
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pll &= ~(SDHCI_GLI_9750_PLLSSC_STEP |
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SDHCI_GLI_9750_PLLSSC_EN);
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ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM;
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pll |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_STEP, step) |
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FIELD_PREP(SDHCI_GLI_9750_PLLSSC_EN, enable);
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ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm);
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sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC);
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sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
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gl9750_wt_off(host);
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}
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static void gl9750_set_ssc_pll_205mhz(struct sdhci_host *host)
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{
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/* set pll to 205MHz and enable ssc */
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gl9750_set_ssc(host, 0x1, 0x1F, 0xFFE7);
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gl9750_set_pll(host, 0x1, 0x246, 0x0);
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}
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static void sdhci_gl9750_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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struct mmc_ios *ios = &host->mmc->ios;
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u16 clk;
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host->mmc->actual_clock = 0;
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gl9750_disable_ssc_pll(host);
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sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
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if (clock == 0)
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return;
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clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
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if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
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host->mmc->actual_clock = 205000000;
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gl9750_set_ssc_pll_205mhz(host);
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}
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sdhci_enable_clk(host, clk);
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}
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static void gli_pcie_enable_msi(struct sdhci_pci_slot *slot)
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{
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int ret;
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@ -295,6 +396,121 @@ static void gli_pcie_enable_msi(struct sdhci_pci_slot *slot)
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slot->host->irq = pci_irq_vector(slot->chip->pdev, 0);
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}
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static inline void gl9755_wt_on(struct pci_dev *pdev)
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{
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u32 wt_value;
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u32 wt_enable;
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pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);
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wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value);
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if (wt_enable == GLI_9755_WT_EN_ON)
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return;
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wt_value &= ~PCI_GLI_9755_WT_EN;
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wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_ON);
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pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);
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}
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static inline void gl9755_wt_off(struct pci_dev *pdev)
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{
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u32 wt_value;
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u32 wt_enable;
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pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);
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wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value);
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if (wt_enable == GLI_9755_WT_EN_OFF)
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return;
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wt_value &= ~PCI_GLI_9755_WT_EN;
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wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_OFF);
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pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);
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}
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static void gl9755_disable_ssc_pll(struct pci_dev *pdev)
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{
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u32 pll;
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gl9755_wt_on(pdev);
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pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
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pll &= ~(PCI_GLI_9755_PLL_DIR | PCI_GLI_9755_PLLSSC_EN);
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pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
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gl9755_wt_off(pdev);
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}
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static void gl9755_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv)
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{
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u32 pll;
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gl9755_wt_on(pdev);
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pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
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pll &= ~(PCI_GLI_9755_PLL_LDIV |
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PCI_GLI_9755_PLL_PDIV |
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PCI_GLI_9755_PLL_DIR);
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pll |= FIELD_PREP(PCI_GLI_9755_PLL_LDIV, ldiv) |
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FIELD_PREP(PCI_GLI_9755_PLL_PDIV, pdiv) |
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FIELD_PREP(PCI_GLI_9755_PLL_DIR, dir);
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pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
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gl9755_wt_off(pdev);
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/* wait for pll stable */
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mdelay(1);
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}
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static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm)
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{
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u32 pll;
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u32 ssc;
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gl9755_wt_on(pdev);
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pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
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pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc);
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pll &= ~(PCI_GLI_9755_PLLSSC_STEP |
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PCI_GLI_9755_PLLSSC_EN);
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ssc &= ~PCI_GLI_9755_PLLSSC_PPM;
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pll |= FIELD_PREP(PCI_GLI_9755_PLLSSC_STEP, step) |
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FIELD_PREP(PCI_GLI_9755_PLLSSC_EN, enable);
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ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm);
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pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc);
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pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
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gl9755_wt_off(pdev);
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}
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static void gl9755_set_ssc_pll_205mhz(struct pci_dev *pdev)
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{
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/* set pll to 205MHz and enable ssc */
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gl9755_set_ssc(pdev, 0x1, 0x1F, 0xFFE7);
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gl9755_set_pll(pdev, 0x1, 0x246, 0x0);
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}
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static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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struct sdhci_pci_slot *slot = sdhci_priv(host);
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struct mmc_ios *ios = &host->mmc->ios;
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struct pci_dev *pdev;
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u16 clk;
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pdev = slot->chip->pdev;
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host->mmc->actual_clock = 0;
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gl9755_disable_ssc_pll(pdev);
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sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
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if (clock == 0)
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return;
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clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
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if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
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host->mmc->actual_clock = 205000000;
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gl9755_set_ssc_pll_205mhz(pdev);
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}
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sdhci_enable_clk(host, clk);
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}
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static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot)
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{
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struct sdhci_host *host = slot->host;
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@ -440,7 +656,7 @@ static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot)
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}
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static const struct sdhci_ops sdhci_gl9755_ops = {
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.set_clock = sdhci_set_clock,
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.set_clock = sdhci_gl9755_set_clock,
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.enable_dma = sdhci_pci_enable_dma,
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.set_bus_width = sdhci_set_bus_width,
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.reset = sdhci_reset,
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@ -460,7 +676,7 @@ const struct sdhci_pci_fixes sdhci_gl9755 = {
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static const struct sdhci_ops sdhci_gl9750_ops = {
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.read_l = sdhci_gl9750_readl,
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.set_clock = sdhci_set_clock,
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.set_clock = sdhci_gl9750_set_clock,
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.enable_dma = sdhci_pci_enable_dma,
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.set_bus_width = sdhci_set_bus_width,
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.reset = sdhci_gl9750_reset,
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