Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle: - Improvements to the tlb_dump code - KVM fixes - Add support for appended DTB - Minor improvements to the R12000 support - Minor improvements to the R12000 support - Various platform improvments for BCM47xx - The usual pile of minor cleanups - A number of BPF fixes and improvments - Some improvments to the support for R3000 and DECstations - Some improvments to the ATH79 platform support - A major patchset for the JZ4740 SOC adding support for the CI20 platform - Add support for the Pistachio SOC - Minor BMIPS/BCM63xx platform support improvments. - Avoid "SYNC 0" as memory barrier when unlocking spinlocks - Add support for the XWR-1750 board. - Paul's __cpuinit/__cpuinitdata cleanups. - New Malta CPU board support large memory so enable ZONE_DMA32. * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (131 commits) MIPS: spinlock: Adjust arch_spin_lock back-off time MIPS: asmmacro: Ensure 64-bit FP registers are used with MSA MIPS: BCM47xx: Simplify handling SPROM revisions MIPS: Cobalt Don't use module_init in non-modular MTD registration. MIPS: BCM47xx: Move NVRAM driver to the drivers/firmware/ MIPS: use for_each_sg() MIPS: BCM47xx: Don't select BCMA_HOST_PCI MIPS: BCM47xx: Add helper variable for storing NVRAM length MIPS: IRQ/IP27: Move IRQ allocation API to platform code. MIPS: Replace smp_mb with release barrier function in unlocks. MIPS: i8259: DT support MIPS: Malta: Basic DT plumbing MIPS: include errno.h for ENODEV in mips-cm.h MIPS: Define GCR_GIC_STATUS register fields MIPS: BPF: Introduce BPF ASM helpers MIPS: BPF: Use BPF register names to describe the ABI MIPS: BPF: Move register definition to the BPF header MIPS: net: BPF: Replace RSIZE with SZREG MIPS: BPF: Free up some callee-saved registers MIPS: Xtalk: Update xwidget.h with known Xtalk device numbers ...
This commit is contained in:
Linus Torvalds
Коммит
78c10e556e
|
|
@ -0,0 +1,53 @@
|
|||
Ingenic SoC CGU binding
|
||||
|
||||
The CGU in an Ingenic SoC provides all the clocks generated on-chip. It
|
||||
typically includes a variety of PLLs, multiplexers, dividers & gates in order
|
||||
to provide many different clock signals derived from only 2 external source
|
||||
clocks.
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "ingenic,<soctype>-cgu".
|
||||
For example "ingenic,jz4740-cgu" or "ingenic,jz4780-cgu".
|
||||
- reg : The address & length of the CGU registers.
|
||||
- clocks : List of phandle & clock specifiers for clocks external to the CGU.
|
||||
Two such external clocks should be specified - first the external crystal
|
||||
"ext" and second the RTC clock source "rtc".
|
||||
- clock-names : List of name strings for the external clocks.
|
||||
- #clock-cells: Should be 1.
|
||||
Clock consumers specify this argument to identify a clock. The valid values
|
||||
may be found in <dt-bindings/clock/<soctype>-cgu.h>.
|
||||
|
||||
Example SoC include file:
|
||||
|
||||
/ {
|
||||
cgu: jz4740-cgu {
|
||||
compatible = "ingenic,jz4740-cgu";
|
||||
reg = <0x10000000 0x100>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
uart0: serial@10030000 {
|
||||
clocks = <&cgu JZ4740_CLK_UART0>;
|
||||
};
|
||||
};
|
||||
|
||||
Example board file:
|
||||
|
||||
/ {
|
||||
ext: clock@0 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
|
||||
rtc: clock@1 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
&cgu {
|
||||
clocks = <&ext> <&rtc>;
|
||||
clock-names: "ext", "rtc";
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller
|
||||
|
||||
The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
|
||||
|
||||
Required Properties:
|
||||
- compatible: has to be "qca,<soctype>-cpu-intc" and one of the following
|
||||
fallbacks:
|
||||
- "qca,ar7100-pll"
|
||||
- "qca,ar7240-pll"
|
||||
- "qca,ar9130-pll"
|
||||
- "qca,ar9330-pll"
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||||
- "qca,ar9340-pll"
|
||||
- "qca,qca9550-pll"
|
||||
- reg: Base address and size of the controllers memory area
|
||||
- clock-names: Name of the input clock, has to be "ref"
|
||||
- clocks: phandle of the external reference clock
|
||||
- #clock-cells: has to be one
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names: should be "cpu", "ddr", "ahb"
|
||||
|
||||
Example:
|
||||
|
||||
memory-controller@18050000 {
|
||||
compatible = "qca,ar9132-ppl", "qca,ar9130-pll";
|
||||
reg = <0x18050000 0x20>;
|
||||
|
||||
clock-names = "ref";
|
||||
clocks = <&extosc>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "cpu", "ddr", "ahb";
|
||||
};
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
Binding for Qualcomm Atheros AR7xxx/AR9xxx GPIO controller
|
||||
|
||||
Required properties:
|
||||
- compatible: has to be "qca,<soctype>-gpio" and one of the following
|
||||
fallbacks:
|
||||
- "qca,ar7100-gpio"
|
||||
- "qca,ar9340-gpio"
|
||||
- reg: Base address and size of the controllers memory area
|
||||
- gpio-controller : Marks the device node as a GPIO controller.
|
||||
- #gpio-cells : Should be two. The first cell is the pin number and the
|
||||
second cell is used to specify optional parameters.
|
||||
- ngpios: Should be set to the number of GPIOs available on the SoC.
|
||||
|
||||
Optional properties:
|
||||
- interrupt-parent: phandle of the parent interrupt controller.
|
||||
- interrupts: Interrupt specifier for the controllers interrupt.
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode interrupt
|
||||
source, should be 2
|
||||
|
||||
Please refer to interrupts.txt in this directory for details of the common
|
||||
Interrupt Controllers bindings used by client devices.
|
||||
|
||||
Example:
|
||||
|
||||
gpio@18040000 {
|
||||
compatible = "qca,ar9132-gpio", "qca,ar7100-gpio";
|
||||
reg = <0x18040000 0x30>;
|
||||
interrupts = <2>;
|
||||
|
||||
ngpios = <22>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
Ingenic SoC Interrupt Controller
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "ingenic,<socname>-intc". Valid strings are:
|
||||
ingenic,jz4740-intc
|
||||
ingenic,jz4770-intc
|
||||
ingenic,jz4775-intc
|
||||
ingenic,jz4780-intc
|
||||
- reg : Specifies base physical address and size of the registers.
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode an
|
||||
interrupt source. The value shall be 1.
|
||||
- interrupt-parent : phandle of the CPU interrupt controller.
|
||||
- interrupts : Specifies the CPU interrupt the controller is connected to.
|
||||
|
||||
Example:
|
||||
|
||||
intc: interrupt-controller@10001000 {
|
||||
compatible = "ingenic,jz4740-intc";
|
||||
reg = <0x10001000 0x14>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&cpuintc>;
|
||||
interrupts = <2>;
|
||||
};
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
Binding for Qualcomm Atheros AR7xxx/AR9XXX CPU interrupt controller
|
||||
|
||||
On most SoC the IRQ controller need to flush the DDR FIFO before running
|
||||
the interrupt handler of some devices. This is configured using the
|
||||
qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-cpu-intc"
|
||||
as fallback
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode interrupt
|
||||
source, should be 1 for intc
|
||||
|
||||
Please refer to interrupts.txt in this directory for details of the common
|
||||
Interrupt Controllers bindings used by client devices.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- qca,ddr-wb-channel-interrupts: List of the interrupts needing a write
|
||||
buffer flush
|
||||
- qca,ddr-wb-channels: List of phandles to the write buffer channels for
|
||||
each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt
|
||||
default to the entry's index.
|
||||
|
||||
Example:
|
||||
|
||||
interrupt-controller {
|
||||
compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
|
||||
qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
|
||||
<&ddr_ctrl 0>, <&ddr_ctrl 1>;
|
||||
};
|
||||
|
||||
...
|
||||
|
||||
ddr_ctrl: memory-controller@18000000 {
|
||||
...
|
||||
#qca,ddr-wb-channel-cells = <1>;
|
||||
};
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
Binding for Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller
|
||||
|
||||
The MISC interrupt controller is a secondary controller for lower priority
|
||||
interrupt.
|
||||
|
||||
Required Properties:
|
||||
- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc"
|
||||
as fallback
|
||||
- reg: Base address and size of the controllers memory area
|
||||
- interrupt-parent: phandle of the parent interrupt controller.
|
||||
- interrupts: Interrupt specifier for the controllers interrupt.
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode interrupt
|
||||
source, should be 1
|
||||
|
||||
Please refer to interrupts.txt in this directory for details of the common
|
||||
Interrupt Controllers bindings used by client devices.
|
||||
|
||||
Example:
|
||||
|
||||
interrupt-controller@18060010 {
|
||||
compatible = "qca,ar9132-misc-intc", qca,ar7100-misc-intc";
|
||||
reg = <0x18060010 0x4>;
|
||||
|
||||
interrupt-parent = <&cpuintc>;
|
||||
interrupts = <6>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
Binding for Qualcomm Atheros AR7xxx/AR9xxx DDR controller
|
||||
|
||||
The DDR controller of the ARxxx and AR9xxx families provides an interface
|
||||
to flush the FIFO between various devices and the DDR. This is mainly used
|
||||
by the IRQ controller to flush the FIFO before running the interrupt handler
|
||||
of such devices.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: has to be "qca,<soc-type>-ddr-controller",
|
||||
"qca,[ar7100|ar7240]-ddr-controller" as fallback.
|
||||
On SoC with PCI support "qca,ar7100-ddr-controller" should be used as
|
||||
fallback, otherwise "qca,ar7240-ddr-controller" should be used.
|
||||
- reg: Base address and size of the controllers memory area
|
||||
- #qca,ddr-wb-channel-cells: has to be 1, the index of the write buffer
|
||||
channel
|
||||
|
||||
Example:
|
||||
|
||||
ddr_ctrl: memory-controller@18000000 {
|
||||
compatible = "qca,ar9132-ddr-controller",
|
||||
"qca,ar7240-ddr-controller";
|
||||
reg = <0x18000000 0x100>;
|
||||
|
||||
#qca,ddr-wb-channel-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
||||
|
||||
interrupt-controller {
|
||||
...
|
||||
qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
|
||||
qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
|
||||
<&ddr_ctrl 0>, <&ddr_ctrl 1>;
|
||||
};
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
Binding for Qualcomm Atheros AR7xxx/AR9XXX SoC
|
||||
|
||||
Each device tree must specify a compatible value for the AR SoC
|
||||
it uses in the compatible property of the root node. The compatible
|
||||
value must be one of the following values:
|
||||
|
||||
- qca,ar7130
|
||||
- qca,ar7141
|
||||
- qca,ar7161
|
||||
- qca,ar7240
|
||||
- qca,ar7241
|
||||
- qca,ar7242
|
||||
- qca,ar9130
|
||||
- qca,ar9132
|
||||
- qca,ar9330
|
||||
- qca,ar9331
|
||||
- qca,ar9341
|
||||
- qca,ar9342
|
||||
- qca,ar9344
|
||||
- qca,qca9556
|
||||
- qca,qca9558
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
IMG Pistachio USB PHY
|
||||
=====================
|
||||
|
||||
Required properties:
|
||||
--------------------
|
||||
- compatible: Must be "img,pistachio-usb-phy".
|
||||
- #phy-cells: Must be 0. See ./phy-bindings.txt for details.
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
See ../clock/clock-bindings.txt for details.
|
||||
- clock-names: Must include "usb_phy".
|
||||
- img,cr-top: Must constain a phandle to the CR_TOP syscon node.
|
||||
- img,refclk: Indicates the reference clock source for the USB PHY.
|
||||
See <dt-bindings/phy/phy-pistachio-usb.h> for a list of valid values.
|
||||
|
||||
Optional properties:
|
||||
--------------------
|
||||
- phy-supply: USB VBUS supply. Must supply 5.0V.
|
||||
|
||||
Example:
|
||||
--------
|
||||
usb_phy: usb-phy {
|
||||
compatible = "img,pistachio-usb-phy";
|
||||
clocks = <&clk_core CLK_USB_PHY>;
|
||||
clock-names = "usb_phy";
|
||||
phy-supply = <&usb_vbus>;
|
||||
img,refclk = <REFCLK_CLK_CORE>;
|
||||
img,cr-top = <&cr_top>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
* Ingenic SoC UART
|
||||
|
||||
Required properties:
|
||||
- compatible : "ingenic,jz4740-uart" or "ingenic,jz4780-uart"
|
||||
- reg : offset and length of the register set for the device.
|
||||
- interrupts : should contain uart interrupt.
|
||||
- clocks : phandles to the module & baud clocks.
|
||||
- clock-names: tuple listing input clock names.
|
||||
Required elements: "baud", "module"
|
||||
|
||||
Example:
|
||||
|
||||
uart0: serial@10030000 {
|
||||
compatible = "ingenic,jz4740-uart";
|
||||
reg = <0x10030000 0x100>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <9>;
|
||||
|
||||
clocks = <&ext>, <&cgu JZ4740_CLK_UART0>;
|
||||
clock-names = "baud", "module";
|
||||
};
|
||||
|
|
@ -106,6 +106,7 @@ ibm International Business Machines (IBM)
|
|||
idt Integrated Device Technologies, Inc.
|
||||
iom Iomega Corporation
|
||||
img Imagination Technologies Ltd.
|
||||
ingenic Ingenic Semiconductor
|
||||
innolux Innolux Corporation
|
||||
intel Intel Corporation
|
||||
intercontrol Inter Control Group
|
||||
|
|
@ -161,6 +162,7 @@ powervr PowerVR (deprecated, use img)
|
|||
qca Qualcomm Atheros, Inc.
|
||||
qcom Qualcomm Technologies, Inc
|
||||
qemu QEMU, a generic and open source machine emulator and virtualizer
|
||||
qi Qi Hardware
|
||||
qnap QNAP Systems, Inc.
|
||||
radxa Radxa
|
||||
raidsonic RaidSonic Technology GmbH
|
||||
|
|
@ -206,6 +208,7 @@ tlm Trusted Logic Mobility
|
|||
toradex Toradex AG
|
||||
toshiba Toshiba Corporation
|
||||
toumaz Toumaz
|
||||
tplink TP-LINK Technologies Co., Ltd.
|
||||
truly Truly Semiconductors Limited
|
||||
usi Universal Scientific Industrial Co., Ltd.
|
||||
v3 V3 Semiconductor
|
||||
|
|
|
|||
14
MAINTAINERS
14
MAINTAINERS
|
|
@ -2229,6 +2229,14 @@ F: arch/mips/bcm3384/*
|
|||
F: arch/mips/include/asm/mach-bcm3384/*
|
||||
F: arch/mips/kernel/*bmips*
|
||||
|
||||
BROADCOM BCM47XX MIPS ARCHITECTURE
|
||||
M: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
M: Rafał Miłecki <zajec5@gmail.com>
|
||||
L: linux-mips@linux-mips.org
|
||||
S: Maintained
|
||||
F: arch/mips/bcm47xx/*
|
||||
F: arch/mips/include/asm/mach-bcm47xx/*
|
||||
|
||||
BROADCOM BCM5301X ARM ARCHITECTURE
|
||||
M: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
L: linux-arm-kernel@lists.infradead.org
|
||||
|
|
@ -2333,6 +2341,12 @@ S: Supported
|
|||
F: drivers/gpio/gpio-bcm-kona.c
|
||||
F: Documentation/devicetree/bindings/gpio/gpio-bcm-kona.txt
|
||||
|
||||
BROADCOM NVRAM DRIVER
|
||||
M: Rafał Miłecki <zajec5@gmail.com>
|
||||
L: linux-mips@linux-mips.org
|
||||
S: Maintained
|
||||
F: drivers/firmware/broadcom/*
|
||||
|
||||
BROADCOM STB NAND FLASH DRIVER
|
||||
M: Brian Norris <computersforpeace@gmail.com>
|
||||
L: linux-mtd@lists.infradead.org
|
||||
|
|
|
|||
|
|
@ -15,8 +15,8 @@ platforms += jazz
|
|||
platforms += jz4740
|
||||
platforms += lantiq
|
||||
platforms += lasat
|
||||
platforms += loongson
|
||||
platforms += loongson1
|
||||
platforms += loongson32
|
||||
platforms += loongson64
|
||||
platforms += mti-malta
|
||||
platforms += mti-sead3
|
||||
platforms += netlogic
|
||||
|
|
|
|||
|
|
@ -21,11 +21,12 @@ config MIPS
|
|||
select HAVE_FUNCTION_GRAPH_TRACER
|
||||
select HAVE_KPROBES
|
||||
select HAVE_KRETPROBES
|
||||
select HAVE_SYSCALL_TRACEPOINTS
|
||||
select HAVE_DEBUG_KMEMLEAK
|
||||
select HAVE_SYSCALL_TRACEPOINTS
|
||||
select ARCH_HAS_ELF_RANDOMIZE
|
||||
select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT
|
||||
select RTC_LIB if !MACH_LOONGSON
|
||||
select RTC_LIB if !MACH_LOONGSON64
|
||||
select GENERIC_ATOMIC64 if !64BIT
|
||||
select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
|
||||
select HAVE_DMA_ATTRS
|
||||
|
|
@ -70,7 +71,7 @@ config MIPS_ALCHEMY
|
|||
select ARCH_PHYS_ADDR_T_64BIT
|
||||
select CEVT_R4K
|
||||
select CSRC_R4K
|
||||
select IRQ_CPU
|
||||
select IRQ_MIPS_CPU
|
||||
select DMA_MAYBE_COHERENT # Au1000,1500,1100 aren't, rest is
|
||||
select SYS_HAS_CPU_MIPS32_R1
|
||||
select SYS_SUPPORTS_32BIT_KERNEL
|
||||
|
|
@ -85,7 +86,7 @@ config AR7
|
|||
select DMA_NONCOHERENT
|
||||
select CEVT_R4K
|
||||
select CSRC_R4K
|
||||
select IRQ_CPU
|
||||
select IRQ_MIPS_CPU
|
||||
select NO_EXCEPT_FILL
|
||||
select SWAP_IO_SPACE
|
||||
select SYS_HAS_CPU_MIPS32_R1
|
||||
|
|
@ -106,7 +107,7 @@ config ATH25
|
|||
select CEVT_R4K
|
||||
select CSRC_R4K
|
||||
select DMA_NONCOHERENT
|
||||
select IRQ_CPU
|
||||
select IRQ_MIPS_CPU
|
||||
select IRQ_DOMAIN
|
||||
select SYS_HAS_CPU_MIPS32_R1
|
||||
select SYS_SUPPORTS_BIG_ENDIAN
|
||||
|
|
@ -123,14 +124,17 @@ config ATH79
|
|||
select CSRC_R4K
|
||||
select DMA_NONCOHERENT
|
||||
select HAVE_CLK
|
||||
select COMMON_CLK
|
||||
select CLKDEV_LOOKUP
|
||||
select IRQ_CPU
|
||||
select IRQ_MIPS_CPU
|
||||
select MIPS_MACHINE
|
||||
select SYS_HAS_CPU_MIPS32_R2
|
||||
select SYS_HAS_EARLY_PRINTK
|
||||
select SYS_SUPPORTS_32BIT_KERNEL
|
||||
select SYS_SUPPORTS_BIG_ENDIAN
|
||||
select SYS_SUPPORTS_MIPS16
|
||||
select SYS_SUPPORTS_ZBOOT
|
||||
select USE_OF
|
||||
help
|
||||
Support for the Atheros AR71XX/AR724X/AR913X SoCs.
|
||||
|
||||
|
|
@ -146,7 +150,7 @@ config BMIPS_GENERIC
|
|||
select BCM7038_L1_IRQ
|
||||
select BCM7120_L2_IRQ
|
||||
select BRCMSTB_L2_IRQ
|
||||
select IRQ_CPU
|
||||
select IRQ_MIPS_CPU
|
||||
select RAW_IRQ_ACCESSORS
|
||||
select DMA_NONCOHERENT
|
||||
select SYS_SUPPORTS_32BIT_KERNEL
|
||||
|
|
@ -176,7 +180,7 @@ config BCM47XX
|
|||
select CSRC_R4K
|
||||
select DMA_NONCOHERENT
|
||||
select HW_HAS_PCI
|
||||
select IRQ_CPU
|
||||
select IRQ_MIPS_CPU
|
||||
select SYS_HAS_CPU_MIPS32_R1
|
||||
select NO_EXCEPT_FILL
|
||||
select SYS_SUPPORTS_32BIT_KERNEL
|
||||
|
|
@ -186,6 +190,7 @@ config BCM47XX
|
|||
select USE_GENERIC_EARLY_PRINTK_8250
|
||||
select GPIOLIB
|
||||
select LEDS_GPIO_REGISTER
|
||||
select BCM47XX_NVRAM
|
||||
help
|
||||
Support for BCM47XX based boards
|
||||
|
||||
|
|
@ -196,7 +201,7 @@ config BCM63XX
|
|||
select CSRC_R4K
|
||||
select SYNC_R4K
|
||||
select DMA_NONCOHERENT
|
||||
select IRQ_CPU
|
||||
select IRQ_MIPS_CPU
|
||||
select SYS_SUPPORTS_32BIT_KERNEL
|
||||
select SYS_SUPPORTS_BIG_ENDIAN
|
||||
select SYS_HAS_EARLY_PRINTK
|
||||
|
|
@ -216,7 +221,7 @@ config MIPS_COBALT
|
|||
select HW_HAS_PCI
|
||||
select I8253
|
||||
select I8259
|
||||
select IRQ_CPU
|
||||
select IRQ_MIPS_CPU
|
||||
select IRQ_GT641XX
|
||||
select PCI_GT64XXX_PCI0
|
||||
select PCI
|
||||
|
|
@ -239,7 +244,7 @@ config MACH_DECSTATION
|
|||
select CPU_R4400_WORKAROUNDS if 64BIT
|
||||
select DMA_NONCOHERENT
|
||||
select NO_IOPORT_MAP
|
||||
select IRQ_CPU
|
||||
select IRQ_MIPS_CPU
|
||||
select SYS_HAS_CPU_R3000
|
||||
select SYS_HAS_CPU_R4X00
|
||||
select SYS_SUPPORTS_32BIT_KERNEL
|
||||
|
|
@ -274,7 +279,7 @@ config MACH_JAZZ
|
|||
select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
|
||||
select GENERIC_ISA_DMA
|
||||
select HAVE_PCSPKR_PLATFORM
|
||||
select IRQ_CPU
|
||||
select IRQ_MIPS_CPU
|
||||
select I8253
|
||||
select I8259
|
||||
select ISA
|
||||
|
|
@ -288,23 +293,24 @@ config MACH_JAZZ
|
|||
Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
|
||||
Olivetti M700-10 workstations.
|
||||
|
||||
config MACH_JZ4740
|
||||
bool "Ingenic JZ4740 based machines"
|
||||
select SYS_HAS_CPU_MIPS32_R1
|
||||
config MACH_INGENIC
|
||||
bool "Ingenic SoC based machines"
|
||||
select SYS_SUPPORTS_32BIT_KERNEL
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
select SYS_SUPPORTS_ZBOOT_UART16550
|
||||
select DMA_NONCOHERENT
|
||||
select IRQ_CPU
|
||||
select IRQ_MIPS_CPU
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select SYS_HAS_EARLY_PRINTK
|
||||
select HAVE_CLK
|
||||
select COMMON_CLK
|
||||
select GENERIC_IRQ_CHIP
|
||||
select BUILTIN_DTB
|
||||
select USE_OF
|
||||
select LIBFDT
|
||||
|
||||
config LANTIQ
|
||||
bool "Lantiq based platforms"
|
||||
select DMA_NONCOHERENT
|
||||
select IRQ_CPU
|
||||
select IRQ_MIPS_CPU
|
||||
select CEVT_R4K
|
||||
select CSRC_R4K
|
||||
select SYS_HAS_CPU_MIPS32_R1
|
||||
|
|
@ -333,7 +339,7 @@ config LASAT
|
|||
select DMA_NONCOHERENT
|
||||
select SYS_HAS_EARLY_PRINTK
|
||||
select HW_HAS_PCI
|
||||
select IRQ_CPU
|
||||
select IRQ_MIPS_CPU
|
||||
select PCI_GT64XXX_PCI0
|
||||
select MIPS_NILE4
|
||||
select R5000_CPU_SCACHE
|
||||
|
|
@ -342,26 +348,28 @@ config LASAT
|
|||
select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
||||
config MACH_LOONGSON
|
||||
bool "Loongson family of machines"
|
||||
config MACH_LOONGSON32
|
||||
bool "Loongson-1 family of machines"
|
||||
select SYS_SUPPORTS_ZBOOT
|
||||
help
|
||||
This enables the support of Loongson family of machines.
|
||||
This enables support for the Loongson-1 family of machines.
|
||||
|
||||
Loongson is a family of general-purpose MIPS-compatible CPUs.
|
||||
developed at Institute of Computing Technology (ICT),
|
||||
Chinese Academy of Sciences (CAS) in the People's Republic
|
||||
of China. The chief architect is Professor Weiwu Hu.
|
||||
Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
|
||||
the Institute of Computing Technology (ICT), Chinese Academy of
|
||||
Sciences (CAS).
|
||||
|
||||
config MACH_LOONGSON1
|
||||
bool "Loongson 1 family of machines"
|
||||
config MACH_LOONGSON64
|
||||
bool "Loongson-2/3 family of machines"
|
||||
select SYS_SUPPORTS_ZBOOT
|
||||
help
|
||||
This enables support for the Loongson 1 based machines.
|
||||
This enables the support of Loongson-2/3 family of machines.
|
||||
|
||||
Loongson 1 is a family of 32-bit MIPS-compatible SoCs developed by
|
||||
the ICT (Institute of Computing Technology) and the Chinese Academy
|
||||
of Sciences.
|
||||
Loongson-2 is a family of single-core CPUs and Loongson-3 is a
|
||||
family of multi-core CPUs. They are both 64-bit general-purpose
|
||||
MIPS-compatible CPUs. Loongson-2/3 are developed by the Institute
|
||||
of Computing Technology (ICT), Chinese Academy of Sciences (CAS)
|
||||
in the People's Republic of China. The chief architect is Professor
|
||||
Weiwu Hu.
|
||||
|
||||
config MACH_PISTACHIO
|
||||
bool "IMG Pistachio SoC based boards"
|
||||
|
|
@ -373,7 +381,7 @@ config MACH_PISTACHIO
|
|||
select COMMON_CLK
|
||||
select CSRC_R4K
|
||||
select DMA_MAYBE_COHERENT
|
||||
select IRQ_CPU
|
||||
select IRQ_MIPS_CPU
|
||||
select LIBFDT
|
||||
select MFD_SYSCON
|
||||
select MIPS_CPU_SCACHE
|
||||
|
|
@ -386,6 +394,8 @@ config MACH_PISTACHIO
|
|||
select SYS_SUPPORTS_MIPS_CPS
|
||||
select SYS_SUPPORTS_MULTITHREADING
|
||||
select SYS_SUPPORTS_ZBOOT
|
||||
select SYS_HAS_EARLY_PRINTK
|
||||
select USE_GENERIC_EARLY_PRINTK_8250
|
||||
select USE_OF
|
||||
help
|
||||
This enables support for the IMG Pistachio SoC platform.
|
||||
|
|
@ -395,13 +405,14 @@ config MIPS_MALTA
|
|||
select ARCH_MAY_HAVE_PC_FDC
|
||||
select BOOT_ELF32
|
||||
select BOOT_RAW
|
||||
select BUILTIN_DTB
|
||||
select CEVT_R4K
|
||||
select CSRC_R4K
|
||||
select CLKSRC_MIPS_GIC
|
||||
select DMA_MAYBE_COHERENT
|
||||
select GENERIC_ISA_DMA
|
||||
select HAVE_PCSPKR_PLATFORM
|
||||
select IRQ_CPU
|
||||
select IRQ_MIPS_CPU
|
||||
select MIPS_GIC
|
||||
select HW_HAS_PCI
|
||||
select I8253
|
||||
|
|
@ -434,6 +445,8 @@ config MIPS_MALTA
|
|||
select SYS_SUPPORTS_MULTITHREADING
|
||||
select SYS_SUPPORTS_SMARTMIPS
|
||||
select SYS_SUPPORTS_ZBOOT
|
||||
select USE_OF
|
||||
select ZONE_DMA32 if 64BIT
|
||||
help
|
||||
This enables support for the MIPS Technologies Malta evaluation
|
||||
board.
|
||||
|
|
@ -449,7 +462,7 @@ config MIPS_SEAD3
|
|||
select CPU_MIPSR2_IRQ_VI
|
||||
select CPU_MIPSR2_IRQ_EI
|
||||
select DMA_NONCOHERENT
|
||||
select IRQ_CPU
|
||||
select IRQ_MIPS_CPU
|
||||
select MIPS_GIC
|
||||
select LIBFDT
|
||||
select MIPS_MSC
|
||||
|
|
@ -512,7 +525,7 @@ config PMC_MSP
|
|||
select SYS_SUPPORTS_32BIT_KERNEL
|
||||
select SYS_SUPPORTS_BIG_ENDIAN
|
||||
select SYS_SUPPORTS_MIPS16
|
||||
select IRQ_CPU
|
||||
select IRQ_MIPS_CPU
|
||||
select SERIAL_8250
|
||||
select SERIAL_8250_CONSOLE
|
||||
select USB_EHCI_BIG_ENDIAN_MMIO
|
||||
|
|
@ -529,7 +542,7 @@ config RALINK
|
|||
select CSRC_R4K
|
||||
select BOOT_RAW
|
||||
select DMA_NONCOHERENT
|
||||
select IRQ_CPU
|
||||
select IRQ_MIPS_CPU
|
||||
select USE_OF
|
||||
select SYS_HAS_CPU_MIPS32_R1
|
||||
select SYS_HAS_CPU_MIPS32_R2
|
||||
|
|
@ -555,7 +568,7 @@ config SGI_IP22
|
|||
select I8253
|
||||
select I8259
|
||||
select IP22_CPU_SCACHE
|
||||
select IRQ_CPU
|
||||
select IRQ_MIPS_CPU
|
||||
select GENERIC_ISA_DMA_SUPPORT_BROKEN
|
||||
select SGI_HAS_I8042
|
||||
select SGI_HAS_INDYDOG
|
||||
|
|
@ -614,7 +627,7 @@ config SGI_IP28
|
|||
select DEFAULT_SGI_PARTITION
|
||||
select DMA_NONCOHERENT
|
||||
select GENERIC_ISA_DMA_SUPPORT_BROKEN
|
||||
select IRQ_CPU
|
||||
select IRQ_MIPS_CPU
|
||||
select HW_HAS_EISA
|
||||
select I8253
|
||||
select I8259
|
||||
|
|
@ -650,7 +663,7 @@ config SGI_IP32
|
|||
select CSRC_R4K
|
||||
select DMA_NONCOHERENT
|
||||
select HW_HAS_PCI
|
||||
select IRQ_CPU
|
||||
select IRQ_MIPS_CPU
|
||||
select R5000_CPU_SCACHE
|
||||
select RM7000_CPU_SCACHE
|
||||
select SYS_HAS_CPU_R5000
|
||||
|
|
@ -766,7 +779,7 @@ config SNI_RM
|
|||
select HAVE_PCSPKR_PLATFORM
|
||||
select HW_HAS_EISA
|
||||
select HW_HAS_PCI
|
||||
select IRQ_CPU
|
||||
select IRQ_MIPS_CPU
|
||||
select I8253
|
||||
select I8259
|
||||
select ISA
|
||||
|
|
@ -799,7 +812,7 @@ config MIKROTIK_RB532
|
|||
select CSRC_R4K
|
||||
select DMA_NONCOHERENT
|
||||
select HW_HAS_PCI
|
||||
select IRQ_CPU
|
||||
select IRQ_MIPS_CPU
|
||||
select SYS_HAS_CPU_MIPS32_R1
|
||||
select SYS_SUPPORTS_32BIT_KERNEL
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
|
|
@ -866,7 +879,7 @@ config NLM_XLR_BOARD
|
|||
select NR_CPUS_DEFAULT_32
|
||||
select CEVT_R4K
|
||||
select CSRC_R4K
|
||||
select IRQ_CPU
|
||||
select IRQ_MIPS_CPU
|
||||
select ZONE_DMA32 if 64BIT
|
||||
select SYNC_R4K
|
||||
select SYS_HAS_EARLY_PRINTK
|
||||
|
|
@ -893,7 +906,7 @@ config NLM_XLP_BOARD
|
|||
select NR_CPUS_DEFAULT_32
|
||||
select CEVT_R4K
|
||||
select CSRC_R4K
|
||||
select IRQ_CPU
|
||||
select IRQ_MIPS_CPU
|
||||
select ZONE_DMA32 if 64BIT
|
||||
select SYNC_R4K
|
||||
select SYS_HAS_EARLY_PRINTK
|
||||
|
|
@ -942,8 +955,8 @@ source "arch/mips/sibyte/Kconfig"
|
|||
source "arch/mips/txx9/Kconfig"
|
||||
source "arch/mips/vr41xx/Kconfig"
|
||||
source "arch/mips/cavium-octeon/Kconfig"
|
||||
source "arch/mips/loongson/Kconfig"
|
||||
source "arch/mips/loongson1/Kconfig"
|
||||
source "arch/mips/loongson32/Kconfig"
|
||||
source "arch/mips/loongson64/Kconfig"
|
||||
source "arch/mips/netlogic/Kconfig"
|
||||
source "arch/mips/paravirt/Kconfig"
|
||||
|
||||
|
|
@ -1142,10 +1155,6 @@ config SYS_SUPPORTS_HUGETLBFS
|
|||
config MIPS_HUGE_TLB_SUPPORT
|
||||
def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE
|
||||
|
||||
config IRQ_CPU
|
||||
bool
|
||||
select IRQ_DOMAIN
|
||||
|
||||
config IRQ_CPU_RM7K
|
||||
bool
|
||||
|
||||
|
|
@ -1172,7 +1181,7 @@ config SOC_EMMA2RH
|
|||
select CEVT_R4K
|
||||
select CSRC_R4K
|
||||
select DMA_NONCOHERENT
|
||||
select IRQ_CPU
|
||||
select IRQ_MIPS_CPU
|
||||
select SWAP_IO_SPACE
|
||||
select SYS_HAS_CPU_R5500
|
||||
select SYS_SUPPORTS_32BIT_KERNEL
|
||||
|
|
@ -1183,7 +1192,7 @@ config SOC_PNX833X
|
|||
bool
|
||||
select CEVT_R4K
|
||||
select CSRC_R4K
|
||||
select IRQ_CPU
|
||||
select IRQ_MIPS_CPU
|
||||
select DMA_NONCOHERENT
|
||||
select SYS_HAS_CPU_MIPS32_R2
|
||||
select SYS_SUPPORTS_32BIT_KERNEL
|
||||
|
|
@ -1569,7 +1578,8 @@ config CPU_CAVIUM_OCTEON
|
|||
select WEAK_ORDERING
|
||||
select CPU_SUPPORTS_HIGHMEM
|
||||
select CPU_SUPPORTS_HUGEPAGES
|
||||
select USB_EHCI_BIG_ENDIAN_MMIO
|
||||
select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
|
||||
select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
|
||||
select MIPS_L1_CACHE_SHIFT_7
|
||||
help
|
||||
The Cavium Octeon processor is a highly integrated chip containing
|
||||
|
|
@ -1587,7 +1597,7 @@ config CPU_BMIPS
|
|||
select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
|
||||
select CPU_SUPPORTS_32BIT_KERNEL
|
||||
select DMA_NONCOHERENT
|
||||
select IRQ_CPU
|
||||
select IRQ_MIPS_CPU
|
||||
select SWAP_IO_SPACE
|
||||
select WEAK_ORDERING
|
||||
select CPU_SUPPORTS_HIGHMEM
|
||||
|
|
@ -2672,6 +2682,51 @@ config USE_OF
|
|||
config BUILTIN_DTB
|
||||
bool
|
||||
|
||||
choice
|
||||
prompt "Kernel appended dtb support" if OF
|
||||
default MIPS_NO_APPENDED_DTB
|
||||
|
||||
config MIPS_NO_APPENDED_DTB
|
||||
bool "None"
|
||||
help
|
||||
Do not enable appended dtb support.
|
||||
|
||||
config MIPS_RAW_APPENDED_DTB
|
||||
bool "vmlinux.bin"
|
||||
help
|
||||
With this option, the boot code will look for a device tree binary
|
||||
DTB) appended to raw vmlinux.bin (without decompressor).
|
||||
(e.g. cat vmlinux.bin <filename>.dtb > vmlinux_w_dtb).
|
||||
|
||||
This is meant as a backward compatibility convenience for those
|
||||
systems with a bootloader that can't be upgraded to accommodate
|
||||
the documented boot protocol using a device tree.
|
||||
|
||||
Beware that there is very little in terms of protection against
|
||||
this option being confused by leftover garbage in memory that might
|
||||
look like a DTB header after a reboot if no actual DTB is appended
|
||||
to vmlinux.bin. Do not leave this option active in a production kernel
|
||||
if you don't intend to always append a DTB.
|
||||
|
||||
config MIPS_ZBOOT_APPENDED_DTB
|
||||
bool "vmlinuz.bin"
|
||||
depends on SYS_SUPPORTS_ZBOOT
|
||||
help
|
||||
With this option, the boot code will look for a device tree binary
|
||||
DTB) appended to raw vmlinuz.bin (with decompressor).
|
||||
(e.g. cat vmlinuz.bin <filename>.dtb > vmlinuz_w_dtb).
|
||||
|
||||
This is meant as a backward compatibility convenience for those
|
||||
systems with a bootloader that can't be upgraded to accommodate
|
||||
the documented boot protocol using a device tree.
|
||||
|
||||
Beware that there is very little in terms of protection against
|
||||
this option being confused by leftover garbage in memory that might
|
||||
look like a DTB header after a reboot if no actual DTB is appended
|
||||
to vmlinuz.bin. Do not leave this option active in a production kernel
|
||||
if you don't intend to always append a DTB.
|
||||
endchoice
|
||||
|
||||
endmenu
|
||||
|
||||
config LOCKDEP_SUPPORT
|
||||
|
|
|
|||
|
|
@ -752,12 +752,12 @@ static int __init alchemy_clk_init_fgens(int ctype)
|
|||
switch (ctype) {
|
||||
case ALCHEMY_CPU_AU1000...ALCHEMY_CPU_AU1200:
|
||||
id.ops = &alchemy_clkops_fgenv1;
|
||||
id.parent_names = (const char **)alchemy_clk_fgv1_parents;
|
||||
id.parent_names = alchemy_clk_fgv1_parents;
|
||||
id.num_parents = 2;
|
||||
break;
|
||||
case ALCHEMY_CPU_AU1300:
|
||||
id.ops = &alchemy_clkops_fgenv2;
|
||||
id.parent_names = (const char **)alchemy_clk_fgv2_parents;
|
||||
id.parent_names = alchemy_clk_fgv2_parents;
|
||||
id.num_parents = 3;
|
||||
break;
|
||||
default:
|
||||
|
|
@ -961,7 +961,7 @@ static int __init alchemy_clk_setup_imux(int ctype)
|
|||
struct clk *c;
|
||||
|
||||
id.ops = &alchemy_clkops_csrc;
|
||||
id.parent_names = (const char **)alchemy_clk_csrc_parents;
|
||||
id.parent_names = alchemy_clk_csrc_parents;
|
||||
id.num_parents = 7;
|
||||
id.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE;
|
||||
|
||||
|
|
|
|||
|
|
@ -76,7 +76,7 @@ static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
|
|||
unsigned nr, misc_irq = 0;
|
||||
|
||||
if (pending) {
|
||||
struct irq_domain *domain = irq_get_handler_data(irq);
|
||||
struct irq_domain *domain = irq_desc_get_handler_data(desc);
|
||||
|
||||
nr = __ffs(pending);
|
||||
misc_irq = irq_find_mapping(domain, nr);
|
||||
|
|
|
|||
|
|
@ -80,7 +80,7 @@ static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
|
|||
unsigned nr, misc_irq = 0;
|
||||
|
||||
if (pending) {
|
||||
struct irq_domain *domain = irq_get_handler_data(irq);
|
||||
struct irq_domain *domain = irq_desc_get_handler_data(desc);
|
||||
|
||||
nr = __ffs(pending);
|
||||
misc_irq = irq_find_mapping(domain, nr);
|
||||
|
|
|
|||
|
|
@ -216,7 +216,7 @@ void __init plat_time_init(void)
|
|||
ar2315_plat_time_init();
|
||||
}
|
||||
|
||||
unsigned int __cpuinit get_c0_compare_int(void)
|
||||
unsigned int get_c0_compare_int(void)
|
||||
{
|
||||
return CP0_LEGACY_COMPARE_IRQ;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -71,6 +71,18 @@ config ATH79_MACH_UBNT_XM
|
|||
Say 'Y' here if you want your kernel to support the
|
||||
Ubiquiti Networks XM (rev 1.0) board.
|
||||
|
||||
choice
|
||||
prompt "Build a DTB in the kernel"
|
||||
optional
|
||||
help
|
||||
Select a devicetree that should be built into the kernel.
|
||||
|
||||
config DTB_TL_WR1043ND_V1
|
||||
bool "TL-WR1043ND Version 1"
|
||||
select BUILTIN_DTB
|
||||
select SOC_AR913X
|
||||
endchoice
|
||||
|
||||
endmenu
|
||||
|
||||
config SOC_AR71XX
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@
|
|||
#include <linux/err.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk-provider.h>
|
||||
|
||||
#include <asm/div64.h>
|
||||
|
||||
|
|
@ -28,24 +29,27 @@
|
|||
#define AR724X_BASE_FREQ 5000000
|
||||
#define AR913X_BASE_FREQ 5000000
|
||||
|
||||
struct clk {
|
||||
unsigned long rate;
|
||||
static struct clk *clks[3];
|
||||
static struct clk_onecell_data clk_data = {
|
||||
.clks = clks,
|
||||
.clk_num = ARRAY_SIZE(clks),
|
||||
};
|
||||
|
||||
static void __init ath79_add_sys_clkdev(const char *id, unsigned long rate)
|
||||
static struct clk *__init ath79_add_sys_clkdev(
|
||||
const char *id, unsigned long rate)
|
||||
{
|
||||
struct clk *clk;
|
||||
int err;
|
||||
|
||||
clk = kzalloc(sizeof(*clk), GFP_KERNEL);
|
||||
clk = clk_register_fixed_rate(NULL, id, NULL, CLK_IS_ROOT, rate);
|
||||
if (!clk)
|
||||
panic("failed to allocate %s clock structure", id);
|
||||
|
||||
clk->rate = rate;
|
||||
|
||||
err = clk_register_clkdev(clk, id, NULL);
|
||||
if (err)
|
||||
panic("unable to register %s clock device", id);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
static void __init ar71xx_clocks_init(void)
|
||||
|
|
@ -62,7 +66,7 @@ static void __init ar71xx_clocks_init(void)
|
|||
|
||||
pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
|
||||
|
||||
div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
|
||||
div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;
|
||||
freq = div * ref_rate;
|
||||
|
||||
div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
|
||||
|
|
@ -75,9 +79,9 @@ static void __init ar71xx_clocks_init(void)
|
|||
ahb_rate = cpu_rate / div;
|
||||
|
||||
ath79_add_sys_clkdev("ref", ref_rate);
|
||||
ath79_add_sys_clkdev("cpu", cpu_rate);
|
||||
ath79_add_sys_clkdev("ddr", ddr_rate);
|
||||
ath79_add_sys_clkdev("ahb", ahb_rate);
|
||||
clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
|
||||
clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
|
||||
clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
|
||||
|
||||
clk_add_alias("wdt", NULL, "ahb", NULL);
|
||||
clk_add_alias("uart", NULL, "ahb", NULL);
|
||||
|
|
@ -96,7 +100,7 @@ static void __init ar724x_clocks_init(void)
|
|||
ref_rate = AR724X_BASE_FREQ;
|
||||
pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
|
||||
|
||||
div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
|
||||
div = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);
|
||||
freq = div * ref_rate;
|
||||
|
||||
div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
|
||||
|
|
@ -111,9 +115,9 @@ static void __init ar724x_clocks_init(void)
|
|||
ahb_rate = cpu_rate / div;
|
||||
|
||||
ath79_add_sys_clkdev("ref", ref_rate);
|
||||
ath79_add_sys_clkdev("cpu", cpu_rate);
|
||||
ath79_add_sys_clkdev("ddr", ddr_rate);
|
||||
ath79_add_sys_clkdev("ahb", ahb_rate);
|
||||
clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
|
||||
clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
|
||||
clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
|
||||
|
||||
clk_add_alias("wdt", NULL, "ahb", NULL);
|
||||
clk_add_alias("uart", NULL, "ahb", NULL);
|
||||
|
|
@ -132,7 +136,7 @@ static void __init ar913x_clocks_init(void)
|
|||
ref_rate = AR913X_BASE_FREQ;
|
||||
pll = ath79_pll_rr(AR913X_PLL_REG_CPU_CONFIG);
|
||||
|
||||
div = ((pll >> AR913X_PLL_DIV_SHIFT) & AR913X_PLL_DIV_MASK);
|
||||
div = ((pll >> AR913X_PLL_FB_SHIFT) & AR913X_PLL_FB_MASK);
|
||||
freq = div * ref_rate;
|
||||
|
||||
cpu_rate = freq;
|
||||
|
|
@ -144,9 +148,9 @@ static void __init ar913x_clocks_init(void)
|
|||
ahb_rate = cpu_rate / div;
|
||||
|
||||
ath79_add_sys_clkdev("ref", ref_rate);
|
||||
ath79_add_sys_clkdev("cpu", cpu_rate);
|
||||
ath79_add_sys_clkdev("ddr", ddr_rate);
|
||||
ath79_add_sys_clkdev("ahb", ahb_rate);
|
||||
clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
|
||||
clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
|
||||
clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
|
||||
|
||||
clk_add_alias("wdt", NULL, "ahb", NULL);
|
||||
clk_add_alias("uart", NULL, "ahb", NULL);
|
||||
|
|
@ -206,9 +210,9 @@ static void __init ar933x_clocks_init(void)
|
|||
}
|
||||
|
||||
ath79_add_sys_clkdev("ref", ref_rate);
|
||||
ath79_add_sys_clkdev("cpu", cpu_rate);
|
||||
ath79_add_sys_clkdev("ddr", ddr_rate);
|
||||
ath79_add_sys_clkdev("ahb", ahb_rate);
|
||||
clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
|
||||
clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
|
||||
clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
|
||||
|
||||
clk_add_alias("wdt", NULL, "ahb", NULL);
|
||||
clk_add_alias("uart", NULL, "ref", NULL);
|
||||
|
|
@ -340,9 +344,9 @@ static void __init ar934x_clocks_init(void)
|
|||
ahb_rate = cpu_pll / (postdiv + 1);
|
||||
|
||||
ath79_add_sys_clkdev("ref", ref_rate);
|
||||
ath79_add_sys_clkdev("cpu", cpu_rate);
|
||||
ath79_add_sys_clkdev("ddr", ddr_rate);
|
||||
ath79_add_sys_clkdev("ahb", ahb_rate);
|
||||
clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
|
||||
clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
|
||||
clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
|
||||
|
||||
clk_add_alias("wdt", NULL, "ref", NULL);
|
||||
clk_add_alias("uart", NULL, "ref", NULL);
|
||||
|
|
@ -427,9 +431,9 @@ static void __init qca955x_clocks_init(void)
|
|||
ahb_rate = cpu_pll / (postdiv + 1);
|
||||
|
||||
ath79_add_sys_clkdev("ref", ref_rate);
|
||||
ath79_add_sys_clkdev("cpu", cpu_rate);
|
||||
ath79_add_sys_clkdev("ddr", ddr_rate);
|
||||
ath79_add_sys_clkdev("ahb", ahb_rate);
|
||||
clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
|
||||
clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
|
||||
clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
|
||||
|
||||
clk_add_alias("wdt", NULL, "ref", NULL);
|
||||
clk_add_alias("uart", NULL, "ref", NULL);
|
||||
|
|
@ -451,6 +455,8 @@ void __init ath79_clocks_init(void)
|
|||
qca955x_clocks_init();
|
||||
else
|
||||
BUG();
|
||||
|
||||
of_clk_init(NULL);
|
||||
}
|
||||
|
||||
unsigned long __init
|
||||
|
|
@ -469,22 +475,16 @@ ath79_get_sys_clk_rate(const char *id)
|
|||
return rate;
|
||||
}
|
||||
|
||||
/*
|
||||
* Linux clock API
|
||||
*/
|
||||
int clk_enable(struct clk *clk)
|
||||
#ifdef CONFIG_OF
|
||||
static void __init ath79_clocks_init_dt(struct device_node *np)
|
||||
{
|
||||
return 0;
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
}
|
||||
EXPORT_SYMBOL(clk_enable);
|
||||
|
||||
void clk_disable(struct clk *clk)
|
||||
{
|
||||
}
|
||||
EXPORT_SYMBOL(clk_disable);
|
||||
|
||||
unsigned long clk_get_rate(struct clk *clk)
|
||||
{
|
||||
return clk->rate;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_get_rate);
|
||||
CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt);
|
||||
CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt);
|
||||
CLK_OF_DECLARE(ar9130, "qca,ar9130-pll", ath79_clocks_init_dt);
|
||||
CLK_OF_DECLARE(ar9330, "qca,ar9330-pll", ath79_clocks_init_dt);
|
||||
CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt);
|
||||
CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -38,11 +38,27 @@ unsigned int ath79_soc_rev;
|
|||
void __iomem *ath79_pll_base;
|
||||
void __iomem *ath79_reset_base;
|
||||
EXPORT_SYMBOL_GPL(ath79_reset_base);
|
||||
void __iomem *ath79_ddr_base;
|
||||
static void __iomem *ath79_ddr_base;
|
||||
static void __iomem *ath79_ddr_wb_flush_base;
|
||||
static void __iomem *ath79_ddr_pci_win_base;
|
||||
|
||||
void ath79_ddr_ctrl_init(void)
|
||||
{
|
||||
ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
|
||||
AR71XX_DDR_CTRL_SIZE);
|
||||
if (soc_is_ar71xx() || soc_is_ar934x()) {
|
||||
ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c;
|
||||
ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c;
|
||||
} else {
|
||||
ath79_ddr_wb_flush_base = ath79_ddr_base + 0x7c;
|
||||
ath79_ddr_pci_win_base = 0;
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init);
|
||||
|
||||
void ath79_ddr_wb_flush(u32 reg)
|
||||
{
|
||||
void __iomem *flush_reg = ath79_ddr_base + reg;
|
||||
void __iomem *flush_reg = ath79_ddr_wb_flush_base + reg;
|
||||
|
||||
/* Flush the DDR write buffer. */
|
||||
__raw_writel(0x1, flush_reg);
|
||||
|
|
@ -56,6 +72,21 @@ void ath79_ddr_wb_flush(u32 reg)
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(ath79_ddr_wb_flush);
|
||||
|
||||
void ath79_ddr_set_pci_windows(void)
|
||||
{
|
||||
BUG_ON(!ath79_ddr_pci_win_base);
|
||||
|
||||
__raw_writel(AR71XX_PCI_WIN0_OFFS, ath79_ddr_pci_win_base + 0);
|
||||
__raw_writel(AR71XX_PCI_WIN1_OFFS, ath79_ddr_pci_win_base + 1);
|
||||
__raw_writel(AR71XX_PCI_WIN2_OFFS, ath79_ddr_pci_win_base + 2);
|
||||
__raw_writel(AR71XX_PCI_WIN3_OFFS, ath79_ddr_pci_win_base + 3);
|
||||
__raw_writel(AR71XX_PCI_WIN4_OFFS, ath79_ddr_pci_win_base + 4);
|
||||
__raw_writel(AR71XX_PCI_WIN5_OFFS, ath79_ddr_pci_win_base + 5);
|
||||
__raw_writel(AR71XX_PCI_WIN6_OFFS, ath79_ddr_pci_win_base + 6);
|
||||
__raw_writel(AR71XX_PCI_WIN7_OFFS, ath79_ddr_pci_win_base + 7);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ath79_ddr_set_pci_windows);
|
||||
|
||||
void ath79_device_reset_set(u32 mask)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
void ath79_clocks_init(void);
|
||||
unsigned long ath79_get_sys_clk_rate(const char *id);
|
||||
|
||||
void ath79_ddr_ctrl_init(void);
|
||||
void ath79_ddr_wb_flush(unsigned int reg);
|
||||
|
||||
void ath79_gpio_function_enable(u32 mask);
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/platform_data/gpio-ath79.h>
|
||||
#include <linux/serial_8250.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/err.h>
|
||||
|
|
@ -106,3 +107,53 @@ void __init ath79_register_wdt(void)
|
|||
|
||||
platform_device_register_simple("ath79-wdt", -1, &res, 1);
|
||||
}
|
||||
|
||||
static struct ath79_gpio_platform_data ath79_gpio_pdata;
|
||||
|
||||
static struct resource ath79_gpio_resources[] = {
|
||||
{
|
||||
.flags = IORESOURCE_MEM,
|
||||
.start = AR71XX_GPIO_BASE,
|
||||
.end = AR71XX_GPIO_BASE + AR71XX_GPIO_SIZE - 1,
|
||||
},
|
||||
{
|
||||
.start = ATH79_MISC_IRQ(2),
|
||||
.end = ATH79_MISC_IRQ(2),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device ath79_gpio_device = {
|
||||
.name = "ath79-gpio",
|
||||
.id = -1,
|
||||
.resource = ath79_gpio_resources,
|
||||
.num_resources = ARRAY_SIZE(ath79_gpio_resources),
|
||||
.dev = {
|
||||
.platform_data = &ath79_gpio_pdata
|
||||
},
|
||||
};
|
||||
|
||||
void __init ath79_gpio_init(void)
|
||||
{
|
||||
if (soc_is_ar71xx()) {
|
||||
ath79_gpio_pdata.ngpios = AR71XX_GPIO_COUNT;
|
||||
} else if (soc_is_ar7240()) {
|
||||
ath79_gpio_pdata.ngpios = AR7240_GPIO_COUNT;
|
||||
} else if (soc_is_ar7241() || soc_is_ar7242()) {
|
||||
ath79_gpio_pdata.ngpios = AR7241_GPIO_COUNT;
|
||||
} else if (soc_is_ar913x()) {
|
||||
ath79_gpio_pdata.ngpios = AR913X_GPIO_COUNT;
|
||||
} else if (soc_is_ar933x()) {
|
||||
ath79_gpio_pdata.ngpios = AR933X_GPIO_COUNT;
|
||||
} else if (soc_is_ar934x()) {
|
||||
ath79_gpio_pdata.ngpios = AR934X_GPIO_COUNT;
|
||||
ath79_gpio_pdata.oe_inverted = 1;
|
||||
} else if (soc_is_qca955x()) {
|
||||
ath79_gpio_pdata.ngpios = QCA955X_GPIO_COUNT;
|
||||
ath79_gpio_pdata.oe_inverted = 1;
|
||||
} else {
|
||||
BUG();
|
||||
}
|
||||
|
||||
platform_device_register(&ath79_gpio_device);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -20,13 +20,15 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/platform_data/gpio-ath79.h>
|
||||
#include <linux/of_device.h>
|
||||
|
||||
#include <asm/mach-ath79/ar71xx_regs.h>
|
||||
#include <asm/mach-ath79/ath79.h>
|
||||
#include "common.h"
|
||||
|
||||
static void __iomem *ath79_gpio_base;
|
||||
static unsigned long ath79_gpio_count;
|
||||
static u32 ath79_gpio_count;
|
||||
static DEFINE_SPINLOCK(ath79_gpio_lock);
|
||||
|
||||
static void __ath79_gpio_set_value(unsigned gpio, int value)
|
||||
|
|
@ -178,39 +180,72 @@ void ath79_gpio_function_disable(u32 mask)
|
|||
ath79_gpio_function_setup(0, mask);
|
||||
}
|
||||
|
||||
void __init ath79_gpio_init(void)
|
||||
static const struct of_device_id ath79_gpio_of_match[] = {
|
||||
{ .compatible = "qca,ar7100-gpio" },
|
||||
{ .compatible = "qca,ar9340-gpio" },
|
||||
{},
|
||||
};
|
||||
|
||||
static int ath79_gpio_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct ath79_gpio_platform_data *pdata = pdev->dev.platform_data;
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct resource *res;
|
||||
bool oe_inverted;
|
||||
int err;
|
||||
|
||||
if (soc_is_ar71xx())
|
||||
ath79_gpio_count = AR71XX_GPIO_COUNT;
|
||||
else if (soc_is_ar7240())
|
||||
ath79_gpio_count = AR7240_GPIO_COUNT;
|
||||
else if (soc_is_ar7241() || soc_is_ar7242())
|
||||
ath79_gpio_count = AR7241_GPIO_COUNT;
|
||||
else if (soc_is_ar913x())
|
||||
ath79_gpio_count = AR913X_GPIO_COUNT;
|
||||
else if (soc_is_ar933x())
|
||||
ath79_gpio_count = AR933X_GPIO_COUNT;
|
||||
else if (soc_is_ar934x())
|
||||
ath79_gpio_count = AR934X_GPIO_COUNT;
|
||||
else if (soc_is_qca955x())
|
||||
ath79_gpio_count = QCA955X_GPIO_COUNT;
|
||||
else
|
||||
BUG();
|
||||
if (np) {
|
||||
err = of_property_read_u32(np, "ngpios", &ath79_gpio_count);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "ngpios property is not valid\n");
|
||||
return err;
|
||||
}
|
||||
if (ath79_gpio_count >= 32) {
|
||||
dev_err(&pdev->dev, "ngpios must be less than 32\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
oe_inverted = of_device_is_compatible(np, "qca,ar9340-gpio");
|
||||
} else if (pdata) {
|
||||
ath79_gpio_count = pdata->ngpios;
|
||||
oe_inverted = pdata->oe_inverted;
|
||||
} else {
|
||||
dev_err(&pdev->dev, "No DT node or platform data found\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
ath79_gpio_base = devm_ioremap_nocache(
|
||||
&pdev->dev, res->start, resource_size(res));
|
||||
if (!ath79_gpio_base)
|
||||
return -ENOMEM;
|
||||
|
||||
ath79_gpio_chip.dev = &pdev->dev;
|
||||
ath79_gpio_chip.ngpio = ath79_gpio_count;
|
||||
if (soc_is_ar934x() || soc_is_qca955x()) {
|
||||
if (oe_inverted) {
|
||||
ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
|
||||
ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
|
||||
}
|
||||
|
||||
err = gpiochip_add(&ath79_gpio_chip);
|
||||
if (err)
|
||||
panic("cannot add AR71xx GPIO chip, error=%d", err);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev,
|
||||
"cannot add AR71xx GPIO chip, error=%d", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver ath79_gpio_driver = {
|
||||
.driver = {
|
||||
.name = "ath79-gpio",
|
||||
.of_match_table = ath79_gpio_of_match,
|
||||
},
|
||||
.probe = ath79_gpio_probe,
|
||||
};
|
||||
|
||||
module_platform_driver(ath79_gpio_driver);
|
||||
|
||||
int gpio_get_value(unsigned gpio)
|
||||
{
|
||||
if (gpio < ath79_gpio_count)
|
||||
|
|
|
|||
|
|
@ -15,7 +15,9 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include "../../../drivers/irqchip/irqchip.h"
|
||||
|
||||
#include <asm/irq_cpu.h>
|
||||
#include <asm/mipsregs.h>
|
||||
|
|
@ -23,9 +25,7 @@
|
|||
#include <asm/mach-ath79/ath79.h>
|
||||
#include <asm/mach-ath79/ar71xx_regs.h>
|
||||
#include "common.h"
|
||||
|
||||
static void (*ath79_ip2_handler)(void);
|
||||
static void (*ath79_ip3_handler)(void);
|
||||
#include "machtypes.h"
|
||||
|
||||
static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
|
|
@ -129,10 +129,10 @@ static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
|
|||
status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
|
||||
|
||||
if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) {
|
||||
ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_PCIE);
|
||||
ath79_ddr_wb_flush(3);
|
||||
generic_handle_irq(ATH79_IP2_IRQ(0));
|
||||
} else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
|
||||
ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_WMAC);
|
||||
ath79_ddr_wb_flush(4);
|
||||
generic_handle_irq(ATH79_IP2_IRQ(1));
|
||||
} else {
|
||||
spurious_interrupt();
|
||||
|
|
@ -235,128 +235,132 @@ static void qca955x_irq_init(void)
|
|||
irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
|
||||
}
|
||||
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned long pending;
|
||||
|
||||
pending = read_c0_status() & read_c0_cause() & ST0_IM;
|
||||
|
||||
if (pending & STATUSF_IP7)
|
||||
do_IRQ(ATH79_CPU_IRQ(7));
|
||||
|
||||
else if (pending & STATUSF_IP2)
|
||||
ath79_ip2_handler();
|
||||
|
||||
else if (pending & STATUSF_IP4)
|
||||
do_IRQ(ATH79_CPU_IRQ(4));
|
||||
|
||||
else if (pending & STATUSF_IP5)
|
||||
do_IRQ(ATH79_CPU_IRQ(5));
|
||||
|
||||
else if (pending & STATUSF_IP3)
|
||||
ath79_ip3_handler();
|
||||
|
||||
else if (pending & STATUSF_IP6)
|
||||
do_IRQ(ATH79_CPU_IRQ(6));
|
||||
|
||||
else
|
||||
spurious_interrupt();
|
||||
}
|
||||
|
||||
/*
|
||||
* The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for
|
||||
* these devices typically allocate coherent DMA memory, however the
|
||||
* DMA controller may still have some unsynchronized data in the FIFO.
|
||||
* Issue a flush in the handlers to ensure that the driver sees
|
||||
* the update.
|
||||
*
|
||||
* This array map the interrupt lines to the DDR write buffer channels.
|
||||
*/
|
||||
|
||||
static void ath79_default_ip2_handler(void)
|
||||
static unsigned irq_wb_chan[8] = {
|
||||
-1, -1, -1, -1, -1, -1, -1, -1,
|
||||
};
|
||||
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
do_IRQ(ATH79_CPU_IRQ(2));
|
||||
unsigned long pending;
|
||||
int irq;
|
||||
|
||||
pending = read_c0_status() & read_c0_cause() & ST0_IM;
|
||||
|
||||
if (!pending) {
|
||||
spurious_interrupt();
|
||||
return;
|
||||
}
|
||||
|
||||
pending >>= CAUSEB_IP;
|
||||
while (pending) {
|
||||
irq = fls(pending) - 1;
|
||||
if (irq < ARRAY_SIZE(irq_wb_chan) && irq_wb_chan[irq] != -1)
|
||||
ath79_ddr_wb_flush(irq_wb_chan[irq]);
|
||||
do_IRQ(MIPS_CPU_IRQ_BASE + irq);
|
||||
pending &= ~BIT(irq);
|
||||
}
|
||||
}
|
||||
|
||||
static void ath79_default_ip3_handler(void)
|
||||
#ifdef CONFIG_IRQCHIP
|
||||
static int misc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
|
||||
{
|
||||
do_IRQ(ATH79_CPU_IRQ(3));
|
||||
irq_set_chip_and_handler(irq, &ath79_misc_irq_chip, handle_level_irq);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ar71xx_ip2_handler(void)
|
||||
{
|
||||
ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI);
|
||||
do_IRQ(ATH79_CPU_IRQ(2));
|
||||
}
|
||||
static const struct irq_domain_ops misc_irq_domain_ops = {
|
||||
.xlate = irq_domain_xlate_onecell,
|
||||
.map = misc_map,
|
||||
};
|
||||
|
||||
static void ar724x_ip2_handler(void)
|
||||
static int __init ath79_misc_intc_of_init(
|
||||
struct device_node *node, struct device_node *parent)
|
||||
{
|
||||
ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_PCIE);
|
||||
do_IRQ(ATH79_CPU_IRQ(2));
|
||||
}
|
||||
void __iomem *base = ath79_reset_base;
|
||||
struct irq_domain *domain;
|
||||
int irq;
|
||||
|
||||
static void ar913x_ip2_handler(void)
|
||||
{
|
||||
ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_WMAC);
|
||||
do_IRQ(ATH79_CPU_IRQ(2));
|
||||
}
|
||||
irq = irq_of_parse_and_map(node, 0);
|
||||
if (!irq)
|
||||
panic("Failed to get MISC IRQ");
|
||||
|
||||
static void ar933x_ip2_handler(void)
|
||||
{
|
||||
ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_WMAC);
|
||||
do_IRQ(ATH79_CPU_IRQ(2));
|
||||
}
|
||||
domain = irq_domain_add_legacy(node, ATH79_MISC_IRQ_COUNT,
|
||||
ATH79_MISC_IRQ_BASE, 0, &misc_irq_domain_ops, NULL);
|
||||
if (!domain)
|
||||
panic("Failed to add MISC irqdomain");
|
||||
|
||||
static void ar71xx_ip3_handler(void)
|
||||
{
|
||||
ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB);
|
||||
do_IRQ(ATH79_CPU_IRQ(3));
|
||||
}
|
||||
/* Disable and clear all interrupts */
|
||||
__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
|
||||
__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
|
||||
|
||||
static void ar724x_ip3_handler(void)
|
||||
{
|
||||
ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_USB);
|
||||
do_IRQ(ATH79_CPU_IRQ(3));
|
||||
}
|
||||
|
||||
static void ar913x_ip3_handler(void)
|
||||
{
|
||||
ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_USB);
|
||||
do_IRQ(ATH79_CPU_IRQ(3));
|
||||
}
|
||||
irq_set_chained_handler(irq, ath79_misc_irq_handler);
|
||||
|
||||
static void ar933x_ip3_handler(void)
|
||||
{
|
||||
ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_USB);
|
||||
do_IRQ(ATH79_CPU_IRQ(3));
|
||||
return 0;
|
||||
}
|
||||
IRQCHIP_DECLARE(ath79_misc_intc, "qca,ar7100-misc-intc",
|
||||
ath79_misc_intc_of_init);
|
||||
|
||||
static void ar934x_ip3_handler(void)
|
||||
static int __init ar79_cpu_intc_of_init(
|
||||
struct device_node *node, struct device_node *parent)
|
||||
{
|
||||
ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_USB);
|
||||
do_IRQ(ATH79_CPU_IRQ(3));
|
||||
int err, i, count;
|
||||
|
||||
/* Fill the irq_wb_chan table */
|
||||
count = of_count_phandle_with_args(
|
||||
node, "qca,ddr-wb-channels", "#qca,ddr-wb-channel-cells");
|
||||
|
||||
for (i = 0; i < count; i++) {
|
||||
struct of_phandle_args args;
|
||||
u32 irq = i;
|
||||
|
||||
of_property_read_u32_index(
|
||||
node, "qca,ddr-wb-channel-interrupts", i, &irq);
|
||||
if (irq >= ARRAY_SIZE(irq_wb_chan))
|
||||
continue;
|
||||
|
||||
err = of_parse_phandle_with_args(
|
||||
node, "qca,ddr-wb-channels",
|
||||
"#qca,ddr-wb-channel-cells",
|
||||
i, &args);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
irq_wb_chan[irq] = args.args[0];
|
||||
pr_info("IRQ: Set flush channel of IRQ%d to %d\n",
|
||||
irq, args.args[0]);
|
||||
}
|
||||
|
||||
return mips_cpu_irq_of_init(node, parent);
|
||||
}
|
||||
IRQCHIP_DECLARE(ar79_cpu_intc, "qca,ar7100-cpu-intc",
|
||||
ar79_cpu_intc_of_init);
|
||||
|
||||
#endif
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
if (soc_is_ar71xx()) {
|
||||
ath79_ip2_handler = ar71xx_ip2_handler;
|
||||
ath79_ip3_handler = ar71xx_ip3_handler;
|
||||
} else if (soc_is_ar724x()) {
|
||||
ath79_ip2_handler = ar724x_ip2_handler;
|
||||
ath79_ip3_handler = ar724x_ip3_handler;
|
||||
} else if (soc_is_ar913x()) {
|
||||
ath79_ip2_handler = ar913x_ip2_handler;
|
||||
ath79_ip3_handler = ar913x_ip3_handler;
|
||||
} else if (soc_is_ar933x()) {
|
||||
ath79_ip2_handler = ar933x_ip2_handler;
|
||||
ath79_ip3_handler = ar933x_ip3_handler;
|
||||
if (mips_machtype == ATH79_MACH_GENERIC_OF) {
|
||||
irqchip_init();
|
||||
return;
|
||||
}
|
||||
|
||||
if (soc_is_ar71xx() || soc_is_ar724x() ||
|
||||
soc_is_ar913x() || soc_is_ar933x()) {
|
||||
irq_wb_chan[2] = 3;
|
||||
irq_wb_chan[3] = 2;
|
||||
} else if (soc_is_ar934x()) {
|
||||
ath79_ip2_handler = ath79_default_ip2_handler;
|
||||
ath79_ip3_handler = ar934x_ip3_handler;
|
||||
} else if (soc_is_qca955x()) {
|
||||
ath79_ip2_handler = ath79_default_ip2_handler;
|
||||
ath79_ip3_handler = ath79_default_ip3_handler;
|
||||
} else {
|
||||
BUG();
|
||||
irq_wb_chan[3] = 2;
|
||||
}
|
||||
|
||||
mips_cpu_irq_init();
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@
|
|||
#include <asm/mips_machine.h>
|
||||
|
||||
enum ath79_mach_type {
|
||||
ATH79_MACH_GENERIC_OF = -1, /* Device tree board */
|
||||
ATH79_MACH_GENERIC = 0,
|
||||
ATH79_MACH_AP121, /* Atheros AP121 reference board */
|
||||
ATH79_MACH_AP136_010, /* Atheros AP136-010 reference board */
|
||||
|
|
|
|||
|
|
@ -17,12 +17,16 @@
|
|||
#include <linux/bootmem.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/of_fdt.h>
|
||||
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/idle.h>
|
||||
#include <asm/time.h> /* for mips_hpt_frequency */
|
||||
#include <asm/reboot.h> /* for _machine_{restart,halt} */
|
||||
#include <asm/mips_machine.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/fw/fw.h>
|
||||
|
||||
#include <asm/mach-ath79/ath79.h>
|
||||
#include <asm/mach-ath79/ar71xx_regs.h>
|
||||
|
|
@ -194,17 +198,28 @@ unsigned int get_c0_compare_int(void)
|
|||
|
||||
void __init plat_mem_setup(void)
|
||||
{
|
||||
unsigned long fdt_start;
|
||||
|
||||
set_io_port_base(KSEG1);
|
||||
|
||||
/* Get the position of the FDT passed by the bootloader */
|
||||
fdt_start = fw_getenvl("fdt_start");
|
||||
if (fdt_start)
|
||||
__dt_setup_arch((void *)KSEG0ADDR(fdt_start));
|
||||
#ifdef CONFIG_BUILTIN_DTB
|
||||
else
|
||||
__dt_setup_arch(__dtb_start);
|
||||
#endif
|
||||
|
||||
ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
|
||||
AR71XX_RESET_SIZE);
|
||||
ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
|
||||
AR71XX_PLL_SIZE);
|
||||
ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
|
||||
AR71XX_DDR_CTRL_SIZE);
|
||||
ath79_ddr_ctrl_init();
|
||||
|
||||
ath79_detect_sys_type();
|
||||
detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
|
||||
if (mips_machtype != ATH79_MACH_GENERIC_OF)
|
||||
detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
|
||||
|
||||
_machine_restart = ath79_restart;
|
||||
_machine_halt = ath79_halt;
|
||||
|
|
@ -236,6 +251,10 @@ void __init plat_time_init(void)
|
|||
|
||||
static int __init ath79_setup(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
if (mips_machtype == ATH79_MACH_GENERIC_OF)
|
||||
return 0;
|
||||
|
||||
ath79_gpio_init();
|
||||
ath79_register_uart();
|
||||
ath79_register_wdt();
|
||||
|
|
@ -247,6 +266,11 @@ static int __init ath79_setup(void)
|
|||
|
||||
arch_initcall(ath79_setup);
|
||||
|
||||
void __init device_tree_init(void)
|
||||
{
|
||||
unflatten_and_copy_device_tree();
|
||||
}
|
||||
|
||||
static void __init ath79_generic_init(void)
|
||||
{
|
||||
/* Nothing to do */
|
||||
|
|
|
|||
|
|
@ -25,7 +25,6 @@ config BCM47XX_BCMA
|
|||
select BCMA
|
||||
select BCMA_HOST_SOC
|
||||
select BCMA_DRIVER_MIPS
|
||||
select BCMA_HOST_PCI if PCI
|
||||
select BCMA_DRIVER_PCI_HOSTMODE if PCI
|
||||
select BCMA_DRIVER_GPIO
|
||||
default y
|
||||
|
|
|
|||
|
|
@ -3,5 +3,5 @@
|
|||
# under Linux.
|
||||
#
|
||||
|
||||
obj-y += irq.o nvram.o prom.o serial.o setup.o time.o sprom.o
|
||||
obj-y += irq.o prom.o serial.o setup.o time.o sprom.o
|
||||
obj-y += board.o buttons.o leds.o workarounds.o
|
||||
|
|
|
|||
|
|
@ -149,6 +149,7 @@ struct bcm47xx_board_type_list2 bcm47xx_board_list_boot_hw[] __initconst = {
|
|||
/* board_id */
|
||||
static const
|
||||
struct bcm47xx_board_type_list1 bcm47xx_board_list_board_id[] __initconst = {
|
||||
{{BCM47XX_BOARD_LUXUL_XWR_1750_V1, "Luxul XWR-1750 V1"}, "luxul_xwr1750_v1"},
|
||||
{{BCM47XX_BOARD_NETGEAR_WGR614V8, "Netgear WGR614 V8"}, "U12H072T00_NETGEAR"},
|
||||
{{BCM47XX_BOARD_NETGEAR_WGR614V9, "Netgear WGR614 V9"}, "U12H094T00_NETGEAR"},
|
||||
{{BCM47XX_BOARD_NETGEAR_WGR614_V10, "Netgear WGR614 V10"}, "U12H139T01_NETGEAR"},
|
||||
|
|
|
|||
|
|
@ -299,6 +299,13 @@ bcm47xx_buttons_linksys_wrtsl54gs[] __initconst = {
|
|||
BCM47XX_GPIO_KEY(6, KEY_RESTART),
|
||||
};
|
||||
|
||||
/* Luxul */
|
||||
|
||||
static const struct gpio_keys_button
|
||||
bcm47xx_buttons_luxul_xwr_1750_v1[] = {
|
||||
BCM47XX_GPIO_KEY(14, BTN_TASK),
|
||||
};
|
||||
|
||||
/* Microsoft */
|
||||
|
||||
static const struct gpio_keys_button
|
||||
|
|
@ -555,6 +562,10 @@ int __init bcm47xx_buttons_register(void)
|
|||
err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrtsl54gs);
|
||||
break;
|
||||
|
||||
case BCM47XX_BOARD_LUXUL_XWR_1750_V1:
|
||||
err = bcm47xx_copy_bdata(bcm47xx_buttons_luxul_xwr_1750_v1);
|
||||
break;
|
||||
|
||||
case BCM47XX_BOARD_MICROSOFT_MN700:
|
||||
err = bcm47xx_copy_bdata(bcm47xx_buttons_microsoft_nm700);
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -370,6 +370,16 @@ bcm47xx_leds_linksys_wrtsl54gs[] __initconst = {
|
|||
BCM47XX_GPIO_LED(7, "orange", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
|
||||
};
|
||||
|
||||
/* Luxul */
|
||||
|
||||
static const struct gpio_led
|
||||
bcm47xx_leds_luxul_xwr_1750_v1[] __initconst = {
|
||||
BCM47XX_GPIO_LED(5, "green", "5ghz", 0, LEDS_GPIO_DEFSTATE_OFF),
|
||||
BCM47XX_GPIO_LED(12, "green", "usb", 0, LEDS_GPIO_DEFSTATE_OFF),
|
||||
BCM47XX_GPIO_LED_TRIGGER(13, "green", "status", 0, "timer"),
|
||||
BCM47XX_GPIO_LED(15, "green", "wps", 0, LEDS_GPIO_DEFSTATE_OFF),
|
||||
};
|
||||
|
||||
/* Microsoft */
|
||||
|
||||
static const struct gpio_led
|
||||
|
|
@ -623,6 +633,10 @@ void __init bcm47xx_leds_register(void)
|
|||
bcm47xx_set_pdata(bcm47xx_leds_linksys_wrtsl54gs);
|
||||
break;
|
||||
|
||||
case BCM47XX_BOARD_LUXUL_XWR_1750_V1:
|
||||
bcm47xx_set_pdata(bcm47xx_leds_luxul_xwr_1750_v1);
|
||||
break;
|
||||
|
||||
case BCM47XX_BOARD_MICROSOFT_MN700:
|
||||
bcm47xx_set_pdata(bcm47xx_leds_microsoft_nm700);
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -126,7 +126,7 @@ void __init prom_free_prom_memory(void)
|
|||
/* Stripped version of tlb_init, with the call to build_tlb_refill_handler
|
||||
* dropped. Calling it at this stage causes a hang.
|
||||
*/
|
||||
void __cpuinit early_tlb_init(void)
|
||||
void early_tlb_init(void)
|
||||
{
|
||||
write_c0_pagemask(PM_DEFAULT_MASK);
|
||||
write_c0_wired(0);
|
||||
|
|
|
|||
|
|
@ -206,9 +206,6 @@ void __init bcm47xx_bus_setup(void)
|
|||
err = bcma_host_soc_init(&bcm47xx_bus.bcma);
|
||||
if (err)
|
||||
panic("Failed to initialize BCMA bus (err %d)", err);
|
||||
|
||||
bcm47xx_fill_bcma_boardinfo(&bcm47xx_bus.bcma.bus.boardinfo,
|
||||
NULL);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -200,7 +200,13 @@ static void bcm47xx_sprom_fill_auto(struct ssb_sprom *sprom,
|
|||
const char *pre = prefix;
|
||||
bool fb = fallback;
|
||||
|
||||
/* Broadcom extracts it for rev 8+ but it was found on 2 and 4 too */
|
||||
ENTRY(0xfffffffe, u16, pre, "devid", dev_id, 0, fallback);
|
||||
|
||||
ENTRY(0xfffffffe, u16, pre, "boardrev", board_rev, 0, true);
|
||||
ENTRY(0xfffffffe, u32, pre, "boardflags", boardflags, 0, fb);
|
||||
ENTRY(0xfffffff0, u32, pre, "boardflags2", boardflags2, 0, fb);
|
||||
ENTRY(0xfffff800, u32, pre, "boardflags3", boardflags3, 0, fb);
|
||||
ENTRY(0x00000002, u16, pre, "boardflags", boardflags_lo, 0, fb);
|
||||
ENTRY(0xfffffffc, u16, pre, "boardtype", board_type, 0, true);
|
||||
ENTRY(0xfffffffe, u16, pre, "boardnum", board_num, 0, fb);
|
||||
|
|
@ -409,27 +415,6 @@ static void bcm47xx_sprom_fill_auto(struct ssb_sprom *sprom,
|
|||
}
|
||||
#undef ENTRY /* It's specififc, uses local variable, don't use it (again). */
|
||||
|
||||
static void bcm47xx_fill_sprom_r1234589(struct ssb_sprom *sprom,
|
||||
const char *prefix, bool fallback)
|
||||
{
|
||||
nvram_read_u16(prefix, NULL, "devid", &sprom->dev_id, 0, fallback);
|
||||
nvram_read_alpha2(prefix, "ccode", sprom->alpha2, fallback);
|
||||
}
|
||||
|
||||
static void bcm47xx_fill_sprom_r3(struct ssb_sprom *sprom, const char *prefix,
|
||||
bool fallback)
|
||||
{
|
||||
nvram_read_leddc(prefix, "leddc", &sprom->leddc_on_time,
|
||||
&sprom->leddc_off_time, fallback);
|
||||
}
|
||||
|
||||
static void bcm47xx_fill_sprom_r4589(struct ssb_sprom *sprom,
|
||||
const char *prefix, bool fallback)
|
||||
{
|
||||
nvram_read_leddc(prefix, "leddc", &sprom->leddc_on_time,
|
||||
&sprom->leddc_off_time, fallback);
|
||||
}
|
||||
|
||||
static void bcm47xx_fill_sprom_path_r4589(struct ssb_sprom *sprom,
|
||||
const char *prefix, bool fallback)
|
||||
{
|
||||
|
|
@ -528,6 +513,8 @@ static int mac_addr_used = 2;
|
|||
static void bcm47xx_fill_sprom_ethernet(struct ssb_sprom *sprom,
|
||||
const char *prefix, bool fallback)
|
||||
{
|
||||
bool fb = fallback;
|
||||
|
||||
nvram_read_macaddr(prefix, "et0macaddr", sprom->et0mac, fallback);
|
||||
nvram_read_u8(prefix, NULL, "et0mdcport", &sprom->et0mdcport, 0,
|
||||
fallback);
|
||||
|
|
@ -540,6 +527,10 @@ static void bcm47xx_fill_sprom_ethernet(struct ssb_sprom *sprom,
|
|||
nvram_read_u8(prefix, NULL, "et1phyaddr", &sprom->et1phyaddr, 0,
|
||||
fallback);
|
||||
|
||||
nvram_read_macaddr(prefix, "et2macaddr", sprom->et2mac, fb);
|
||||
nvram_read_u8(prefix, NULL, "et2mdcport", &sprom->et2mdcport, 0, fb);
|
||||
nvram_read_u8(prefix, NULL, "et2phyaddr", &sprom->et2phyaddr, 0, fb);
|
||||
|
||||
nvram_read_macaddr(prefix, "macaddr", sprom->il0mac, fallback);
|
||||
nvram_read_macaddr(prefix, "il0macaddr", sprom->il0mac, fallback);
|
||||
|
||||
|
|
@ -580,39 +571,22 @@ void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix,
|
|||
|
||||
nvram_read_u8(prefix, NULL, "sromrev", &sprom->revision, 0, fallback);
|
||||
|
||||
/* Entries requiring custom functions */
|
||||
nvram_read_alpha2(prefix, "ccode", sprom->alpha2, fallback);
|
||||
if (sprom->revision >= 3)
|
||||
nvram_read_leddc(prefix, "leddc", &sprom->leddc_on_time,
|
||||
&sprom->leddc_off_time, fallback);
|
||||
|
||||
switch (sprom->revision) {
|
||||
case 1:
|
||||
bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback);
|
||||
break;
|
||||
case 2:
|
||||
bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback);
|
||||
break;
|
||||
case 3:
|
||||
bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_r3(sprom, prefix, fallback);
|
||||
break;
|
||||
case 4:
|
||||
case 5:
|
||||
bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_r4589(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_path_r4589(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_path_r45(sprom, prefix, fallback);
|
||||
break;
|
||||
case 8:
|
||||
bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_r4589(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_path_r4589(sprom, prefix, fallback);
|
||||
break;
|
||||
case 9:
|
||||
bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_r4589(sprom, prefix, fallback);
|
||||
bcm47xx_fill_sprom_path_r4589(sprom, prefix, fallback);
|
||||
break;
|
||||
default:
|
||||
pr_warn("Unsupported SPROM revision %d detected. Will extract v1\n",
|
||||
sprom->revision);
|
||||
sprom->revision = 1;
|
||||
bcm47xx_fill_sprom_r1234589(sprom, prefix, fallback);
|
||||
}
|
||||
|
||||
bcm47xx_sprom_fill_auto(sprom, prefix, fallback);
|
||||
|
|
@ -631,19 +605,6 @@ void bcm47xx_fill_ssb_boardinfo(struct ssb_boardinfo *boardinfo,
|
|||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BCM47XX_BCMA
|
||||
void bcm47xx_fill_bcma_boardinfo(struct bcma_boardinfo *boardinfo,
|
||||
const char *prefix)
|
||||
{
|
||||
nvram_read_u16(prefix, NULL, "boardvendor", &boardinfo->vendor, 0,
|
||||
true);
|
||||
if (!boardinfo->vendor)
|
||||
boardinfo->vendor = SSB_BOARDVENDOR_BCM;
|
||||
|
||||
nvram_read_u16(prefix, NULL, "boardtype", &boardinfo->type, 0, true);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BCM47XX_SSB)
|
||||
static int bcm47xx_get_sprom_ssb(struct ssb_bus *bus, struct ssb_sprom *out)
|
||||
{
|
||||
|
|
@ -698,33 +659,46 @@ static void bcm47xx_sprom_apply_prefix_alias(char *prefix, size_t prefix_size)
|
|||
|
||||
static int bcm47xx_get_sprom_bcma(struct bcma_bus *bus, struct ssb_sprom *out)
|
||||
{
|
||||
char prefix[10];
|
||||
struct bcma_boardinfo *binfo = &bus->boardinfo;
|
||||
struct bcma_device *core;
|
||||
char buf[10];
|
||||
char *prefix;
|
||||
bool fallback = false;
|
||||
|
||||
switch (bus->hosttype) {
|
||||
case BCMA_HOSTTYPE_PCI:
|
||||
memset(out, 0, sizeof(struct ssb_sprom));
|
||||
snprintf(prefix, sizeof(prefix), "pci/%u/%u/",
|
||||
snprintf(buf, sizeof(buf), "pci/%u/%u/",
|
||||
bus->host_pci->bus->number + 1,
|
||||
PCI_SLOT(bus->host_pci->devfn));
|
||||
bcm47xx_sprom_apply_prefix_alias(prefix, sizeof(prefix));
|
||||
bcm47xx_fill_sprom(out, prefix, false);
|
||||
return 0;
|
||||
bcm47xx_sprom_apply_prefix_alias(buf, sizeof(buf));
|
||||
prefix = buf;
|
||||
break;
|
||||
case BCMA_HOSTTYPE_SOC:
|
||||
memset(out, 0, sizeof(struct ssb_sprom));
|
||||
core = bcma_find_core(bus, BCMA_CORE_80211);
|
||||
if (core) {
|
||||
snprintf(prefix, sizeof(prefix), "sb/%u/",
|
||||
snprintf(buf, sizeof(buf), "sb/%u/",
|
||||
core->core_index);
|
||||
bcm47xx_fill_sprom(out, prefix, true);
|
||||
prefix = buf;
|
||||
fallback = true;
|
||||
} else {
|
||||
bcm47xx_fill_sprom(out, NULL, false);
|
||||
prefix = NULL;
|
||||
}
|
||||
return 0;
|
||||
break;
|
||||
default:
|
||||
pr_warn("Unable to fill SPROM for given bustype.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
nvram_read_u16(prefix, NULL, "boardvendor", &binfo->vendor, 0, true);
|
||||
if (!binfo->vendor)
|
||||
binfo->vendor = SSB_BOARDVENDOR_BCM;
|
||||
nvram_read_u16(prefix, NULL, "boardtype", &binfo->type, 0, true);
|
||||
|
||||
bcm47xx_fill_sprom(out, prefix, fallback);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -57,6 +57,10 @@ config DT_BCM97425SVMB
|
|||
bool "BCM97425SVMB"
|
||||
select BUILTIN_DTB
|
||||
|
||||
config DT_BCM97435SVMB
|
||||
bool "BCM97435SVMB"
|
||||
select BUILTIN_DTB
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -149,6 +149,8 @@ void __init plat_mem_setup(void)
|
|||
/* intended to somewhat resemble ARM; see Documentation/arm/Booting */
|
||||
if (fw_arg0 == 0 && fw_arg1 == 0xffffffff)
|
||||
dtb = phys_to_virt(fw_arg2);
|
||||
else if (fw_arg0 == -2) /* UHI interface */
|
||||
dtb = (void *)fw_arg1;
|
||||
else if (__dtb_start != __dtb_end)
|
||||
dtb = (void *)__dtb_start;
|
||||
else
|
||||
|
|
|
|||
|
|
@ -25,6 +25,22 @@ start:
|
|||
move s2, a2
|
||||
move s3, a3
|
||||
|
||||
#ifdef CONFIG_MIPS_ZBOOT_APPENDED_DTB
|
||||
PTR_LA t0, __appended_dtb
|
||||
#ifdef CONFIG_CPU_BIG_ENDIAN
|
||||
li t1, 0xd00dfeed
|
||||
#else
|
||||
li t1, 0xedfe0dd0
|
||||
#endif
|
||||
lw t2, (t0)
|
||||
bne t1, t2, not_found
|
||||
nop
|
||||
|
||||
move s1, t0
|
||||
PTR_LI s0, -2
|
||||
not_found:
|
||||
#endif
|
||||
|
||||
/* Clear BSS */
|
||||
PTR_LA a0, _edata
|
||||
PTR_LA a2, _end
|
||||
|
|
|
|||
|
|
@ -29,8 +29,12 @@ SECTIONS
|
|||
*(.image)
|
||||
__image_end = .;
|
||||
CONSTRUCTORS
|
||||
. = ALIGN(16);
|
||||
}
|
||||
. = ALIGN(16);
|
||||
__appended_dtb = .;
|
||||
/* leave space for appended DTB */
|
||||
. += 0x100000;
|
||||
|
||||
_edata = .;
|
||||
/* End of data section */
|
||||
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
|
||||
#include <asm/addrspace.h>
|
||||
|
||||
#if defined(CONFIG_MACH_LOONGSON) || defined(CONFIG_MIPS_MALTA)
|
||||
#if defined(CONFIG_MACH_LOONGSON64) || defined(CONFIG_MIPS_MALTA)
|
||||
#define UART_BASE 0x1fd003f8
|
||||
#define PORT(offset) (CKSEG1ADDR(UART_BASE) + (offset))
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,8 +1,10 @@
|
|||
dts-dirs += brcm
|
||||
dts-dirs += cavium-octeon
|
||||
dts-dirs += ingenic
|
||||
dts-dirs += lantiq
|
||||
dts-dirs += mti
|
||||
dts-dirs += netlogic
|
||||
dts-dirs += qca
|
||||
dts-dirs += ralink
|
||||
|
||||
obj-y := $(addsuffix /, $(dts-dirs))
|
||||
|
|
|
|||
|
|
@ -9,6 +9,20 @@ dtb-$(CONFIG_DT_BCM97360SVMB) += bcm97360svmb.dtb
|
|||
dtb-$(CONFIG_DT_BCM97362SVMB) += bcm97362svmb.dtb
|
||||
dtb-$(CONFIG_DT_BCM97420C) += bcm97420c.dtb
|
||||
dtb-$(CONFIG_DT_BCM97425SVMB) += bcm97425svmb.dtb
|
||||
dtb-$(CONFIG_DT_BCM97435SVMB) += bcm97435svmb.dtb
|
||||
|
||||
dtb-$(CONFIG_DT_NONE) += \
|
||||
bcm93384wvg.dtb \
|
||||
bcm93384wvg_viper.dtb \
|
||||
bcm96368mvwg.dtb \
|
||||
bcm9ejtagprb.dtb \
|
||||
bcm97125cbmb.dtb \
|
||||
bcm97346dbsmb.dtb \
|
||||
bcm97358svmb.dtb \
|
||||
bcm97360svmb.dtb \
|
||||
bcm97362svmb.dtb \
|
||||
bcm97420c.dtb \
|
||||
bcm97425svmb.dtb
|
||||
|
||||
obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
|
||||
|
||||
|
|
|
|||
|
|
@ -24,6 +24,8 @@
|
|||
|
||||
aliases {
|
||||
uart0 = &uart0;
|
||||
uart1 = &uart1;
|
||||
uart2 = &uart2;
|
||||
};
|
||||
|
||||
cpu_intc: cpu_intc {
|
||||
|
|
@ -118,6 +120,30 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@406940 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x406940 0x20>;
|
||||
reg-io-width = <0x4>;
|
||||
reg-shift = <0x2>;
|
||||
native-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <65>;
|
||||
clocks = <&uart_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@406980 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x406980 0x20>;
|
||||
reg-io-width = <0x4>;
|
||||
reg-shift = <0x2>;
|
||||
native-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <66>;
|
||||
clocks = <&uart_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
enet0: ethernet@430000 {
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy1>;
|
||||
|
|
|
|||
|
|
@ -18,6 +18,8 @@
|
|||
|
||||
aliases {
|
||||
uart0 = &uart0;
|
||||
uart1 = &uart1;
|
||||
uart2 = &uart2;
|
||||
};
|
||||
|
||||
cpu_intc: cpu_intc {
|
||||
|
|
@ -112,6 +114,30 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@406840 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x406840 0x20>;
|
||||
reg-io-width = <0x4>;
|
||||
reg-shift = <0x2>;
|
||||
native-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <62>;
|
||||
clocks = <&uart_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@406880 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x406880 0x20>;
|
||||
reg-io-width = <0x4>;
|
||||
reg-shift = <0x2>;
|
||||
native-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <63>;
|
||||
clocks = <&uart_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
enet0: ethernet@430000 {
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy1>;
|
||||
|
|
|
|||
|
|
@ -18,6 +18,8 @@
|
|||
|
||||
aliases {
|
||||
uart0 = &uart0;
|
||||
uart1 = &uart1;
|
||||
uart2 = &uart2;
|
||||
};
|
||||
|
||||
cpu_intc: cpu_intc {
|
||||
|
|
@ -112,6 +114,30 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@406840 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x406840 0x20>;
|
||||
reg-io-width = <0x4>;
|
||||
reg-shift = <0x2>;
|
||||
native-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <62>;
|
||||
clocks = <&uart_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@406880 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x406880 0x20>;
|
||||
reg-io-width = <0x4>;
|
||||
reg-shift = <0x2>;
|
||||
native-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <63>;
|
||||
clocks = <&uart_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
enet0: ethernet@430000 {
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy1>;
|
||||
|
|
|
|||
|
|
@ -24,6 +24,8 @@
|
|||
|
||||
aliases {
|
||||
uart0 = &uart0;
|
||||
uart1 = &uart1;
|
||||
uart2 = &uart2;
|
||||
};
|
||||
|
||||
cpu_intc: cpu_intc {
|
||||
|
|
@ -118,6 +120,30 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@406840 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x406840 0x20>;
|
||||
reg-io-width = <0x4>;
|
||||
reg-shift = <0x2>;
|
||||
native-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <62>;
|
||||
clocks = <&uart_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@406880 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x406880 0x20>;
|
||||
reg-io-width = <0x4>;
|
||||
reg-shift = <0x2>;
|
||||
native-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <63>;
|
||||
clocks = <&uart_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
enet0: ethernet@430000 {
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy1>;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,239 @@
|
|||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "brcm,bcm7435";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mips-hpt-frequency = <163125000>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "brcm,bmips5200";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "brcm,bmips5200";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
cpu@2 {
|
||||
compatible = "brcm,bmips5200";
|
||||
device_type = "cpu";
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
cpu@3 {
|
||||
compatible = "brcm,bmips5200";
|
||||
device_type = "cpu";
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
uart0 = &uart0;
|
||||
};
|
||||
|
||||
cpu_intc: cpu_intc {
|
||||
#address-cells = <0>;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
uart_clk: uart_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <81000000>;
|
||||
};
|
||||
};
|
||||
|
||||
rdb {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
compatible = "simple-bus";
|
||||
ranges = <0 0x10000000 0x01000000>;
|
||||
|
||||
periph_intc: periph_intc@41b500 {
|
||||
compatible = "brcm,bcm7038-l1-intc";
|
||||
reg = <0x41b500 0x40>, <0x41b600 0x40>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&cpu_intc>;
|
||||
interrupts = <2>, <3>;
|
||||
};
|
||||
|
||||
sun_l2_intc: sun_l2_intc@403000 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x403000 0x30>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <52>;
|
||||
};
|
||||
|
||||
gisb-arb@400000 {
|
||||
compatible = "brcm,bcm7400-gisb-arb";
|
||||
reg = <0x400000 0xdc>;
|
||||
native-endian;
|
||||
interrupt-parent = <&sun_l2_intc>;
|
||||
interrupts = <0>, <2>;
|
||||
brcm,gisb-arb-master-mask = <0xf77f>;
|
||||
brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "webcpu_0",
|
||||
"pcie_0", "bsp_0",
|
||||
"rdc_0", "raaga_0",
|
||||
"avd_1", "jtag_0",
|
||||
"svd_0", "vice_0",
|
||||
"vice_1", "raaga_1",
|
||||
"scpu";
|
||||
};
|
||||
|
||||
upg_irq0_intc: upg_irq0_intc@406780 {
|
||||
compatible = "brcm,bcm7120-l2-intc";
|
||||
reg = <0x406780 0x8>;
|
||||
|
||||
brcm,int-map-mask = <0x44>;
|
||||
brcm,int-fwd-mask = <0x70000>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <60>;
|
||||
};
|
||||
|
||||
sun_top_ctrl: syscon@404000 {
|
||||
compatible = "brcm,bcm7425-sun-top-ctrl", "syscon";
|
||||
reg = <0x404000 0x51c>;
|
||||
little-endian;
|
||||
};
|
||||
|
||||
reboot {
|
||||
compatible = "brcm,brcmstb-reboot";
|
||||
syscon = <&sun_top_ctrl 0x304 0x308>;
|
||||
};
|
||||
|
||||
uart0: serial@406b00 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x406b00 0x20>;
|
||||
reg-io-width = <0x4>;
|
||||
reg-shift = <0x2>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <66>;
|
||||
clocks = <&uart_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
enet0: ethernet@b80000 {
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy1>;
|
||||
mac-address = [ 00 10 18 36 23 1a ];
|
||||
compatible = "brcm,genet-v3";
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
reg = <0xb80000 0x11c88>;
|
||||
interrupts = <17>, <18>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
status = "disabled";
|
||||
|
||||
mdio@e14 {
|
||||
compatible = "brcm,genet-mdio-v3";
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
reg = <0xe14 0x8>;
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
max-speed = <100>;
|
||||
reg = <0x1>;
|
||||
compatible = "brcm,40nm-ephy",
|
||||
"ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ehci0: usb@480300 {
|
||||
compatible = "brcm,bcm7435-ehci", "generic-ehci";
|
||||
reg = <0x480300 0x100>;
|
||||
native-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <70>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci0: usb@480400 {
|
||||
compatible = "brcm,bcm7435-ohci", "generic-ohci";
|
||||
reg = <0x480400 0x100>;
|
||||
native-endian;
|
||||
no-big-frame-no;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <72>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci1: usb@480500 {
|
||||
compatible = "brcm,bcm7435-ehci", "generic-ehci";
|
||||
reg = <0x480500 0x100>;
|
||||
native-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <71>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci1: usb@480600 {
|
||||
compatible = "brcm,bcm7435-ohci", "generic-ohci";
|
||||
reg = <0x480600 0x100>;
|
||||
native-endian;
|
||||
no-big-frame-no;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <73>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci2: usb@490300 {
|
||||
compatible = "brcm,bcm7435-ehci", "generic-ehci";
|
||||
reg = <0x490300 0x100>;
|
||||
native-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <75>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci2: usb@490400 {
|
||||
compatible = "brcm,bcm7435-ohci", "generic-ohci";
|
||||
reg = <0x490400 0x100>;
|
||||
native-endian;
|
||||
no-big-frame-no;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <77>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci3: usb@490500 {
|
||||
compatible = "brcm,bcm7435-ehci", "generic-ehci";
|
||||
reg = <0x490500 0x100>;
|
||||
native-endian;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <76>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci3: usb@490600 {
|
||||
compatible = "brcm,bcm7435-ohci", "generic-ohci";
|
||||
reg = <0x490600 0x100>;
|
||||
native-endian;
|
||||
no-big-frame-no;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <78>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -21,6 +21,14 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enet0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -21,6 +21,14 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enet0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -21,6 +21,14 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enet0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -21,6 +21,14 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enet0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,60 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "bcm7435.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm97435svmb", "brcm,bcm7435";
|
||||
model = "Broadcom BCM97435SVMB";
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x10000000>,
|
||||
<0x20000000 0x30000000>,
|
||||
<0x90000000 0x40000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 maxcpus=1";
|
||||
stdout-path = &uart0;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enet0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
dtb-$(CONFIG_JZ4740_QI_LB60) += qi_lb60.dtb
|
||||
dtb-$(CONFIG_JZ4780_CI20) += ci20.dtb
|
||||
|
||||
obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
|
||||
|
||||
# Force kbuild to make empty built-in.o if necessary
|
||||
obj- += dummy.o
|
||||
|
||||
always := $(dtb-y)
|
||||
clean-files := *.dtb *.dtb.S
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "jz4780.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "img,ci20", "ingenic,jz4780";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial3 = &uart3;
|
||||
serial4 = &uart4;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart4;
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x10000000
|
||||
0x30000000 0x30000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&ext {
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
#include <dt-bindings/clock/jz4740-cgu.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "ingenic,jz4740";
|
||||
|
||||
cpuintc: interrupt-controller@0 {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
};
|
||||
|
||||
intc: interrupt-controller@10001000 {
|
||||
compatible = "ingenic,jz4740-intc";
|
||||
reg = <0x10001000 0x14>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&cpuintc>;
|
||||
interrupts = <2>;
|
||||
};
|
||||
|
||||
ext: ext {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
rtc: rtc {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
cgu: jz4740-cgu@10000000 {
|
||||
compatible = "ingenic,jz4740-cgu";
|
||||
reg = <0x10000000 0x100>;
|
||||
|
||||
clocks = <&ext>, <&rtc>;
|
||||
clock-names = "ext", "rtc";
|
||||
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
uart0: serial@10030000 {
|
||||
compatible = "ingenic,jz4740-uart";
|
||||
reg = <0x10030000 0x100>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <9>;
|
||||
|
||||
clocks = <&ext>, <&cgu JZ4740_CLK_UART0>;
|
||||
clock-names = "baud", "module";
|
||||
};
|
||||
|
||||
uart1: serial@10031000 {
|
||||
compatible = "ingenic,jz4740-uart";
|
||||
reg = <0x10031000 0x100>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <8>;
|
||||
|
||||
clocks = <&ext>, <&cgu JZ4740_CLK_UART1>;
|
||||
clock-names = "baud", "module";
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,111 @@
|
|||
#include <dt-bindings/clock/jz4780-cgu.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "ingenic,jz4780";
|
||||
|
||||
cpuintc: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
};
|
||||
|
||||
intc: interrupt-controller@10001000 {
|
||||
compatible = "ingenic,jz4780-intc";
|
||||
reg = <0x10001000 0x50>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&cpuintc>;
|
||||
interrupts = <2>;
|
||||
};
|
||||
|
||||
ext: ext {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
rtc: rtc {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
cgu: jz4780-cgu@10000000 {
|
||||
compatible = "ingenic,jz4780-cgu";
|
||||
reg = <0x10000000 0x100>;
|
||||
|
||||
clocks = <&ext>, <&rtc>;
|
||||
clock-names = "ext", "rtc";
|
||||
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
uart0: serial@10030000 {
|
||||
compatible = "ingenic,jz4780-uart";
|
||||
reg = <0x10030000 0x100>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <51>;
|
||||
|
||||
clocks = <&ext>, <&cgu JZ4780_CLK_UART0>;
|
||||
clock-names = "baud", "module";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@10031000 {
|
||||
compatible = "ingenic,jz4780-uart";
|
||||
reg = <0x10031000 0x100>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <50>;
|
||||
|
||||
clocks = <&ext>, <&cgu JZ4780_CLK_UART1>;
|
||||
clock-names = "baud", "module";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@10032000 {
|
||||
compatible = "ingenic,jz4780-uart";
|
||||
reg = <0x10032000 0x100>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <49>;
|
||||
|
||||
clocks = <&ext>, <&cgu JZ4780_CLK_UART2>;
|
||||
clock-names = "baud", "module";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@10033000 {
|
||||
compatible = "ingenic,jz4780-uart";
|
||||
reg = <0x10033000 0x100>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <48>;
|
||||
|
||||
clocks = <&ext>, <&cgu JZ4780_CLK_UART3>;
|
||||
clock-names = "baud", "module";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@10034000 {
|
||||
compatible = "ingenic,jz4780-uart";
|
||||
reg = <0x10034000 0x100>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <34>;
|
||||
|
||||
clocks = <&ext>, <&cgu JZ4780_CLK_UART4>;
|
||||
clock-names = "baud", "module";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include "jz4740.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "qi,lb60", "ingenic,jz4740";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart0;
|
||||
};
|
||||
};
|
||||
|
||||
&ext {
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
|
|
@ -1,3 +1,4 @@
|
|||
dtb-$(CONFIG_MIPS_MALTA) += malta.dtb
|
||||
dtb-$(CONFIG_MIPS_SEAD3) += sead3.dtb
|
||||
|
||||
obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
|
||||
|
|
|
|||
|
|
@ -0,0 +1,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "mti,malta";
|
||||
};
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
# All DTBs
|
||||
dtb-$(CONFIG_ATH79) += ar9132_tl_wr1043nd_v1.dtb
|
||||
|
||||
# Select a DTB to build in the kernel
|
||||
obj-$(CONFIG_DTB_TL_WR1043ND_V1) += ar9132_tl_wr1043nd_v1.dtb.o
|
||||
|
||||
# Force kbuild to make empty built-in.o if necessary
|
||||
obj- += dummy.o
|
||||
|
||||
always := $(dtb-y)
|
||||
clean-files := *.dtb *.dtb.S
|
||||
|
|
@ -0,0 +1,133 @@
|
|||
/ {
|
||||
compatible = "qca,ar9132";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "mips,mips24Kc";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
cpuintc: interrupt-controller {
|
||||
compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
|
||||
qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
|
||||
<&ddr_ctrl 0>, <&ddr_ctrl 1>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
interrupt-parent = <&cpuintc>;
|
||||
|
||||
apb {
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
interrupt-parent = <&miscintc>;
|
||||
|
||||
ddr_ctrl: memory-controller@18000000 {
|
||||
compatible = "qca,ar9132-ddr-controller",
|
||||
"qca,ar7240-ddr-controller";
|
||||
reg = <0x18000000 0x100>;
|
||||
|
||||
#qca,ddr-wb-channel-cells = <1>;
|
||||
};
|
||||
|
||||
uart@18020000 {
|
||||
compatible = "ns8250";
|
||||
reg = <0x18020000 0x20>;
|
||||
interrupts = <3>;
|
||||
|
||||
clocks = <&pll 2>;
|
||||
clock-names = "uart";
|
||||
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
no-loopback-test;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio: gpio@18040000 {
|
||||
compatible = "qca,ar9132-gpio",
|
||||
"qca,ar7100-gpio";
|
||||
reg = <0x18040000 0x30>;
|
||||
interrupts = <2>;
|
||||
|
||||
ngpios = <22>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pll: pll-controller@18050000 {
|
||||
compatible = "qca,ar9132-ppl",
|
||||
"qca,ar9130-pll";
|
||||
reg = <0x18050000 0x20>;
|
||||
|
||||
clock-names = "ref";
|
||||
/* The board must provides the ref clock */
|
||||
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "cpu", "ddr", "ahb";
|
||||
};
|
||||
|
||||
wdt@18060008 {
|
||||
compatible = "qca,ar7130-wdt";
|
||||
reg = <0x18060008 0x8>;
|
||||
|
||||
interrupts = <4>;
|
||||
|
||||
clocks = <&pll 2>;
|
||||
clock-names = "wdt";
|
||||
};
|
||||
|
||||
miscintc: interrupt-controller@18060010 {
|
||||
compatible = "qca,ar9132-misc-intc",
|
||||
"qca,ar7100-misc-intc";
|
||||
reg = <0x18060010 0x4>;
|
||||
|
||||
interrupt-parent = <&cpuintc>;
|
||||
interrupts = <6>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
spi@1f000000 {
|
||||
compatible = "qca,ar9132-spi", "qca,ar7100-spi";
|
||||
reg = <0x1f000000 0x10>;
|
||||
|
||||
clocks = <&pll 2>;
|
||||
clock-names = "ahb";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,112 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
#include "ar9132.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "tplink,tl-wr1043nd-v1", "qca,ar9132";
|
||||
model = "TP-Link TL-WR1043ND Version 1";
|
||||
|
||||
alias {
|
||||
serial0 = "/ahb/apb/uart@18020000";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x2000000>;
|
||||
};
|
||||
|
||||
extosc: oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <40000000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
uart@18020000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pll-controller@18050000 {
|
||||
clocks = <&extosc>;
|
||||
};
|
||||
};
|
||||
|
||||
spi@1f000000 {
|
||||
status = "okay";
|
||||
num-cs = <1>;
|
||||
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "s25sl064a";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <25000000>;
|
||||
|
||||
partition@0 {
|
||||
label = "u-boot";
|
||||
reg = <0x000000 0x020000>;
|
||||
};
|
||||
|
||||
partition@1 {
|
||||
label = "firmware";
|
||||
reg = <0x020000 0x7D0000>;
|
||||
};
|
||||
|
||||
partition@2 {
|
||||
label = "art";
|
||||
reg = <0x7F0000 0x010000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys-polled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
poll-interval = <20>;
|
||||
button@0 {
|
||||
label = "reset";
|
||||
linux,code = <KEY_RESTART>;
|
||||
gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
|
||||
debounce-interval = <60>;
|
||||
};
|
||||
|
||||
button@1 {
|
||||
label = "qss";
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
|
||||
debounce-interval = <60>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
led@0 {
|
||||
label = "tp-link:green:usb";
|
||||
gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
led@1 {
|
||||
label = "tp-link:green:system";
|
||||
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
led@2 {
|
||||
label = "tp-link:green:qss";
|
||||
gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led@3 {
|
||||
label = "tp-link:green:wlan";
|
||||
gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -698,7 +698,9 @@ static void octeon_irq_ciu_gpio_ack(struct irq_data *data)
|
|||
|
||||
static void octeon_irq_handle_trigger(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
if (irq_get_trigger_type(irq) & IRQ_TYPE_EDGE_BOTH)
|
||||
struct irq_data *data = irq_desc_get_irq_data(desc);
|
||||
|
||||
if (irqd_get_trigger_type(data) & IRQ_TYPE_EDGE_BOTH)
|
||||
handle_edge_irq(irq, desc);
|
||||
else
|
||||
handle_level_irq(irq, desc);
|
||||
|
|
|
|||
|
|
@ -57,5 +57,4 @@ static int __init cobalt_mtd_init(void)
|
|||
|
||||
return 0;
|
||||
}
|
||||
|
||||
module_init(cobalt_mtd_init);
|
||||
device_initcall(cobalt_mtd_init);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,162 @@
|
|||
CONFIG_MACH_INGENIC=y
|
||||
CONFIG_JZ4780_CI20=y
|
||||
CONFIG_HIGHMEM=y
|
||||
# CONFIG_COMPACTION is not set
|
||||
CONFIG_CMA=y
|
||||
CONFIG_HZ_100=y
|
||||
CONFIG_PREEMPT=y
|
||||
# CONFIG_SECCOMP is not set
|
||||
# CONFIG_LOCALVERSION_AUTO is not set
|
||||
CONFIG_KERNEL_XZ=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_FHANDLE=y
|
||||
CONFIG_NO_HZ_IDLE=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_CGROUPS=y
|
||||
CONFIG_CGROUP_FREEZER=y
|
||||
CONFIG_CGROUP_DEVICE=y
|
||||
CONFIG_CPUSETS=y
|
||||
CONFIG_CGROUP_CPUACCT=y
|
||||
CONFIG_MEMCG=y
|
||||
CONFIG_MEMCG_KMEM=y
|
||||
CONFIG_CGROUP_SCHED=y
|
||||
CONFIG_NAMESPACES=y
|
||||
CONFIG_USER_NS=y
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
CONFIG_SYSCTL_SYSCALL=y
|
||||
CONFIG_KALLSYMS_ALL=y
|
||||
CONFIG_EMBEDDED=y
|
||||
# CONFIG_VM_EVENT_COUNTERS is not set
|
||||
# CONFIG_COMPAT_BRK is not set
|
||||
CONFIG_SLAB=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
# CONFIG_SUSPEND is not set
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
# CONFIG_INET_DIAG is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
# CONFIG_WIRELESS is not set
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
# CONFIG_FW_LOADER is not set
|
||||
# CONFIG_ALLOW_DEV_COREDUMP is not set
|
||||
CONFIG_DMA_CMA=y
|
||||
CONFIG_CMA_SIZE_MBYTES=32
|
||||
CONFIG_NETDEVICES=y
|
||||
# CONFIG_NET_VENDOR_ARC is not set
|
||||
# CONFIG_NET_CADENCE is not set
|
||||
# CONFIG_NET_VENDOR_BROADCOM is not set
|
||||
CONFIG_DM9000=y
|
||||
CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL=y
|
||||
# CONFIG_NET_VENDOR_INTEL is not set
|
||||
# CONFIG_NET_VENDOR_MARVELL is not set
|
||||
# CONFIG_NET_VENDOR_MICREL is not set
|
||||
# CONFIG_NET_VENDOR_NATSEMI is not set
|
||||
# CONFIG_NET_VENDOR_QUALCOMM is not set
|
||||
# CONFIG_NET_VENDOR_ROCKER is not set
|
||||
# CONFIG_NET_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_NET_VENDOR_SEEQ is not set
|
||||
# CONFIG_NET_VENDOR_SMSC is not set
|
||||
# CONFIG_NET_VENDOR_STMICRO is not set
|
||||
# CONFIG_NET_VENDOR_VIA is not set
|
||||
# CONFIG_NET_VENDOR_WIZNET is not set
|
||||
# CONFIG_WLAN is not set
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_SERIO is not set
|
||||
CONFIG_VT_HW_CONSOLE_BINDING=y
|
||||
CONFIG_LEGACY_PTY_COUNT=2
|
||||
# CONFIG_DEVKMEM is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=5
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=5
|
||||
CONFIG_SERIAL_8250_INGENIC=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_JZ4780=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_REGULATOR_DEBUG=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
# CONFIG_VGA_CONSOLE is not set
|
||||
# CONFIG_HID is not set
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
CONFIG_MMC=y
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
CONFIG_MEMORY=y
|
||||
# CONFIG_DNOTIFY is not set
|
||||
CONFIG_PROC_KCORE=y
|
||||
# CONFIG_PROC_PAGE_MONITOR is not set
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_CONFIGFS_FS=y
|
||||
# CONFIG_MISC_FILESYSTEMS is not set
|
||||
# CONFIG_NETWORK_FILESYSTEMS is not set
|
||||
CONFIG_NLS=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_CODEPAGE_737=y
|
||||
CONFIG_NLS_CODEPAGE_775=y
|
||||
CONFIG_NLS_CODEPAGE_850=y
|
||||
CONFIG_NLS_CODEPAGE_852=y
|
||||
CONFIG_NLS_CODEPAGE_855=y
|
||||
CONFIG_NLS_CODEPAGE_857=y
|
||||
CONFIG_NLS_CODEPAGE_860=y
|
||||
CONFIG_NLS_CODEPAGE_861=y
|
||||
CONFIG_NLS_CODEPAGE_862=y
|
||||
CONFIG_NLS_CODEPAGE_863=y
|
||||
CONFIG_NLS_CODEPAGE_864=y
|
||||
CONFIG_NLS_CODEPAGE_865=y
|
||||
CONFIG_NLS_CODEPAGE_866=y
|
||||
CONFIG_NLS_CODEPAGE_869=y
|
||||
CONFIG_NLS_CODEPAGE_936=y
|
||||
CONFIG_NLS_CODEPAGE_950=y
|
||||
CONFIG_NLS_CODEPAGE_932=y
|
||||
CONFIG_NLS_CODEPAGE_949=y
|
||||
CONFIG_NLS_CODEPAGE_874=y
|
||||
CONFIG_NLS_ISO8859_8=y
|
||||
CONFIG_NLS_CODEPAGE_1250=y
|
||||
CONFIG_NLS_CODEPAGE_1251=y
|
||||
CONFIG_NLS_ASCII=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_NLS_ISO8859_2=y
|
||||
CONFIG_NLS_ISO8859_3=y
|
||||
CONFIG_NLS_ISO8859_4=y
|
||||
CONFIG_NLS_ISO8859_5=y
|
||||
CONFIG_NLS_ISO8859_6=y
|
||||
CONFIG_NLS_ISO8859_7=y
|
||||
CONFIG_NLS_ISO8859_9=y
|
||||
CONFIG_NLS_ISO8859_13=y
|
||||
CONFIG_NLS_ISO8859_14=y
|
||||
CONFIG_NLS_ISO8859_15=y
|
||||
CONFIG_NLS_KOI8_R=y
|
||||
CONFIG_NLS_KOI8_U=y
|
||||
CONFIG_NLS_UTF8=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_STRIP_ASM_SYMS=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_LOCKUP_DETECTOR=y
|
||||
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
|
||||
CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
|
||||
CONFIG_PANIC_ON_OOPS=y
|
||||
CONFIG_PANIC_TIMEOUT=10
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
# CONFIG_DEBUG_PREEMPT is not set
|
||||
CONFIG_STACKTRACE=y
|
||||
# CONFIG_FTRACE is not set
|
||||
CONFIG_CMDLINE_BOOL=y
|
||||
CONFIG_CMDLINE="earlycon console=ttyS4,115200 clk_ignore_unused"
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
CONFIG_MACH_LOONGSON=y
|
||||
CONFIG_MACH_LOONGSON64=y
|
||||
CONFIG_64BIT=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
CONFIG_MACH_LOONGSON=y
|
||||
CONFIG_MACH_LOONGSON64=y
|
||||
CONFIG_LEMOTE_MACH2F=y
|
||||
CONFIG_CS5536_MFGPT=y
|
||||
CONFIG_64BIT=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
CONFIG_MACH_LOONGSON=y
|
||||
CONFIG_MACH_LOONGSON64=y
|
||||
CONFIG_SWIOTLB=y
|
||||
CONFIG_LOONGSON_MACH3X=y
|
||||
CONFIG_CPU_LOONGSON3=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
CONFIG_MACH_LOONGSON1=y
|
||||
CONFIG_MACH_LOONGSON32=y
|
||||
CONFIG_PREEMPT=y
|
||||
# CONFIG_SECCOMP is not set
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
|
|
|
|||
|
|
@ -84,15 +84,12 @@ CONFIG_NET_CLS_IND=y
|
|||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_CRYPTOLOOP=m
|
||||
CONFIG_IDE=y
|
||||
# CONFIG_IDE_PROC_FS is not set
|
||||
# CONFIG_IDEPCI_PCIBUS_ORDER is not set
|
||||
CONFIG_BLK_DEV_GENERIC=y
|
||||
CONFIG_BLK_DEV_PIIX=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_CHR_DEV_SG=y
|
||||
# CONFIG_SCSI_LOWLEVEL is not set
|
||||
CONFIG_ATA=y
|
||||
# CONFIG_SATA_PMP is not set
|
||||
CONFIG_ATA_PIIX=y
|
||||
CONFIG_NETDEVICES=y
|
||||
# CONFIG_NET_VENDOR_3COM is not set
|
||||
# CONFIG_NET_VENDOR_ADAPTEC is not set
|
||||
|
|
@ -138,7 +135,6 @@ CONFIG_SERIAL_8250=y
|
|||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_VIDEO_OUTPUT_CONTROL=m
|
||||
CONFIG_FB=y
|
||||
CONFIG_FIRMWARE_EDID=y
|
||||
CONFIG_FB_MATROX=y
|
||||
|
|
@ -152,7 +148,6 @@ CONFIG_NEW_LEDS=y
|
|||
CONFIG_LEDS_CLASS=y
|
||||
CONFIG_LEDS_TRIGGERS=y
|
||||
CONFIG_LEDS_TRIGGER_TIMER=y
|
||||
CONFIG_LEDS_TRIGGER_IDE_DISK=y
|
||||
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
|
||||
CONFIG_LEDS_TRIGGER_BACKLIGHT=y
|
||||
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
|
||||
|
|
@ -160,7 +155,11 @@ CONFIG_RTC_CLASS=y
|
|||
CONFIG_RTC_DRV_CMOS=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
|
||||
CONFIG_EXT3_FS_POSIX_ACL=y
|
||||
CONFIG_EXT3_FS_SECURITY=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_EXT4_FS_POSIX_ACL=y
|
||||
CONFIG_EXT4_FS_SECURITY=y
|
||||
CONFIG_XFS_FS=y
|
||||
CONFIG_XFS_QUOTA=y
|
||||
CONFIG_XFS_POSIX_ACL=y
|
||||
|
|
|
|||
|
|
@ -272,6 +272,7 @@ CONFIG_IIO=y
|
|||
CONFIG_CC10001_ADC=y
|
||||
CONFIG_PWM=y
|
||||
CONFIG_PWM_IMG=y
|
||||
CONFIG_PHY_PISTACHIO_USB=y
|
||||
CONFIG_ANDROID=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_EXT4_FS_POSIX_ACL=y
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
CONFIG_MACH_JZ4740=y
|
||||
CONFIG_MACH_INGENIC=y
|
||||
# CONFIG_COMPACTION is not set
|
||||
# CONFIG_CROSS_MEMORY_ATTACH is not set
|
||||
CONFIG_HZ_100=y
|
||||
|
|
@ -66,6 +66,7 @@ CONFIG_SERIAL_8250_CONSOLE=y
|
|||
# CONFIG_SERIAL_8250_DMA is not set
|
||||
CONFIG_SERIAL_8250_NR_UARTS=2
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
|
||||
CONFIG_SERIAL_8250_INGENIC=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_GPIO=y
|
||||
|
|
|
|||
|
|
@ -211,9 +211,13 @@
|
|||
.endm
|
||||
|
||||
#ifdef TOOLCHAIN_SUPPORTS_MSA
|
||||
/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
|
||||
#undef fp
|
||||
|
||||
.macro _cfcmsa rd, cs
|
||||
.set push
|
||||
.set mips32r2
|
||||
.set fp=64
|
||||
.set msa
|
||||
cfcmsa \rd, $\cs
|
||||
.set pop
|
||||
|
|
@ -222,6 +226,7 @@
|
|||
.macro _ctcmsa cd, rs
|
||||
.set push
|
||||
.set mips32r2
|
||||
.set fp=64
|
||||
.set msa
|
||||
ctcmsa $\cd, \rs
|
||||
.set pop
|
||||
|
|
@ -230,6 +235,7 @@
|
|||
.macro ld_d wd, off, base
|
||||
.set push
|
||||
.set mips32r2
|
||||
.set fp=64
|
||||
.set msa
|
||||
ld.d $w\wd, \off(\base)
|
||||
.set pop
|
||||
|
|
@ -238,6 +244,7 @@
|
|||
.macro st_d wd, off, base
|
||||
.set push
|
||||
.set mips32r2
|
||||
.set fp=64
|
||||
.set msa
|
||||
st.d $w\wd, \off(\base)
|
||||
.set pop
|
||||
|
|
@ -246,6 +253,7 @@
|
|||
.macro copy_u_w ws, n
|
||||
.set push
|
||||
.set mips32r2
|
||||
.set fp=64
|
||||
.set msa
|
||||
copy_u.w $1, $w\ws[\n]
|
||||
.set pop
|
||||
|
|
@ -254,6 +262,7 @@
|
|||
.macro copy_u_d ws, n
|
||||
.set push
|
||||
.set mips64r2
|
||||
.set fp=64
|
||||
.set msa
|
||||
copy_u.d $1, $w\ws[\n]
|
||||
.set pop
|
||||
|
|
@ -262,6 +271,7 @@
|
|||
.macro insert_w wd, n
|
||||
.set push
|
||||
.set mips32r2
|
||||
.set fp=64
|
||||
.set msa
|
||||
insert.w $w\wd[\n], $1
|
||||
.set pop
|
||||
|
|
@ -270,6 +280,7 @@
|
|||
.macro insert_d wd, n
|
||||
.set push
|
||||
.set mips64r2
|
||||
.set fp=64
|
||||
.set msa
|
||||
insert.d $w\wd[\n], $1
|
||||
.set pop
|
||||
|
|
|
|||
|
|
@ -469,7 +469,7 @@ static inline int test_and_change_bit(unsigned long nr,
|
|||
*/
|
||||
static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long *addr)
|
||||
{
|
||||
smp_mb();
|
||||
smp_mb__before_llsc();
|
||||
__clear_bit(nr, addr);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,7 @@
|
|||
#ifndef __ASM_BMIPS_SPACES_H
|
||||
#define __ASM_BMIPS_SPACES_H
|
||||
|
||||
/* Avoid collisions with system base register (SBR) region on BMIPS3300 */
|
||||
#define FIXADDR_TOP ((unsigned long)(long)(int)0xff000000)
|
||||
|
||||
#endif /* __ASM_BMIPS_SPACES_H */
|
||||
|
|
@ -108,6 +108,9 @@
|
|||
#ifndef cpu_has_llsc
|
||||
#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
|
||||
#endif
|
||||
#ifndef cpu_has_bp_ghist
|
||||
#define cpu_has_bp_ghist (cpu_data[0].options & MIPS_CPU_BP_GHIST)
|
||||
#endif
|
||||
#ifndef kernel_uses_llsc
|
||||
#define kernel_uses_llsc cpu_has_llsc
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -32,12 +32,12 @@ static inline int __pure __get_cpu_type(const int cpu_type)
|
|||
case CPU_4KC:
|
||||
case CPU_ALCHEMY:
|
||||
case CPU_PR4450:
|
||||
case CPU_JZRISC:
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SYS_HAS_CPU_MIPS32_R1) || \
|
||||
defined(CONFIG_SYS_HAS_CPU_MIPS32_R2)
|
||||
case CPU_4KEC:
|
||||
case CPU_JZRISC:
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R2
|
||||
|
|
|
|||
|
|
@ -42,7 +42,9 @@
|
|||
#define PRID_COMP_LEXRA 0x0b0000
|
||||
#define PRID_COMP_NETLOGIC 0x0c0000
|
||||
#define PRID_COMP_CAVIUM 0x0d0000
|
||||
#define PRID_COMP_INGENIC 0xd00000
|
||||
#define PRID_COMP_INGENIC_D0 0xd00000 /* JZ4740, JZ4750 */
|
||||
#define PRID_COMP_INGENIC_D1 0xd10000 /* JZ4770, JZ4775 */
|
||||
#define PRID_COMP_INGENIC_E1 0xe10000 /* JZ4780 */
|
||||
|
||||
/*
|
||||
* Assigned Processor ID (implementation) values for bits 15:8 of the PRId
|
||||
|
|
@ -168,7 +170,7 @@
|
|||
#define PRID_IMP_CAVIUM_CN70XX 0x9600
|
||||
|
||||
/*
|
||||
* These are the PRID's for when 23:16 == PRID_COMP_INGENIC
|
||||
* These are the PRID's for when 23:16 == PRID_COMP_INGENIC_*
|
||||
*/
|
||||
|
||||
#define PRID_IMP_JZRISC 0x0200
|
||||
|
|
@ -379,6 +381,7 @@ enum cpu_type_enum {
|
|||
#define MIPS_CPU_RW_LLB 0x1000000000ull /* LLADDR/LLB writes are allowed */
|
||||
#define MIPS_CPU_XPA 0x2000000000ull /* CPU supports Extended Physical Addressing */
|
||||
#define MIPS_CPU_CDMM 0x4000000000ull /* CPU has Common Device Memory Map */
|
||||
#define MIPS_CPU_BP_GHIST 0x8000000000ull /* R12K+ Branch Prediction Global History */
|
||||
|
||||
/*
|
||||
* CPU ASE encodings
|
||||
|
|
|
|||
|
|
@ -31,9 +31,15 @@
|
|||
#define __mtc0_tlbw_hazard \
|
||||
___ehb
|
||||
|
||||
#define __mtc0_tlbr_hazard \
|
||||
___ehb
|
||||
|
||||
#define __tlbw_use_hazard \
|
||||
___ehb
|
||||
|
||||
#define __tlb_read_hazard \
|
||||
___ehb
|
||||
|
||||
#define __tlb_probe_hazard \
|
||||
___ehb
|
||||
|
||||
|
|
@ -80,12 +86,23 @@ do { \
|
|||
___ssnop; \
|
||||
___ehb
|
||||
|
||||
#define __mtc0_tlbr_hazard \
|
||||
___ssnop; \
|
||||
___ssnop; \
|
||||
___ehb
|
||||
|
||||
#define __tlbw_use_hazard \
|
||||
___ssnop; \
|
||||
___ssnop; \
|
||||
___ssnop; \
|
||||
___ehb
|
||||
|
||||
#define __tlb_read_hazard \
|
||||
___ssnop; \
|
||||
___ssnop; \
|
||||
___ssnop; \
|
||||
___ehb
|
||||
|
||||
#define __tlb_probe_hazard \
|
||||
___ssnop; \
|
||||
___ssnop; \
|
||||
|
|
@ -147,8 +164,12 @@ do { \
|
|||
|
||||
#define __mtc0_tlbw_hazard
|
||||
|
||||
#define __mtc0_tlbr_hazard
|
||||
|
||||
#define __tlbw_use_hazard
|
||||
|
||||
#define __tlb_read_hazard
|
||||
|
||||
#define __tlb_probe_hazard
|
||||
|
||||
#define __irq_enable_hazard
|
||||
|
|
@ -166,8 +187,12 @@ do { \
|
|||
*/
|
||||
#define __mtc0_tlbw_hazard
|
||||
|
||||
#define __mtc0_tlbr_hazard
|
||||
|
||||
#define __tlbw_use_hazard
|
||||
|
||||
#define __tlb_read_hazard
|
||||
|
||||
#define __tlb_probe_hazard
|
||||
|
||||
#define __irq_enable_hazard
|
||||
|
|
@ -196,11 +221,20 @@ do { \
|
|||
nop; \
|
||||
nop
|
||||
|
||||
#define __mtc0_tlbr_hazard \
|
||||
nop; \
|
||||
nop
|
||||
|
||||
#define __tlbw_use_hazard \
|
||||
nop; \
|
||||
nop; \
|
||||
nop
|
||||
|
||||
#define __tlb_read_hazard \
|
||||
nop; \
|
||||
nop; \
|
||||
nop
|
||||
|
||||
#define __tlb_probe_hazard \
|
||||
nop; \
|
||||
nop; \
|
||||
|
|
@ -267,7 +301,9 @@ do { \
|
|||
#define _ssnop ___ssnop
|
||||
#define _ehb ___ehb
|
||||
#define mtc0_tlbw_hazard __mtc0_tlbw_hazard
|
||||
#define mtc0_tlbr_hazard __mtc0_tlbr_hazard
|
||||
#define tlbw_use_hazard __tlbw_use_hazard
|
||||
#define tlb_read_hazard __tlb_read_hazard
|
||||
#define tlb_probe_hazard __tlb_probe_hazard
|
||||
#define irq_enable_hazard __irq_enable_hazard
|
||||
#define irq_disable_hazard __irq_disable_hazard
|
||||
|
|
@ -300,6 +336,14 @@ do { \
|
|||
} while (0)
|
||||
|
||||
|
||||
#define mtc0_tlbr_hazard() \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
__stringify(__mtc0_tlbr_hazard) \
|
||||
); \
|
||||
} while (0)
|
||||
|
||||
|
||||
#define tlbw_use_hazard() \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
|
|
@ -308,6 +352,14 @@ do { \
|
|||
} while (0)
|
||||
|
||||
|
||||
#define tlb_read_hazard() \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
__stringify(__tlb_read_hazard) \
|
||||
); \
|
||||
} while (0)
|
||||
|
||||
|
||||
#define tlb_probe_hazard() \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
|
|
|
|||
|
|
@ -41,6 +41,7 @@ extern int i8259A_irq_pending(unsigned int irq);
|
|||
extern void make_8259A_irq(unsigned int irq);
|
||||
|
||||
extern void init_i8259_irqs(void);
|
||||
extern int i8259_of_init(struct device_node *node, struct device_node *parent);
|
||||
|
||||
/*
|
||||
* Do the traditional i8259 interrupt polling thing. This is for the few
|
||||
|
|
|
|||
|
|
@ -60,7 +60,7 @@ static inline void arch_local_irq_restore(unsigned long flags)
|
|||
" .set push \n"
|
||||
" .set noreorder \n"
|
||||
" .set noat \n"
|
||||
#if defined(CONFIG_IRQ_CPU)
|
||||
#if defined(CONFIG_IRQ_MIPS_CPU)
|
||||
/*
|
||||
* Slow, but doesn't suffer from a relatively unlikely race
|
||||
* condition we're having since days 1.
|
||||
|
|
@ -90,7 +90,7 @@ static inline void __arch_local_irq_restore(unsigned long flags)
|
|||
" .set push \n"
|
||||
" .set noreorder \n"
|
||||
" .set noat \n"
|
||||
#if defined(CONFIG_IRQ_CPU)
|
||||
#if defined(CONFIG_IRQ_MIPS_CPU)
|
||||
/*
|
||||
* Slow, but doesn't suffer from a relatively unlikely race
|
||||
* condition we're having since days 1.
|
||||
|
|
|
|||
|
|
@ -33,7 +33,6 @@
|
|||
#define CACHE_FLUSH_IS_SAFE 0
|
||||
|
||||
extern void arch_kgdb_breakpoint(void);
|
||||
extern int kgdb_early_setup;
|
||||
extern void *saved_vectors[32];
|
||||
extern void handle_exception(struct pt_regs *regs);
|
||||
extern void breakinst(void);
|
||||
|
|
|
|||
|
|
@ -157,8 +157,8 @@
|
|||
#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10
|
||||
#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14
|
||||
|
||||
#define AR71XX_PLL_DIV_SHIFT 3
|
||||
#define AR71XX_PLL_DIV_MASK 0x1f
|
||||
#define AR71XX_PLL_FB_SHIFT 3
|
||||
#define AR71XX_PLL_FB_MASK 0x1f
|
||||
#define AR71XX_CPU_DIV_SHIFT 16
|
||||
#define AR71XX_CPU_DIV_MASK 0x3
|
||||
#define AR71XX_DDR_DIV_SHIFT 18
|
||||
|
|
@ -169,8 +169,8 @@
|
|||
#define AR724X_PLL_REG_CPU_CONFIG 0x00
|
||||
#define AR724X_PLL_REG_PCIE_CONFIG 0x18
|
||||
|
||||
#define AR724X_PLL_DIV_SHIFT 0
|
||||
#define AR724X_PLL_DIV_MASK 0x3ff
|
||||
#define AR724X_PLL_FB_SHIFT 0
|
||||
#define AR724X_PLL_FB_MASK 0x3ff
|
||||
#define AR724X_PLL_REF_DIV_SHIFT 10
|
||||
#define AR724X_PLL_REF_DIV_MASK 0xf
|
||||
#define AR724X_AHB_DIV_SHIFT 19
|
||||
|
|
@ -183,8 +183,8 @@
|
|||
#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
|
||||
#define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18
|
||||
|
||||
#define AR913X_PLL_DIV_SHIFT 0
|
||||
#define AR913X_PLL_DIV_MASK 0x3ff
|
||||
#define AR913X_PLL_FB_SHIFT 0
|
||||
#define AR913X_PLL_FB_MASK 0x3ff
|
||||
#define AR913X_DDR_DIV_SHIFT 22
|
||||
#define AR913X_DDR_DIV_MASK 0x3
|
||||
#define AR913X_AHB_DIV_SHIFT 19
|
||||
|
|
|
|||
|
|
@ -115,7 +115,8 @@ static inline int soc_is_qca955x(void)
|
|||
return soc_is_qca9556() || soc_is_qca9558();
|
||||
}
|
||||
|
||||
extern void __iomem *ath79_ddr_base;
|
||||
void ath79_ddr_set_pci_windows(void);
|
||||
|
||||
extern void __iomem *ath79_pll_base;
|
||||
extern void __iomem *ath79_reset_base;
|
||||
|
||||
|
|
|
|||
|
|
@ -52,10 +52,6 @@ void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix,
|
|||
void bcm47xx_fill_ssb_boardinfo(struct ssb_boardinfo *boardinfo,
|
||||
const char *prefix);
|
||||
#endif
|
||||
#ifdef CONFIG_BCM47XX_BCMA
|
||||
void bcm47xx_fill_bcma_boardinfo(struct bcma_boardinfo *boardinfo,
|
||||
const char *prefix);
|
||||
#endif
|
||||
|
||||
void bcm47xx_set_system_type(u16 chip_id);
|
||||
|
||||
|
|
|
|||
|
|
@ -80,6 +80,8 @@ enum bcm47xx_board {
|
|||
BCM47XX_BOARD_LINKSYS_WRT610NV2,
|
||||
BCM47XX_BOARD_LINKSYS_WRTSL54GS,
|
||||
|
||||
BCM47XX_BOARD_LUXUL_XWR_1750_V1,
|
||||
|
||||
BCM47XX_BOARD_MICROSOFT_MN700,
|
||||
|
||||
BCM47XX_BOARD_MOTOROLA_WE800G,
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
#ifndef _ASM_BCM63XX_SPACES_H
|
||||
#define _ASM_BCM63XX_SPACES_H
|
||||
|
||||
#define FIXADDR_TOP ((unsigned long)(long)(int)0xff000000)
|
||||
#include <asm/bmips-spaces.h>
|
||||
|
||||
#include <asm/mach-generic/spaces.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
#define _ASM_BMIPS_SPACES_H
|
||||
|
||||
/* Avoid collisions with system base register (SBR) region on BMIPS3300 */
|
||||
#define FIXADDR_TOP ((unsigned long)(long)(int)0xff000000)
|
||||
#include <asm/bmips-spaces.h>
|
||||
|
||||
#include <asm/mach-generic/spaces.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -14,6 +14,13 @@
|
|||
|
||||
/* Generic ones first. */
|
||||
#define cpu_has_tlb 1
|
||||
#define cpu_has_tlbinv 0
|
||||
#define cpu_has_segments 0
|
||||
#define cpu_has_eva 0
|
||||
#define cpu_has_htw 0
|
||||
#define cpu_has_rixiex 0
|
||||
#define cpu_has_maar 0
|
||||
#define cpu_has_rw_llb 0
|
||||
#define cpu_has_tx39_cache 0
|
||||
#define cpu_has_divec 0
|
||||
#define cpu_has_prefetch 0
|
||||
|
|
@ -24,6 +31,7 @@
|
|||
#define cpu_has_mips3d 0
|
||||
#define cpu_has_smartmips 0
|
||||
#define cpu_has_rixi 0
|
||||
#define cpu_has_xpa 0
|
||||
#define cpu_has_vtag_icache 0
|
||||
#define cpu_has_ic_fills_f_dc 0
|
||||
#define cpu_has_pindexed_dcache 0
|
||||
|
|
@ -36,11 +44,18 @@
|
|||
#define cpu_has_mips64r1 0
|
||||
#define cpu_has_mips64r2 0
|
||||
#define cpu_has_dsp 0
|
||||
#define cpu_has_dsp2 0
|
||||
#define cpu_has_mipsmt 0
|
||||
#define cpu_has_userlocal 0
|
||||
#define cpu_hwrena_impl_bits 0
|
||||
#define cpu_has_perf_cntr_intr_bit 0
|
||||
#define cpu_has_vz 0
|
||||
#define cpu_has_fre 0
|
||||
#define cpu_has_cdmm 0
|
||||
|
||||
/* R3k-specific ones. */
|
||||
#ifdef CONFIG_CPU_R3000
|
||||
#define cpu_has_3kex 1
|
||||
#define cpu_has_4kex 0
|
||||
#define cpu_has_3k_cache 1
|
||||
#define cpu_has_4k_cache 0
|
||||
|
|
@ -63,6 +78,7 @@
|
|||
|
||||
/* R4k-specific ones. */
|
||||
#ifdef CONFIG_CPU_R4X00
|
||||
#define cpu_has_3kex 0
|
||||
#define cpu_has_4kex 1
|
||||
#define cpu_has_3k_cache 0
|
||||
#define cpu_has_4k_cache 1
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@
|
|||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IRQ_CPU
|
||||
#ifdef CONFIG_IRQ_MIPS_CPU
|
||||
|
||||
#ifndef MIPS_CPU_IRQ_BASE
|
||||
#ifdef CONFIG_I8259
|
||||
|
|
@ -34,7 +34,7 @@
|
|||
#endif
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_IRQ_CPU */
|
||||
#endif /* CONFIG_IRQ_MIPS_CPU */
|
||||
|
||||
#ifdef CONFIG_MIPS_GIC
|
||||
#ifndef MIPS_GIC_IRQ_BASE
|
||||
|
|
|
|||
|
|
@ -94,7 +94,11 @@
|
|||
#endif
|
||||
|
||||
#ifndef FIXADDR_TOP
|
||||
#ifdef CONFIG_KVM_GUEST
|
||||
#define FIXADDR_TOP ((unsigned long)(long)(int)0x7ffe0000)
|
||||
#else
|
||||
#define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_MACH_GENERIC_SPACES_H */
|
||||
|
|
|
|||
|
|
@ -11,47 +11,69 @@
|
|||
#include <asm/cpu.h>
|
||||
|
||||
/*
|
||||
* IP27 only comes with R10000 family processors all using the same config
|
||||
* IP27 only comes with R1x000 family processors, all using the same config
|
||||
*/
|
||||
#define cpu_has_watch 1
|
||||
#define cpu_has_mips16 0
|
||||
#define cpu_has_divec 0
|
||||
#define cpu_has_vce 0
|
||||
#define cpu_has_cache_cdex_p 0
|
||||
#define cpu_has_cache_cdex_s 0
|
||||
#define cpu_has_prefetch 1
|
||||
#define cpu_has_mcheck 0
|
||||
#define cpu_has_ejtag 0
|
||||
#define cpu_has_tlb 1
|
||||
#define cpu_has_tlbinv 0
|
||||
#define cpu_has_segments 0
|
||||
#define cpu_has_eva 0
|
||||
#define cpu_has_htw 0
|
||||
#define cpu_has_rixiex 0
|
||||
#define cpu_has_maar 0
|
||||
#define cpu_has_rw_llb 0
|
||||
#define cpu_has_3kex 0
|
||||
#define cpu_has_4kex 1
|
||||
#define cpu_has_3k_cache 0
|
||||
#define cpu_has_4k_cache 1
|
||||
#define cpu_has_6k_cache 0
|
||||
#define cpu_has_8k_cache 0
|
||||
#define cpu_has_tx39_cache 0
|
||||
#define cpu_has_fpu 1
|
||||
#define cpu_has_nofpuex 0
|
||||
#define cpu_has_32fpr 1
|
||||
#define cpu_has_counter 1
|
||||
#define cpu_has_watch 1
|
||||
#define cpu_has_64bits 1
|
||||
#define cpu_has_divec 0
|
||||
#define cpu_has_vce 0
|
||||
#define cpu_has_cache_cdex_p 0
|
||||
#define cpu_has_cache_cdex_s 0
|
||||
#define cpu_has_prefetch 1
|
||||
#define cpu_has_mcheck 0
|
||||
#define cpu_has_ejtag 0
|
||||
#define cpu_has_llsc 1
|
||||
#define cpu_has_mips16 0
|
||||
#define cpu_has_mdmx 0
|
||||
#define cpu_has_mips3d 0
|
||||
#define cpu_has_smartmips 0
|
||||
#define cpu_has_rixi 0
|
||||
#define cpu_has_xpa 0
|
||||
#define cpu_has_vtag_icache 0
|
||||
#define cpu_has_dc_aliases 0
|
||||
#define cpu_has_ic_fills_f_dc 0
|
||||
|
||||
#define cpu_has_llsc 1
|
||||
#define cpu_has_vtag_icache 0
|
||||
#define cpu_has_dc_aliases 0
|
||||
#define cpu_has_ic_fills_f_dc 0
|
||||
#define cpu_has_dsp 0
|
||||
#define cpu_has_dsp2 0
|
||||
#define cpu_icache_snoops_remote_store 1
|
||||
#define cpu_has_mipsmt 0
|
||||
#define cpu_has_userlocal 0
|
||||
|
||||
#define cpu_has_nofpuex 0
|
||||
#define cpu_has_64bits 1
|
||||
|
||||
#define cpu_has_4kex 1
|
||||
#define cpu_has_3k_cache 0
|
||||
#define cpu_has_6k_cache 0
|
||||
#define cpu_has_4k_cache 1
|
||||
#define cpu_has_8k_cache 0
|
||||
#define cpu_has_tx39_cache 0
|
||||
#define cpu_has_mips32r1 0
|
||||
#define cpu_has_mips32r2 0
|
||||
#define cpu_has_mips64r1 0
|
||||
#define cpu_has_mips64r2 0
|
||||
#define cpu_has_mips32r6 0
|
||||
#define cpu_has_mips64r6 0
|
||||
|
||||
#define cpu_has_dsp 0
|
||||
#define cpu_has_dsp2 0
|
||||
#define cpu_has_mipsmt 0
|
||||
#define cpu_has_userlocal 0
|
||||
#define cpu_has_inclusive_pcaches 1
|
||||
#define cpu_hwrena_impl_bits 0
|
||||
#define cpu_has_perf_cntr_intr_bit 0
|
||||
#define cpu_has_vz 0
|
||||
#define cpu_has_fre 0
|
||||
#define cpu_has_cdmm 0
|
||||
|
||||
#define cpu_dcache_line_size() 32
|
||||
#define cpu_icache_line_size() 64
|
||||
#define cpu_scache_line_size() 128
|
||||
|
||||
#define cpu_has_mips32r1 0
|
||||
#define cpu_has_mips32r2 0
|
||||
#define cpu_has_mips64r1 0
|
||||
#define cpu_has_mips64r2 0
|
||||
#define cpu_dcache_line_size() 32
|
||||
#define cpu_icache_line_size() 64
|
||||
#define cpu_scache_line_size() 128
|
||||
|
||||
#endif /* __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H */
|
||||
|
|
|
|||
|
|
@ -22,6 +22,9 @@ enum jz4740_wait_mode {
|
|||
|
||||
void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode);
|
||||
|
||||
void jz4740_clock_suspend(void);
|
||||
void jz4740_clock_resume(void);
|
||||
|
||||
void jz4740_clock_udc_enable_auto_suspend(void);
|
||||
void jz4740_clock_udc_disable_auto_suspend(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -12,8 +12,6 @@
|
|||
#define cpu_has_3k_cache 0
|
||||
#define cpu_has_4k_cache 1
|
||||
#define cpu_has_tx39_cache 0
|
||||
#define cpu_has_fpu 0
|
||||
#define cpu_has_32fpr 0
|
||||
#define cpu_has_counter 0
|
||||
#define cpu_has_watch 1
|
||||
#define cpu_has_divec 1
|
||||
|
|
@ -34,7 +32,6 @@
|
|||
#define cpu_has_ic_fills_f_dc 0
|
||||
#define cpu_has_pindexed_dcache 0
|
||||
#define cpu_has_mips32r1 1
|
||||
#define cpu_has_mips32r2 0
|
||||
#define cpu_has_mips64r1 0
|
||||
#define cpu_has_mips64r2 0
|
||||
#define cpu_has_dsp 0
|
||||
|
|
|
|||
|
|
@ -19,6 +19,12 @@
|
|||
#define MIPS_CPU_IRQ_BASE 0
|
||||
#define JZ4740_IRQ_BASE 8
|
||||
|
||||
#ifdef CONFIG_MACH_JZ4740
|
||||
# define NR_INTC_IRQS 32
|
||||
#else
|
||||
# define NR_INTC_IRQS 64
|
||||
#endif
|
||||
|
||||
/* 1st-level interrupts */
|
||||
#define JZ4740_IRQ(x) (JZ4740_IRQ_BASE + (x))
|
||||
#define JZ4740_IRQ_I2C JZ4740_IRQ(1)
|
||||
|
|
@ -44,13 +50,15 @@
|
|||
#define JZ4740_IRQ_IPU JZ4740_IRQ(29)
|
||||
#define JZ4740_IRQ_LCD JZ4740_IRQ(30)
|
||||
|
||||
#define JZ4780_IRQ_TCU2 JZ4740_IRQ(25)
|
||||
|
||||
/* 2nd-level interrupts */
|
||||
#define JZ4740_IRQ_DMA(x) (JZ4740_IRQ(32) + (x))
|
||||
#define JZ4740_IRQ_DMA(x) (JZ4740_IRQ(NR_INTC_IRQS) + (x))
|
||||
|
||||
#define JZ4740_IRQ_INTC_GPIO(x) (JZ4740_IRQ_GPIO0 - (x))
|
||||
#define JZ4740_IRQ_GPIO(x) (JZ4740_IRQ(48) + (x))
|
||||
#define JZ4740_IRQ_GPIO(x) (JZ4740_IRQ(NR_INTC_IRQS + 16) + (x))
|
||||
|
||||
#define JZ4740_IRQ_ADC_BASE JZ4740_IRQ(176)
|
||||
#define JZ4740_IRQ_ADC_BASE JZ4740_IRQ(NR_INTC_IRQS + 144)
|
||||
|
||||
#define NR_IRQS (JZ4740_IRQ_ADC_BASE + 6)
|
||||
|
||||
|
|
|
|||
|
|
@ -35,6 +35,4 @@ extern struct platform_device jz4740_wdt_device;
|
|||
extern struct platform_device jz4740_pwm_device;
|
||||
extern struct platform_device jz4740_dma_device;
|
||||
|
||||
void jz4740_serial_device_register(void);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,7 +0,0 @@
|
|||
#ifndef __ASM_MACH_LOONGSON_WORKAROUNDS_H_
|
||||
#define __ASM_MACH_LOONGSON_WORKAROUNDS_H_
|
||||
|
||||
#define WORKAROUND_CPUFREQ 0x00000001
|
||||
#define WORKAROUND_CPUHOTPLUG 0x00000002
|
||||
|
||||
#endif
|
||||
|
|
@ -10,8 +10,8 @@
|
|||
*/
|
||||
|
||||
|
||||
#ifndef __ASM_MACH_LOONGSON1_CPUFREQ_H
|
||||
#define __ASM_MACH_LOONGSON1_CPUFREQ_H
|
||||
#ifndef __ASM_MACH_LOONGSON32_CPUFREQ_H
|
||||
#define __ASM_MACH_LOONGSON32_CPUFREQ_H
|
||||
|
||||
struct plat_ls1x_cpufreq {
|
||||
const char *clk_name; /* CPU clk */
|
||||
|
|
@ -20,4 +20,4 @@ struct plat_ls1x_cpufreq {
|
|||
unsigned int min_freq; /* in kHz */
|
||||
};
|
||||
|
||||
#endif /* __ASM_MACH_LOONGSON1_CPUFREQ_H */
|
||||
#endif /* __ASM_MACH_LOONGSON32_CPUFREQ_H */
|
||||
|
|
@ -10,8 +10,8 @@
|
|||
*/
|
||||
|
||||
|
||||
#ifndef __ASM_MACH_LOONGSON1_IRQ_H
|
||||
#define __ASM_MACH_LOONGSON1_IRQ_H
|
||||
#ifndef __ASM_MACH_LOONGSON32_IRQ_H
|
||||
#define __ASM_MACH_LOONGSON32_IRQ_H
|
||||
|
||||
/*
|
||||
* CPU core Interrupt Numbers
|
||||
|
|
@ -70,4 +70,4 @@
|
|||
|
||||
#define NR_IRQS (MIPS_CPU_IRQS + LS1X_IRQS)
|
||||
|
||||
#endif /* __ASM_MACH_LOONGSON1_IRQ_H */
|
||||
#endif /* __ASM_MACH_LOONGSON32_IRQ_H */
|
||||
|
|
@ -10,8 +10,8 @@
|
|||
*/
|
||||
|
||||
|
||||
#ifndef __ASM_MACH_LOONGSON1_LOONGSON1_H
|
||||
#define __ASM_MACH_LOONGSON1_LOONGSON1_H
|
||||
#ifndef __ASM_MACH_LOONGSON32_LOONGSON1_H
|
||||
#define __ASM_MACH_LOONGSON32_LOONGSON1_H
|
||||
|
||||
#define DEFAULT_MEMSIZE 256 /* If no memsize provided */
|
||||
|
||||
|
|
@ -47,4 +47,4 @@
|
|||
#include <regs-pwm.h>
|
||||
#include <regs-wdt.h>
|
||||
|
||||
#endif /* __ASM_MACH_LOONGSON1_LOONGSON1_H */
|
||||
#endif /* __ASM_MACH_LOONGSON32_LOONGSON1_H */
|
||||
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