powerpc/perf: Update cpu_hw_event to use `struct` for storing MMCR registers
core-book3s currently uses array to store the MMCR registers as part of per-cpu `cpu_hw_events`. This patch does a clean up to use `struct` to store mmcr regs instead of array. This will make code easier to read and reduces chance of any subtle bug that may come in the future, say when new registers are added. Patch updates all relevant code that was using MMCR array ( cpuhw->mmcr[x]) to use newly introduced `struct`. This includes the PMU driver code for supported platforms (power5 to power9) and ISA macros for counter support functions. Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/1594996707-3727-2-git-send-email-atrajeev@linux.vnet.ibm.com
This commit is contained in:
Athira Rajeev
Michael Ellerman
Родитель
3c9450c053
Коммит
78d76819e6
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@ -17,6 +17,12 @@
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struct perf_event;
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struct mmcr_regs {
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unsigned long mmcr0;
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unsigned long mmcr1;
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unsigned long mmcr2;
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unsigned long mmcra;
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};
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/*
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* This struct provides the constants and functions needed to
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* describe the PMU on a particular POWER-family CPU.
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@ -28,7 +34,7 @@ struct power_pmu {
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unsigned long add_fields;
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unsigned long test_adder;
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int (*compute_mmcr)(u64 events[], int n_ev,
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unsigned int hwc[], unsigned long mmcr[],
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unsigned int hwc[], struct mmcr_regs *mmcr,
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struct perf_event *pevents[]);
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int (*get_constraint)(u64 event_id, unsigned long *mskp,
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unsigned long *valp);
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@ -41,7 +47,7 @@ struct power_pmu {
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unsigned long group_constraint_val;
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u64 (*bhrb_filter_map)(u64 branch_sample_type);
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void (*config_bhrb)(u64 pmu_bhrb_filter);
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void (*disable_pmc)(unsigned int pmc, unsigned long mmcr[]);
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void (*disable_pmc)(unsigned int pmc, struct mmcr_regs *mmcr);
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int (*limited_pmc_event)(u64 event_id);
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u32 flags;
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const struct attribute_group **attr_groups;
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@ -37,12 +37,7 @@ struct cpu_hw_events {
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struct perf_event *event[MAX_HWEVENTS];
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u64 events[MAX_HWEVENTS];
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unsigned int flags[MAX_HWEVENTS];
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/*
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* The order of the MMCR array is:
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* - 64-bit, MMCR0, MMCR1, MMCRA, MMCR2
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* - 32-bit, MMCR0, MMCR1, MMCR2
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*/
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unsigned long mmcr[4];
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struct mmcr_regs mmcr;
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struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS];
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u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS];
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u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
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@ -121,7 +116,7 @@ static void ebb_event_add(struct perf_event *event) { }
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static void ebb_switch_out(unsigned long mmcr0) { }
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static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw)
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{
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return cpuhw->mmcr[0];
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return cpuhw->mmcr.mmcr0;
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}
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static inline void power_pmu_bhrb_enable(struct perf_event *event) {}
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@ -590,7 +585,7 @@ static void ebb_switch_out(unsigned long mmcr0)
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static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw)
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{
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unsigned long mmcr0 = cpuhw->mmcr[0];
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unsigned long mmcr0 = cpuhw->mmcr.mmcr0;
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if (!ebb)
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goto out;
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@ -624,7 +619,7 @@ static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw)
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* unfreeze counters, it should not set exclude_xxx in its events and
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* instead manage the MMCR2 entirely by itself.
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*/
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mtspr(SPRN_MMCR2, cpuhw->mmcr[3] | current->thread.mmcr2);
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mtspr(SPRN_MMCR2, cpuhw->mmcr.mmcr2 | current->thread.mmcr2);
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out:
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return mmcr0;
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}
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@ -1232,9 +1227,9 @@ static void power_pmu_disable(struct pmu *pmu)
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/*
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* Disable instruction sampling if it was enabled
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*/
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if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
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if (cpuhw->mmcr.mmcra & MMCRA_SAMPLE_ENABLE) {
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mtspr(SPRN_MMCRA,
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cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
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cpuhw->mmcr.mmcra & ~MMCRA_SAMPLE_ENABLE);
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mb();
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isync();
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}
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@ -1308,18 +1303,18 @@ static void power_pmu_enable(struct pmu *pmu)
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* (possibly updated for removal of events).
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*/
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if (!cpuhw->n_added) {
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mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
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mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
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mtspr(SPRN_MMCRA, cpuhw->mmcr.mmcra & ~MMCRA_SAMPLE_ENABLE);
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mtspr(SPRN_MMCR1, cpuhw->mmcr.mmcr1);
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goto out_enable;
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}
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/*
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* Clear all MMCR settings and recompute them for the new set of events.
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*/
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memset(cpuhw->mmcr, 0, sizeof(cpuhw->mmcr));
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memset(&cpuhw->mmcr, 0, sizeof(cpuhw->mmcr));
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if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index,
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cpuhw->mmcr, cpuhw->event)) {
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&cpuhw->mmcr, cpuhw->event)) {
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/* shouldn't ever get here */
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printk(KERN_ERR "oops compute_mmcr failed\n");
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goto out;
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@ -1333,11 +1328,11 @@ static void power_pmu_enable(struct pmu *pmu)
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*/
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event = cpuhw->event[0];
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if (event->attr.exclude_user)
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cpuhw->mmcr[0] |= MMCR0_FCP;
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cpuhw->mmcr.mmcr0 |= MMCR0_FCP;
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if (event->attr.exclude_kernel)
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cpuhw->mmcr[0] |= freeze_events_kernel;
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cpuhw->mmcr.mmcr0 |= freeze_events_kernel;
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if (event->attr.exclude_hv)
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cpuhw->mmcr[0] |= MMCR0_FCHV;
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cpuhw->mmcr.mmcr0 |= MMCR0_FCHV;
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}
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/*
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@ -1346,12 +1341,12 @@ static void power_pmu_enable(struct pmu *pmu)
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* Then unfreeze the events.
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*/
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ppc_set_pmu_inuse(1);
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mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
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mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
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mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE))
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mtspr(SPRN_MMCRA, cpuhw->mmcr.mmcra & ~MMCRA_SAMPLE_ENABLE);
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mtspr(SPRN_MMCR1, cpuhw->mmcr.mmcr1);
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mtspr(SPRN_MMCR0, (cpuhw->mmcr.mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE))
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| MMCR0_FC);
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if (ppmu->flags & PPMU_ARCH_207S)
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mtspr(SPRN_MMCR2, cpuhw->mmcr[3]);
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mtspr(SPRN_MMCR2, cpuhw->mmcr.mmcr2);
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/*
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* Read off any pre-existing events that need to move
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@ -1402,7 +1397,7 @@ static void power_pmu_enable(struct pmu *pmu)
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perf_event_update_userpage(event);
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}
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cpuhw->n_limited = n_lim;
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cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE;
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cpuhw->mmcr.mmcr0 |= MMCR0_PMXE | MMCR0_FCECE;
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out_enable:
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pmao_restore_workaround(ebb);
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@ -1418,9 +1413,9 @@ static void power_pmu_enable(struct pmu *pmu)
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/*
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* Enable instruction sampling if necessary
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*/
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if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
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if (cpuhw->mmcr.mmcra & MMCRA_SAMPLE_ENABLE) {
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mb();
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mtspr(SPRN_MMCRA, cpuhw->mmcr[2]);
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mtspr(SPRN_MMCRA, cpuhw->mmcr.mmcra);
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}
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out:
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@ -1550,7 +1545,7 @@ static void power_pmu_del(struct perf_event *event, int ef_flags)
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cpuhw->flags[i-1] = cpuhw->flags[i];
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}
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--cpuhw->n_events;
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ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr);
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ppmu->disable_pmc(event->hw.idx - 1, &cpuhw->mmcr);
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if (event->hw.idx) {
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write_pmc(event->hw.idx, 0);
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event->hw.idx = 0;
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@ -1571,7 +1566,7 @@ static void power_pmu_del(struct perf_event *event, int ef_flags)
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}
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if (cpuhw->n_events == 0) {
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/* disable exceptions if no events are running */
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cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE);
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cpuhw->mmcr.mmcr0 &= ~(MMCR0_PMXE | MMCR0_FCECE);
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}
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if (has_branch_stack(event))
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@ -2240,7 +2235,7 @@ static void __perf_event_interrupt(struct pt_regs *regs)
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* XXX might want to use MSR.PM to keep the events frozen until
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* we get back out of this interrupt.
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*/
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write_mmcr0(cpuhw, cpuhw->mmcr[0]);
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write_mmcr0(cpuhw, cpuhw->mmcr.mmcr0);
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if (nmi)
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nmi_exit();
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@ -2262,7 +2257,7 @@ static int power_pmu_prepare_cpu(unsigned int cpu)
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if (ppmu) {
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memset(cpuhw, 0, sizeof(*cpuhw));
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cpuhw->mmcr[0] = MMCR0_FC;
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cpuhw->mmcr.mmcr0 = MMCR0_FC;
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}
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return 0;
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}
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@ -363,7 +363,7 @@ int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp)
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}
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int isa207_compute_mmcr(u64 event[], int n_ev,
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unsigned int hwc[], unsigned long mmcr[],
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unsigned int hwc[], struct mmcr_regs *mmcr,
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struct perf_event *pevents[])
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{
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unsigned long mmcra, mmcr1, mmcr2, unit, combine, psel, cache, val;
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@ -464,30 +464,30 @@ int isa207_compute_mmcr(u64 event[], int n_ev,
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}
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/* Return MMCRx values */
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mmcr[0] = 0;
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mmcr->mmcr0 = 0;
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/* pmc_inuse is 1-based */
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if (pmc_inuse & 2)
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mmcr[0] = MMCR0_PMC1CE;
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mmcr->mmcr0 = MMCR0_PMC1CE;
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if (pmc_inuse & 0x7c)
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mmcr[0] |= MMCR0_PMCjCE;
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mmcr->mmcr0 |= MMCR0_PMCjCE;
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/* If we're not using PMC 5 or 6, freeze them */
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if (!(pmc_inuse & 0x60))
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mmcr[0] |= MMCR0_FC56;
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mmcr->mmcr0 |= MMCR0_FC56;
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mmcr[1] = mmcr1;
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mmcr[2] = mmcra;
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mmcr[3] = mmcr2;
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mmcr->mmcr1 = mmcr1;
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mmcr->mmcra = mmcra;
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mmcr->mmcr2 = mmcr2;
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return 0;
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}
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void isa207_disable_pmc(unsigned int pmc, unsigned long mmcr[])
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void isa207_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr)
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{
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if (pmc <= 3)
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mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SHIFT(pmc + 1));
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mmcr->mmcr1 &= ~(0xffUL << MMCR1_PMCSEL_SHIFT(pmc + 1));
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}
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static int find_alternative(u64 event, const unsigned int ev_alt[][MAX_ALT], int size)
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@ -217,9 +217,9 @@
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int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp);
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int isa207_compute_mmcr(u64 event[], int n_ev,
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unsigned int hwc[], unsigned long mmcr[],
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unsigned int hwc[], struct mmcr_regs *mmcr,
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struct perf_event *pevents[]);
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void isa207_disable_pmc(unsigned int pmc, unsigned long mmcr[]);
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void isa207_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr);
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int isa207_get_alternatives(u64 event, u64 alt[], int size, unsigned int flags,
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const unsigned int ev_alt[][MAX_ALT]);
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void isa207_get_mem_data_src(union perf_mem_data_src *dsrc, u32 flags,
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@ -257,7 +257,7 @@ static const u32 pmcsel_mask[N_COUNTER] = {
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* Compute MMCR0/1/2 values for a set of events.
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*/
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static int mpc7450_compute_mmcr(u64 event[], int n_ev, unsigned int hwc[],
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unsigned long mmcr[],
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struct mmcr_regs *mmcr,
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struct perf_event *pevents[])
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{
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u8 event_index[N_CLASSES][N_COUNTER];
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@ -321,9 +321,16 @@ static int mpc7450_compute_mmcr(u64 event[], int n_ev, unsigned int hwc[],
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mmcr0 |= MMCR0_PMCnCE;
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/* Return MMCRx values */
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mmcr[0] = mmcr0;
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mmcr[1] = mmcr1;
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mmcr[2] = mmcr2;
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mmcr->mmcr0 = mmcr0;
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mmcr->mmcr1 = mmcr1;
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mmcr->mmcr2 = mmcr2;
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/*
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* 32-bit doesn't have an MMCRA and uses SPRN_MMCR2 to define
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* SPRN_MMCRA. So assign mmcra of cpu_hw_events with `mmcr2`
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* value to ensure that any write to this SPRN_MMCRA will
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* use mmcr2 value.
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*/
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mmcr->mmcra = mmcr2;
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return 0;
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}
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@ -331,12 +338,12 @@ static int mpc7450_compute_mmcr(u64 event[], int n_ev, unsigned int hwc[],
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* Disable counting by a PMC.
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* Note that the pmc argument is 0-based here, not 1-based.
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*/
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static void mpc7450_disable_pmc(unsigned int pmc, unsigned long mmcr[])
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static void mpc7450_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr)
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{
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if (pmc <= 1)
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mmcr[0] &= ~(pmcsel_mask[pmc] << pmcsel_shift[pmc]);
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mmcr->mmcr0 &= ~(pmcsel_mask[pmc] << pmcsel_shift[pmc]);
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else
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mmcr[1] &= ~(pmcsel_mask[pmc] << pmcsel_shift[pmc]);
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mmcr->mmcr1 &= ~(pmcsel_mask[pmc] << pmcsel_shift[pmc]);
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}
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static int mpc7450_generic_events[] = {
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@ -448,7 +448,8 @@ static int power5p_marked_instr_event(u64 event)
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}
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static int power5p_compute_mmcr(u64 event[], int n_ev,
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unsigned int hwc[], unsigned long mmcr[], struct perf_event *pevents[])
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unsigned int hwc[], struct mmcr_regs *mmcr,
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struct perf_event *pevents[])
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{
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unsigned long mmcr1 = 0;
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unsigned long mmcra = 0;
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@ -586,20 +587,20 @@ static int power5p_compute_mmcr(u64 event[], int n_ev,
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}
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/* Return MMCRx values */
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mmcr[0] = 0;
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mmcr->mmcr0 = 0;
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if (pmc_inuse & 1)
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mmcr[0] = MMCR0_PMC1CE;
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mmcr->mmcr0 = MMCR0_PMC1CE;
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if (pmc_inuse & 0x3e)
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mmcr[0] |= MMCR0_PMCjCE;
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mmcr[1] = mmcr1;
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mmcr[2] = mmcra;
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mmcr->mmcr0 |= MMCR0_PMCjCE;
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mmcr->mmcr1 = mmcr1;
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mmcr->mmcra = mmcra;
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return 0;
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}
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static void power5p_disable_pmc(unsigned int pmc, unsigned long mmcr[])
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static void power5p_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr)
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{
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if (pmc <= 3)
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mmcr[1] &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc));
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mmcr->mmcr1 &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc));
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}
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static int power5p_generic_events[] = {
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@ -379,7 +379,8 @@ static int power5_marked_instr_event(u64 event)
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}
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static int power5_compute_mmcr(u64 event[], int n_ev,
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unsigned int hwc[], unsigned long mmcr[], struct perf_event *pevents[])
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unsigned int hwc[], struct mmcr_regs *mmcr,
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struct perf_event *pevents[])
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{
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unsigned long mmcr1 = 0;
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unsigned long mmcra = MMCRA_SDAR_DCACHE_MISS | MMCRA_SDAR_ERAT_MISS;
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@ -528,20 +529,20 @@ static int power5_compute_mmcr(u64 event[], int n_ev,
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}
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/* Return MMCRx values */
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mmcr[0] = 0;
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mmcr->mmcr0 = 0;
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if (pmc_inuse & 1)
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mmcr[0] = MMCR0_PMC1CE;
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mmcr->mmcr0 = MMCR0_PMC1CE;
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if (pmc_inuse & 0x3e)
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mmcr[0] |= MMCR0_PMCjCE;
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mmcr[1] = mmcr1;
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mmcr[2] = mmcra;
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mmcr->mmcr0 |= MMCR0_PMCjCE;
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mmcr->mmcr1 = mmcr1;
|
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mmcr->mmcra = mmcra;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void power5_disable_pmc(unsigned int pmc, unsigned long mmcr[])
|
||||
static void power5_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr)
|
||||
{
|
||||
if (pmc <= 3)
|
||||
mmcr[1] &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc));
|
||||
mmcr->mmcr1 &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc));
|
||||
}
|
||||
|
||||
static int power5_generic_events[] = {
|
||||
|
|
|
|||
|
|
@ -171,7 +171,7 @@ static int power6_marked_instr_event(u64 event)
|
|||
* Assign PMC numbers and compute MMCR1 value for a set of events
|
||||
*/
|
||||
static int p6_compute_mmcr(u64 event[], int n_ev,
|
||||
unsigned int hwc[], unsigned long mmcr[], struct perf_event *pevents[])
|
||||
unsigned int hwc[], struct mmcr_regs *mmcr, struct perf_event *pevents[])
|
||||
{
|
||||
unsigned long mmcr1 = 0;
|
||||
unsigned long mmcra = MMCRA_SDAR_DCACHE_MISS | MMCRA_SDAR_ERAT_MISS;
|
||||
|
|
@ -243,13 +243,13 @@ static int p6_compute_mmcr(u64 event[], int n_ev,
|
|||
if (pmc < 4)
|
||||
mmcr1 |= (unsigned long)psel << MMCR1_PMCSEL_SH(pmc);
|
||||
}
|
||||
mmcr[0] = 0;
|
||||
mmcr->mmcr0 = 0;
|
||||
if (pmc_inuse & 1)
|
||||
mmcr[0] = MMCR0_PMC1CE;
|
||||
mmcr->mmcr0 = MMCR0_PMC1CE;
|
||||
if (pmc_inuse & 0xe)
|
||||
mmcr[0] |= MMCR0_PMCjCE;
|
||||
mmcr[1] = mmcr1;
|
||||
mmcr[2] = mmcra;
|
||||
mmcr->mmcr0 |= MMCR0_PMCjCE;
|
||||
mmcr->mmcr1 = mmcr1;
|
||||
mmcr->mmcra = mmcra;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -457,11 +457,11 @@ static int p6_get_alternatives(u64 event, unsigned int flags, u64 alt[])
|
|||
return nalt;
|
||||
}
|
||||
|
||||
static void p6_disable_pmc(unsigned int pmc, unsigned long mmcr[])
|
||||
static void p6_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr)
|
||||
{
|
||||
/* Set PMCxSEL to 0 to disable PMCx */
|
||||
if (pmc <= 3)
|
||||
mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc));
|
||||
mmcr->mmcr1 &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc));
|
||||
}
|
||||
|
||||
static int power6_generic_events[] = {
|
||||
|
|
|
|||
|
|
@ -242,7 +242,8 @@ static int power7_marked_instr_event(u64 event)
|
|||
}
|
||||
|
||||
static int power7_compute_mmcr(u64 event[], int n_ev,
|
||||
unsigned int hwc[], unsigned long mmcr[], struct perf_event *pevents[])
|
||||
unsigned int hwc[], struct mmcr_regs *mmcr,
|
||||
struct perf_event *pevents[])
|
||||
{
|
||||
unsigned long mmcr1 = 0;
|
||||
unsigned long mmcra = MMCRA_SDAR_DCACHE_MISS | MMCRA_SDAR_ERAT_MISS;
|
||||
|
|
@ -298,20 +299,20 @@ static int power7_compute_mmcr(u64 event[], int n_ev,
|
|||
}
|
||||
|
||||
/* Return MMCRx values */
|
||||
mmcr[0] = 0;
|
||||
mmcr->mmcr0 = 0;
|
||||
if (pmc_inuse & 1)
|
||||
mmcr[0] = MMCR0_PMC1CE;
|
||||
mmcr->mmcr0 = MMCR0_PMC1CE;
|
||||
if (pmc_inuse & 0x3e)
|
||||
mmcr[0] |= MMCR0_PMCjCE;
|
||||
mmcr[1] = mmcr1;
|
||||
mmcr[2] = mmcra;
|
||||
mmcr->mmcr0 |= MMCR0_PMCjCE;
|
||||
mmcr->mmcr1 = mmcr1;
|
||||
mmcr->mmcra = mmcra;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[])
|
||||
static void power7_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr)
|
||||
{
|
||||
if (pmc <= 3)
|
||||
mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc));
|
||||
mmcr->mmcr1 &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc));
|
||||
}
|
||||
|
||||
static int power7_generic_events[] = {
|
||||
|
|
|
|||
|
|
@ -253,7 +253,8 @@ static int p970_get_alternatives(u64 event, unsigned int flags, u64 alt[])
|
|||
}
|
||||
|
||||
static int p970_compute_mmcr(u64 event[], int n_ev,
|
||||
unsigned int hwc[], unsigned long mmcr[], struct perf_event *pevents[])
|
||||
unsigned int hwc[], struct mmcr_regs *mmcr,
|
||||
struct perf_event *pevents[])
|
||||
{
|
||||
unsigned long mmcr0 = 0, mmcr1 = 0, mmcra = 0;
|
||||
unsigned int pmc, unit, byte, psel;
|
||||
|
|
@ -393,27 +394,26 @@ static int p970_compute_mmcr(u64 event[], int n_ev,
|
|||
mmcra |= 0x2000; /* mark only one IOP per PPC instruction */
|
||||
|
||||
/* Return MMCRx values */
|
||||
mmcr[0] = mmcr0;
|
||||
mmcr[1] = mmcr1;
|
||||
mmcr[2] = mmcra;
|
||||
mmcr->mmcr0 = mmcr0;
|
||||
mmcr->mmcr1 = mmcr1;
|
||||
mmcr->mmcra = mmcra;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void p970_disable_pmc(unsigned int pmc, unsigned long mmcr[])
|
||||
static void p970_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr)
|
||||
{
|
||||
int shift, i;
|
||||
int shift;
|
||||
|
||||
if (pmc <= 1) {
|
||||
shift = MMCR0_PMC1SEL_SH - 7 * pmc;
|
||||
i = 0;
|
||||
} else {
|
||||
shift = MMCR1_PMC3SEL_SH - 5 * (pmc - 2);
|
||||
i = 1;
|
||||
}
|
||||
/*
|
||||
* Setting the PMCxSEL field to 0x08 disables PMC x.
|
||||
*/
|
||||
mmcr[i] = (mmcr[i] & ~(0x1fUL << shift)) | (0x08UL << shift);
|
||||
if (pmc <= 1) {
|
||||
shift = MMCR0_PMC1SEL_SH - 7 * pmc;
|
||||
mmcr->mmcr0 = (mmcr->mmcr0 & ~(0x1fUL << shift)) | (0x08UL << shift);
|
||||
} else {
|
||||
shift = MMCR1_PMC3SEL_SH - 5 * (pmc - 2);
|
||||
mmcr->mmcr1 = (mmcr->mmcr1 & ~(0x1fUL << shift)) | (0x08UL << shift);
|
||||
}
|
||||
}
|
||||
|
||||
static int ppc970_generic_events[] = {
|
||||
|
|
|
|||
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