cirrusfb: various Laguna fixes
- The Laguna GD5465 (AGP) has one register more than non-AGP chips. Recognize the AGP version and write a tile control register only on the AGP version. Tested only on an AGP card. - Bump up RAMDAC frequencies after X11 code. This allow to drive a flat panel resolution 1680x1050 at 16bpp from the 4MB card. - Fix screen start address overflow bits on Laguna cards (CRT1D register). - Fix exit path in the cirrusfb_pci_register() in case of error. Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Krzysztof Helt
Linus Torvalds
Родитель
99a4584752
Коммит
78d780e072
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@ -102,7 +102,8 @@ enum cirrus_board {
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BT_PICASSO4, /* GD5446 */
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BT_ALPINE, /* GD543x/4x */
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BT_GD5480,
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BT_LAGUNA, /* GD546x */
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BT_LAGUNA, /* GD5462/64 */
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BT_LAGUNAB, /* GD5465 */
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};
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/*
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@ -234,8 +235,18 @@ static const struct cirrusfb_board_info_rec {
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[BT_LAGUNA] = {
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.name = "CL Laguna",
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.maxclock = {
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/* guess */
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135100, 135100, 135100, 135100, 135100,
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/* taken from X11 code */
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170000, 170000, 170000, 170000, 135100,
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},
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.init_sr07 = false,
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.init_sr1f = false,
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.scrn_start_bit19 = true,
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},
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[BT_LAGUNAB] = {
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.name = "CL Laguna AGP",
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.maxclock = {
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/* taken from X11 code */
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170000, 250000, 170000, 170000, 135100,
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},
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.init_sr07 = false,
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.init_sr1f = false,
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@ -258,7 +269,7 @@ static struct pci_device_id cirrusfb_pci_table[] = {
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CHIP(PCI_DEVICE_ID_CIRRUS_5446, BT_PICASSO4), /* Picasso 4 is 5446 */
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CHIP(PCI_DEVICE_ID_CIRRUS_5462, BT_LAGUNA), /* CL Laguna */
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CHIP(PCI_DEVICE_ID_CIRRUS_5464, BT_LAGUNA), /* CL Laguna 3D */
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CHIP(PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNA), /* CL Laguna 3DA*/
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CHIP(PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNAB), /* CL Laguna 3DA*/
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{ 0, }
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};
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MODULE_DEVICE_TABLE(pci, cirrusfb_pci_table);
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@ -385,6 +396,11 @@ static void cirrusfb_dbg_print_regs(struct fb_info *info,
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/*****************************************************************************/
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/*** BEGIN Interface Used by the World ***************************************/
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static inline int is_laguna(const struct cirrusfb_info *cinfo)
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{
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return cinfo->btype == BT_LAGUNA || cinfo->btype == BT_LAGUNAB;
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}
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static int opencount;
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/*--- Open /dev/fbx ---------------------------------------------------------*/
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@ -814,13 +830,16 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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cirrusfb_set_mclk_as_source(info, divMCLK);
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}
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}
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if (cinfo->btype == BT_LAGUNA) {
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if (is_laguna(cinfo)) {
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long pcifc = fb_readl(cinfo->laguna_mmio + 0x3fc);
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unsigned char tile = fb_readb(cinfo->laguna_mmio + 0x407);
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unsigned short tile_control;
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tile_control = fb_readw(cinfo->laguna_mmio + 0x2c4);
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fb_writew(tile_control & ~0x80, cinfo->laguna_mmio + 0x2c4);
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if (cinfo->btype == BT_LAGUNAB) {
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tile_control = fb_readw(cinfo->laguna_mmio + 0x2c4);
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tile_control &= ~0x80;
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fb_writew(tile_control, cinfo->laguna_mmio + 0x2c4);
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}
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fb_writel(pcifc | 0x10000000l, cinfo->laguna_mmio + 0x3fc);
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fb_writeb(tile & 0x3f, cinfo->laguna_mmio + 0x407);
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@ -842,7 +861,7 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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dev_dbg(info->device, "CL_SEQR1B: %d\n", (int) tmp);
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/* Laguna chipset has reversed clock registers */
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if (cinfo->btype == BT_LAGUNA) {
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if (is_laguna(cinfo)) {
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vga_wseq(regbase, CL_SEQRE, tmp);
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vga_wseq(regbase, CL_SEQR1E, nom);
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} else {
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@ -873,7 +892,7 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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tmp |= 0x40;
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if (var->sync & FB_SYNC_VERT_HIGH_ACT)
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tmp |= 0x80;
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if (cinfo->btype == BT_LAGUNA)
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if (is_laguna(cinfo))
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tmp |= 0xc;
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WGen(cinfo, VGA_MIS_W, tmp);
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@ -908,6 +927,7 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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break;
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case BT_LAGUNA:
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case BT_LAGUNAB:
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vga_wseq(regbase, CL_SEQR7,
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vga_rseq(regbase, CL_SEQR7) & ~0x01);
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break;
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@ -947,6 +967,7 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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case BT_ALPINE:
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case BT_GD5480:
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case BT_LAGUNA:
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case BT_LAGUNAB:
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/* do nothing */
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break;
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@ -991,6 +1012,7 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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break;
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case BT_LAGUNA:
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case BT_LAGUNAB:
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vga_wseq(regbase, CL_SEQR7,
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vga_rseq(regbase, CL_SEQR7) | 0x01);
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threshold |= 0x10;
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@ -1030,6 +1052,7 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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case BT_GD5480:
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case BT_LAGUNA:
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case BT_LAGUNAB:
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/* do nothing */
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break;
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@ -1096,6 +1119,7 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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break;
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case BT_LAGUNA:
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case BT_LAGUNAB:
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vga_wseq(regbase, CL_SEQR7,
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vga_rseq(regbase, CL_SEQR7) & ~0x01);
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control |= 0x2000;
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@ -1166,6 +1190,7 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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break;
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case BT_LAGUNA:
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case BT_LAGUNAB:
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vga_wseq(regbase, CL_SEQR7,
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vga_rseq(regbase, CL_SEQR7) & ~0x01);
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control |= 0x6000;
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@ -1208,7 +1233,7 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19)
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vga_wcrt(regbase, CL_CRT1D, (pitch >> 9) & 1);
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if (cinfo->btype == BT_LAGUNA) {
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if (is_laguna(cinfo)) {
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tmp = 0;
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if ((htotal + 5) & 256)
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tmp |= 128;
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@ -1234,7 +1259,7 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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/* From SetOffset(): Turn on VideoEnable bit in Attribute controller */
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AttrOn(cinfo);
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if (cinfo->btype == BT_LAGUNA) {
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if (is_laguna(cinfo)) {
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/* no tiles */
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fb_writew(control | 0x1000, cinfo->laguna_mmio + 0x402);
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fb_writew(format, cinfo->laguna_mmio + 0xc0);
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@ -1332,7 +1357,7 @@ static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
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xpix = (unsigned char) ((xoffset % 4) * 2);
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}
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if (cinfo->btype != BT_LAGUNA)
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if (!is_laguna(cinfo))
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cirrusfb_WaitBLT(cinfo->regbase);
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/* lower 8 + 8 bits of screen start address */
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@ -1353,8 +1378,11 @@ static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
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/* construct bit 19 of screen start address */
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if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) {
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tmp = vga_rcrt(cinfo->regbase, CL_CRT1D) & ~0x80;
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tmp |= (base >> 12) & 0x80;
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tmp = vga_rcrt(cinfo->regbase, CL_CRT1D);
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if (is_laguna(cinfo))
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tmp = (tmp & ~0x18) | ((base >> 16) & 0x18);
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else
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tmp = (tmp & ~0x80) | ((base >> 12) & 0x80);
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vga_wcrt(cinfo->regbase, CL_CRT1D, tmp);
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}
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@ -1365,7 +1393,7 @@ static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
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if (info->var.bits_per_pixel == 1)
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vga_wattr(cinfo->regbase, CL_AR33, xpix);
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if (cinfo->btype != BT_LAGUNA)
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if (!is_laguna(cinfo))
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cirrusfb_WaitBLT(cinfo->regbase);
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return 0;
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@ -1486,6 +1514,7 @@ static void init_vgachip(struct fb_info *info)
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break;
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case BT_LAGUNA:
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case BT_LAGUNAB:
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case BT_ALPINE:
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/* Nothing to do to reset the board. */
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break;
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@ -1530,6 +1559,7 @@ static void init_vgachip(struct fb_info *info)
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break;
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case BT_ALPINE:
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case BT_LAGUNA:
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case BT_LAGUNAB:
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break;
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case BT_SD64:
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vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8);
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@ -1611,7 +1641,7 @@ static void init_vgachip(struct fb_info *info)
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/* Bit Mask: no mask at all */
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vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff);
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if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_LAGUNA)
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if (cinfo->btype == BT_ALPINE || is_laguna(cinfo))
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/* (5434 can't have bit 3 set for bitblt) */
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vga_wgfx(cinfo->regbase, CL_GRB, 0x20);
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else
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@ -1802,7 +1832,7 @@ static void cirrusfb_imageblit(struct fb_info *info,
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{
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struct cirrusfb_info *cinfo = info->par;
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if (cinfo->btype != BT_LAGUNA)
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if (!is_laguna(cinfo))
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cirrusfb_WaitBLT(cinfo->regbase);
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cfb_imageblit(info, image);
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}
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@ -1831,7 +1861,7 @@ static unsigned int __devinit cirrusfb_get_memsize(struct fb_info *info,
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unsigned long mem;
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struct cirrusfb_info *cinfo = info->par;
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if (cinfo->btype == BT_LAGUNA) {
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if (is_laguna(cinfo)) {
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unsigned char SR14 = vga_rseq(regbase, CL_SEQR14);
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mem = ((SR14 & 7) + 1) << 20;
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@ -1950,7 +1980,7 @@ static int __devinit cirrusfb_set_fbinfo(struct fb_info *info)
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| FBINFO_HWACCEL_YPAN
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| FBINFO_HWACCEL_FILLRECT
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| FBINFO_HWACCEL_COPYAREA;
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if (noaccel || cinfo->btype == BT_LAGUNA)
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if (noaccel || is_laguna(cinfo))
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info->flags |= FBINFO_HWACCEL_DISABLED;
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info->fbops = &cirrusfb_ops;
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if (cinfo->btype == BT_GD5480) {
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@ -2060,7 +2090,7 @@ static int __devinit cirrusfb_pci_register(struct pci_dev *pdev,
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if (!info) {
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printk(KERN_ERR "cirrusfb: could not allocate memory\n");
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ret = -ENOMEM;
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goto err_disable;
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goto err_out;
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}
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cinfo = info->par;
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@ -2127,10 +2157,11 @@ static int __devinit cirrusfb_pci_register(struct pci_dev *pdev,
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pci_set_drvdata(pdev, info);
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ret = cirrusfb_register(info);
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if (ret)
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iounmap(info->screen_base);
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return ret;
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if (!ret)
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return 0;
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pci_set_drvdata(pdev, NULL);
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iounmap(info->screen_base);
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err_release_legacy:
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if (release_io_ports)
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release_region(0x3C0, 32);
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@ -2140,10 +2171,9 @@ err_release_regions:
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#endif
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pci_release_regions(pdev);
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err_release_fb:
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if (cinfo->laguna_mmio == NULL)
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if (cinfo->laguna_mmio != NULL)
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iounmap(cinfo->laguna_mmio);
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framebuffer_release(info);
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err_disable:
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err_out:
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return ret;
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}
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@ -2439,7 +2469,7 @@ static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val)
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{
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unsigned char dummy;
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if (cinfo->btype == BT_LAGUNA)
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if (is_laguna(cinfo))
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return;
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if (cinfo->btype == BT_PICASSO) {
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/* Klaus' hint for correct access to HDR on some boards */
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@ -2509,7 +2539,7 @@ static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned ch
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if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
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cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480 ||
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cinfo->btype == BT_LAGUNA) {
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is_laguna(cinfo)) {
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/* but DAC data register IS, at least for Picasso II */
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if (cinfo->btype == BT_PICASSO)
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data += 0xfff;
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