perf_counter, x86: Fix APIC NMI programming
My Nehalem box locks up in certain situations (with an always-asserted NMI causing a lockup) if the PMU LVT entry is programmed between NMI and IRQ mode with a high frequency. Standardize exlusively on NMIs instead. [ Impact: fix lockup ] Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Mike Galbraith <efault@gmx.de> Cc: Paul Mackerras <paulus@samba.org> Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com> Cc: Marcelo Tosatti <mtosatti@redhat.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: John Kacur <jkacur@redhat.com> LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -285,14 +285,10 @@ static int __hw_perf_counter_init(struct perf_counter *counter)
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hwc->config |= ARCH_PERFMON_EVENTSEL_OS;
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/*
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* If privileged enough, allow NMI events:
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* Use NMI events all the time:
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*/
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hwc->nmi = 0;
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if (hw_event->nmi) {
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if (sysctl_perf_counter_priv && !capable(CAP_SYS_ADMIN))
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return -EACCES;
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hwc->nmi = 1;
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}
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hw_event->nmi = 1;
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if (!hwc->irq_period)
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hwc->irq_period = x86_pmu.max_period;
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@ -553,9 +549,6 @@ fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc)
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if (!x86_pmu.num_counters_fixed)
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return -1;
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if (unlikely(hwc->nmi))
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return -1;
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event = hwc->config & ARCH_PERFMON_EVENT_MASK;
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if (unlikely(event == x86_pmu.event_map(PERF_COUNT_INSTRUCTIONS)))
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@ -806,9 +799,6 @@ static int amd_pmu_handle_irq(struct pt_regs *regs, int nmi)
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counter = cpuc->counters[idx];
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hwc = &counter->hw;
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if (counter->hw_event.nmi != nmi)
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continue;
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val = x86_perf_counter_update(counter, hwc, idx);
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if (val & (1ULL << (x86_pmu.counter_bits - 1)))
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continue;
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