Merge branches 'clk-cleanup', 'clk-bindings', 'clk-renesas', 'clk-versa' and 'clk-amlogic' into clk-next
- Support for Versa 5P49V60 clks * clk-cleanup: clk: rs9: Drop unused pin_xin field clk: sprd: Add dependency for SPRD_UMS512_CLK clk: ralink: fix 'mt7621_gate_is_enabled()' function dt-bindings: clock: remove stih416 bindings drivers/clk: Remove "select SRCU" * clk-bindings: dt-bindings: clock: qcom,sm8450-camcc: constrain required-opps dt-bindings: clock: imx8m-clock: correct i.MX8MQ node name * clk-renesas: clk: renesas: rcar-gen3: Disable R-Car H3 ES1.* clk: renesas: r8a779g0: Add CAN-FD clocks clk: renesas: r8a779g0: Tidy up DMAC name on SYS-DMAC clk: renesas: r8a779a0: Tidy up DMAC name on SYS-DMAC clk: renesas: r8a779g0: Add custom clock for PLL2 clk: renesas: cpg-mssr: Remove superfluous check in resume code clk: renesas: r9a06g032: Handle h2mode setting based on USBF presence clk: renesas: cpg-mssr: Fix use after free if cpg_mssr_common_init() failed clk: renesas: r9a07g044: Add clock and reset entries for CRU clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entries clk: renesas: r9a09g011: Add USB clock and reset entries clk: renesas: r9a09g011: Add TIM clock and reset entries clk: renesas: r8a779g0: Add display related clocks clk: renesas: rcar-gen4: Restore PLL enum sort order clk: renesas: r8a779g0: Fix OSC predividers clk: renesas: r9a09g011: Add PWM clock and reset entries * clk-versa: dt-bindings: clock: versaclock5: Document 5P49V60 compatible string clk: vc5: Add support for 5P49V60 clk: vc5: Use `clamp()` to restrict PLL range * clk-amlogic: clk: meson: clk-cpu-dyndiv: switch from .round_rate to .determine_rate clk: meson: sclk-div: switch from .round_rate to .determine_rate clk: meson: dualdiv: switch from .round_rate to .determine_rate clk: meson: mpll: Switch from .round_rate to .determine_rate
This commit is contained in:
Stephen Boyd
Коммит
792d682728
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@ -54,6 +54,7 @@ properties:
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- idt,5p49v5925
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- idt,5p49v5933
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- idt,5p49v5935
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- idt,5p49v60
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- idt,5p49v6901
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- idt,5p49v6965
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- idt,5p49v6975
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@ -108,7 +108,7 @@ examples:
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};
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- |
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clock-controller@30390000 {
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clock-controller@30380000 {
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compatible = "fsl,imx8mq-ccm";
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reg = <0x30380000 0x10000>;
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#clock-cells = <1>;
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@ -32,6 +32,7 @@ properties:
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A phandle and PM domain specifier for the MMCX power domain.
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required-opps:
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maxItems: 1
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description:
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A phandle to an OPP node describing required MMCX performance point.
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@ -122,9 +122,8 @@
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#define VC5_GLOBAL_REGISTER 0x76
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#define VC5_GLOBAL_REGISTER_GLOBAL_RESET BIT(5)
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/* PLL/VCO runs between 2.5 GHz and 3.0 GHz */
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/* The minimum VCO frequency is 2.5 GHz. The maximum is variant specific. */
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#define VC5_PLL_VCO_MIN 2500000000UL
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#define VC5_PLL_VCO_MAX 3000000000UL
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/* VC5 Input mux settings */
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#define VC5_MUX_IN_XIN BIT(0)
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@ -150,6 +149,7 @@ enum vc5_model {
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IDT_VC5_5P49V5925,
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IDT_VC5_5P49V5933,
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IDT_VC5_5P49V5935,
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IDT_VC6_5P49V60,
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IDT_VC6_5P49V6901,
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IDT_VC6_5P49V6965,
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IDT_VC6_5P49V6975,
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@ -161,6 +161,7 @@ struct vc5_chip_info {
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const unsigned int clk_fod_cnt;
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const unsigned int clk_out_cnt;
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const u32 flags;
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const unsigned long vco_max;
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};
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struct vc5_driver_data;
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@ -446,13 +447,11 @@ static long vc5_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
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struct vc5_driver_data *vc5 = hwdata->vc5;
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u32 div_int;
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u64 div_frc;
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if (rate < VC5_PLL_VCO_MIN)
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rate = VC5_PLL_VCO_MIN;
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if (rate > VC5_PLL_VCO_MAX)
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rate = VC5_PLL_VCO_MAX;
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rate = clamp(rate, VC5_PLL_VCO_MIN, vc5->chip_info->vco_max);
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/* Determine integer part, which is 12 bit wide */
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div_int = rate / *parent_rate;
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@ -1212,6 +1211,7 @@ static const struct vc5_chip_info idt_5p49v5923_info = {
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.clk_fod_cnt = 2,
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.clk_out_cnt = 3,
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.flags = 0,
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.vco_max = 3000000000UL,
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};
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static const struct vc5_chip_info idt_5p49v5925_info = {
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@ -1219,6 +1219,7 @@ static const struct vc5_chip_info idt_5p49v5925_info = {
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.clk_fod_cnt = 4,
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.clk_out_cnt = 5,
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.flags = 0,
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.vco_max = 3000000000UL,
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};
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static const struct vc5_chip_info idt_5p49v5933_info = {
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@ -1226,6 +1227,7 @@ static const struct vc5_chip_info idt_5p49v5933_info = {
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.clk_fod_cnt = 2,
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.clk_out_cnt = 3,
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.flags = VC5_HAS_INTERNAL_XTAL,
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.vco_max = 3000000000UL,
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};
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static const struct vc5_chip_info idt_5p49v5935_info = {
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@ -1233,6 +1235,15 @@ static const struct vc5_chip_info idt_5p49v5935_info = {
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.clk_fod_cnt = 4,
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.clk_out_cnt = 5,
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.flags = VC5_HAS_INTERNAL_XTAL,
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.vco_max = 3000000000UL,
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};
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static const struct vc5_chip_info idt_5p49v60_info = {
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.model = IDT_VC6_5P49V60,
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.clk_fod_cnt = 4,
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.clk_out_cnt = 5,
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.flags = VC5_HAS_PFD_FREQ_DBL | VC5_HAS_BYPASS_SYNC_BIT,
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.vco_max = 2700000000UL,
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};
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static const struct vc5_chip_info idt_5p49v6901_info = {
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@ -1240,6 +1251,7 @@ static const struct vc5_chip_info idt_5p49v6901_info = {
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.clk_fod_cnt = 4,
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.clk_out_cnt = 5,
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.flags = VC5_HAS_PFD_FREQ_DBL | VC5_HAS_BYPASS_SYNC_BIT,
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.vco_max = 3000000000UL,
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};
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static const struct vc5_chip_info idt_5p49v6965_info = {
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@ -1247,6 +1259,7 @@ static const struct vc5_chip_info idt_5p49v6965_info = {
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.clk_fod_cnt = 4,
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.clk_out_cnt = 5,
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.flags = VC5_HAS_BYPASS_SYNC_BIT,
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.vco_max = 3000000000UL,
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};
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static const struct vc5_chip_info idt_5p49v6975_info = {
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@ -1254,6 +1267,7 @@ static const struct vc5_chip_info idt_5p49v6975_info = {
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.clk_fod_cnt = 4,
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.clk_out_cnt = 5,
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.flags = VC5_HAS_BYPASS_SYNC_BIT | VC5_HAS_INTERNAL_XTAL,
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.vco_max = 3000000000UL,
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};
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static const struct i2c_device_id vc5_id[] = {
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@ -1261,6 +1275,7 @@ static const struct i2c_device_id vc5_id[] = {
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{ "5p49v5925", .driver_data = IDT_VC5_5P49V5925 },
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{ "5p49v5933", .driver_data = IDT_VC5_5P49V5933 },
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{ "5p49v5935", .driver_data = IDT_VC5_5P49V5935 },
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{ "5p49v60", .driver_data = IDT_VC6_5P49V60 },
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{ "5p49v6901", .driver_data = IDT_VC6_5P49V6901 },
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{ "5p49v6965", .driver_data = IDT_VC6_5P49V6965 },
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{ "5p49v6975", .driver_data = IDT_VC6_5P49V6975 },
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@ -1273,6 +1288,7 @@ static const struct of_device_id clk_vc5_of_match[] = {
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{ .compatible = "idt,5p49v5925", .data = &idt_5p49v5925_info },
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{ .compatible = "idt,5p49v5933", .data = &idt_5p49v5933_info },
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{ .compatible = "idt,5p49v5935", .data = &idt_5p49v5935_info },
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{ .compatible = "idt,5p49v60", .data = &idt_5p49v60_info },
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{ .compatible = "idt,5p49v6901", .data = &idt_5p49v6901_info },
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{ .compatible = "idt,5p49v6965", .data = &idt_5p49v6965_info },
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{ .compatible = "idt,5p49v6975", .data = &idt_5p49v6975_info },
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@ -27,14 +27,13 @@ static unsigned long meson_clk_cpu_dyndiv_recalc_rate(struct clk_hw *hw,
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NULL, 0, data->div.width);
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}
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static long meson_clk_cpu_dyndiv_round_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long *prate)
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static int meson_clk_cpu_dyndiv_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk);
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return divider_round_rate(hw, rate, prate, NULL, data->div.width, 0);
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return divider_determine_rate(hw, req, NULL, data->div.width, 0);
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}
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static int meson_clk_cpu_dyndiv_set_rate(struct clk_hw *hw, unsigned long rate,
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@ -63,7 +62,7 @@ static int meson_clk_cpu_dyndiv_set_rate(struct clk_hw *hw, unsigned long rate,
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const struct clk_ops meson_clk_cpu_dyndiv_ops = {
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.recalc_rate = meson_clk_cpu_dyndiv_recalc_rate,
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.round_rate = meson_clk_cpu_dyndiv_round_rate,
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.determine_rate = meson_clk_cpu_dyndiv_determine_rate,
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.set_rate = meson_clk_cpu_dyndiv_set_rate,
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};
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EXPORT_SYMBOL_GPL(meson_clk_cpu_dyndiv_ops);
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@ -86,18 +86,23 @@ __dualdiv_get_setting(unsigned long rate, unsigned long parent_rate,
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return (struct meson_clk_dualdiv_param *)&table[best_i];
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}
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static long meson_clk_dualdiv_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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static int meson_clk_dualdiv_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_clk_dualdiv_data *dualdiv = meson_clk_dualdiv_data(clk);
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const struct meson_clk_dualdiv_param *setting =
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__dualdiv_get_setting(rate, *parent_rate, dualdiv);
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const struct meson_clk_dualdiv_param *setting;
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if (!setting)
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return meson_clk_dualdiv_recalc_rate(hw, *parent_rate);
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setting = __dualdiv_get_setting(req->rate, req->best_parent_rate,
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dualdiv);
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if (setting)
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req->rate = __dualdiv_param_to_rate(req->best_parent_rate,
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setting);
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else
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req->rate = meson_clk_dualdiv_recalc_rate(hw,
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req->best_parent_rate);
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return __dualdiv_param_to_rate(*parent_rate, setting);
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return 0;
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}
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static int meson_clk_dualdiv_set_rate(struct clk_hw *hw, unsigned long rate,
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@ -122,7 +127,7 @@ static int meson_clk_dualdiv_set_rate(struct clk_hw *hw, unsigned long rate,
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const struct clk_ops meson_clk_dualdiv_ops = {
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.recalc_rate = meson_clk_dualdiv_recalc_rate,
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.round_rate = meson_clk_dualdiv_round_rate,
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.determine_rate = meson_clk_dualdiv_determine_rate,
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.set_rate = meson_clk_dualdiv_set_rate,
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};
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EXPORT_SYMBOL_GPL(meson_clk_dualdiv_ops);
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@ -87,16 +87,22 @@ static unsigned long mpll_recalc_rate(struct clk_hw *hw,
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return rate < 0 ? 0 : rate;
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}
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static long mpll_round_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long *parent_rate)
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static int mpll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);
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unsigned int sdm, n2;
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long rate;
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params_from_rate(rate, *parent_rate, &sdm, &n2, mpll->flags);
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return rate_from_params(*parent_rate, sdm, n2);
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params_from_rate(req->rate, req->best_parent_rate, &sdm, &n2,
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mpll->flags);
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rate = rate_from_params(req->best_parent_rate, sdm, n2);
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if (rate < 0)
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return rate;
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req->rate = rate;
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return 0;
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}
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static int mpll_set_rate(struct clk_hw *hw,
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@ -157,13 +163,13 @@ static int mpll_init(struct clk_hw *hw)
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const struct clk_ops meson_clk_mpll_ro_ops = {
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.recalc_rate = mpll_recalc_rate,
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.round_rate = mpll_round_rate,
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.determine_rate = mpll_determine_rate,
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};
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EXPORT_SYMBOL_GPL(meson_clk_mpll_ro_ops);
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const struct clk_ops meson_clk_mpll_ops = {
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.recalc_rate = mpll_recalc_rate,
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.round_rate = mpll_round_rate,
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.determine_rate = mpll_determine_rate,
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.set_rate = mpll_set_rate,
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.init = mpll_init,
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};
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@ -96,16 +96,17 @@ static int sclk_div_bestdiv(struct clk_hw *hw, unsigned long rate,
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return bestdiv;
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}
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static long sclk_div_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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static int sclk_div_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk);
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int div;
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div = sclk_div_bestdiv(hw, rate, prate, sclk);
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div = sclk_div_bestdiv(hw, req->rate, &req->best_parent_rate, sclk);
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req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div);
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return DIV_ROUND_UP_ULL((u64)*prate, div);
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return 0;
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}
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static void sclk_apply_ratio(struct clk_regmap *clk,
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@ -237,7 +238,7 @@ static int sclk_div_init(struct clk_hw *hw)
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const struct clk_ops meson_sclk_div_ops = {
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.recalc_rate = sclk_div_recalc_rate,
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.round_rate = sclk_div_round_rate,
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.determine_rate = sclk_div_determine_rate,
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.set_rate = sclk_div_set_rate,
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.enable = sclk_div_enable,
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.disable = sclk_div_disable,
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|
|
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@ -22,7 +22,7 @@ config CLK_RENESAS
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select CLK_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793
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select CLK_R8A7792 if ARCH_R8A7792
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select CLK_R8A7794 if ARCH_R8A7794
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select CLK_R8A7795 if ARCH_R8A77950 || ARCH_R8A77951
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select CLK_R8A7795 if ARCH_R8A77951
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select CLK_R8A77960 if ARCH_R8A77960
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select CLK_R8A77961 if ARCH_R8A77961
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select CLK_R8A77965 if ARCH_R8A77965
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|
|
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|
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@ -128,7 +128,6 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
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};
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static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
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DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */
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DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),
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DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
|
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DEF_MOD("tmu4", 121, R8A7795_CLK_S0D6),
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|
|
@ -162,7 +161,6 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
|
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DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1),
|
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DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1),
|
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DEF_MOD("usb-dmac30", 326, R8A7795_CLK_S3D1),
|
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DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), /* ES1.x */
|
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DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac31", 329, R8A7795_CLK_S3D1),
|
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DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1),
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|
|
@ -187,28 +185,21 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
|
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DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
|
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DEF_MOD("thermal", 522, R8A7795_CLK_CP),
|
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DEF_MOD("pwm", 523, R8A7795_CLK_S0D12),
|
||||
DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), /* ES1.x */
|
||||
DEF_MOD("fcpvd2", 601, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("fcpvd1", 602, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("fcpvd0", 603, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("fcpvb1", 606, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("fcpvb0", 607, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1), /* ES1.x */
|
||||
DEF_MOD("fcpvi1", 610, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("fcpvi0", 611, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), /* ES1.x */
|
||||
DEF_MOD("fcpf1", 614, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("fcpf0", 615, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1), /* ES1.x */
|
||||
DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1), /* ES1.x */
|
||||
DEF_MOD("fcpcs", 619, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), /* ES1.x */
|
||||
DEF_MOD("vspd2", 621, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("vspd1", 622, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("vspd0", 623, R8A7795_CLK_S0D2),
|
||||
DEF_MOD("vspbc", 624, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("vspbd", 626, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */
|
||||
DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1),
|
||||
DEF_MOD("ehci3", 700, R8A7795_CLK_S3D2),
|
||||
|
|
@ -221,7 +212,6 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
|
|||
DEF_MOD("cmm2", 709, R8A7795_CLK_S2D1),
|
||||
DEF_MOD("cmm1", 710, R8A7795_CLK_S2D1),
|
||||
DEF_MOD("cmm0", 711, R8A7795_CLK_S2D1),
|
||||
DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */
|
||||
DEF_MOD("csi20", 714, R8A7795_CLK_CSI0),
|
||||
DEF_MOD("csi41", 715, R8A7795_CLK_CSI0),
|
||||
DEF_MOD("csi40", 716, R8A7795_CLK_CSI0),
|
||||
|
|
@ -350,103 +340,26 @@ static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
|
|||
{ 2, 192, 1, 192, 1, 32, },
|
||||
};
|
||||
|
||||
static const struct soc_device_attribute r8a7795es1[] __initconst = {
|
||||
static const struct soc_device_attribute r8a7795_denylist[] __initconst = {
|
||||
{ .soc_id = "r8a7795", .revision = "ES1.*" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* Fixups for R-Car H3 ES1.x
|
||||
*/
|
||||
|
||||
static const unsigned int r8a7795es1_mod_nullify[] __initconst = {
|
||||
MOD_CLK_ID(326), /* USB-DMAC3-0 */
|
||||
MOD_CLK_ID(329), /* USB-DMAC3-1 */
|
||||
MOD_CLK_ID(700), /* EHCI/OHCI3 */
|
||||
MOD_CLK_ID(705), /* HS-USB-IF3 */
|
||||
|
||||
};
|
||||
|
||||
static const struct mssr_mod_reparent r8a7795es1_mod_reparent[] __initconst = {
|
||||
{ MOD_CLK_ID(118), R8A7795_CLK_S2D1 }, /* FDP1-1 */
|
||||
{ MOD_CLK_ID(119), R8A7795_CLK_S2D1 }, /* FDP1-0 */
|
||||
{ MOD_CLK_ID(121), R8A7795_CLK_S3D2 }, /* TMU4 */
|
||||
{ MOD_CLK_ID(217), R8A7795_CLK_S3D1 }, /* SYS-DMAC2 */
|
||||
{ MOD_CLK_ID(218), R8A7795_CLK_S3D1 }, /* SYS-DMAC1 */
|
||||
{ MOD_CLK_ID(219), R8A7795_CLK_S3D1 }, /* SYS-DMAC0 */
|
||||
{ MOD_CLK_ID(408), R8A7795_CLK_S3D1 }, /* INTC-AP */
|
||||
{ MOD_CLK_ID(501), R8A7795_CLK_S3D1 }, /* AUDMAC1 */
|
||||
{ MOD_CLK_ID(502), R8A7795_CLK_S3D1 }, /* AUDMAC0 */
|
||||
{ MOD_CLK_ID(523), R8A7795_CLK_S3D4 }, /* PWM */
|
||||
{ MOD_CLK_ID(601), R8A7795_CLK_S2D1 }, /* FCPVD2 */
|
||||
{ MOD_CLK_ID(602), R8A7795_CLK_S2D1 }, /* FCPVD1 */
|
||||
{ MOD_CLK_ID(603), R8A7795_CLK_S2D1 }, /* FCPVD0 */
|
||||
{ MOD_CLK_ID(606), R8A7795_CLK_S2D1 }, /* FCPVB1 */
|
||||
{ MOD_CLK_ID(607), R8A7795_CLK_S2D1 }, /* FCPVB0 */
|
||||
{ MOD_CLK_ID(610), R8A7795_CLK_S2D1 }, /* FCPVI1 */
|
||||
{ MOD_CLK_ID(611), R8A7795_CLK_S2D1 }, /* FCPVI0 */
|
||||
{ MOD_CLK_ID(614), R8A7795_CLK_S2D1 }, /* FCPF1 */
|
||||
{ MOD_CLK_ID(615), R8A7795_CLK_S2D1 }, /* FCPF0 */
|
||||
{ MOD_CLK_ID(619), R8A7795_CLK_S2D1 }, /* FCPCS */
|
||||
{ MOD_CLK_ID(621), R8A7795_CLK_S2D1 }, /* VSPD2 */
|
||||
{ MOD_CLK_ID(622), R8A7795_CLK_S2D1 }, /* VSPD1 */
|
||||
{ MOD_CLK_ID(623), R8A7795_CLK_S2D1 }, /* VSPD0 */
|
||||
{ MOD_CLK_ID(624), R8A7795_CLK_S2D1 }, /* VSPBC */
|
||||
{ MOD_CLK_ID(626), R8A7795_CLK_S2D1 }, /* VSPBD */
|
||||
{ MOD_CLK_ID(630), R8A7795_CLK_S2D1 }, /* VSPI1 */
|
||||
{ MOD_CLK_ID(631), R8A7795_CLK_S2D1 }, /* VSPI0 */
|
||||
{ MOD_CLK_ID(804), R8A7795_CLK_S2D1 }, /* VIN7 */
|
||||
{ MOD_CLK_ID(805), R8A7795_CLK_S2D1 }, /* VIN6 */
|
||||
{ MOD_CLK_ID(806), R8A7795_CLK_S2D1 }, /* VIN5 */
|
||||
{ MOD_CLK_ID(807), R8A7795_CLK_S2D1 }, /* VIN4 */
|
||||
{ MOD_CLK_ID(808), R8A7795_CLK_S2D1 }, /* VIN3 */
|
||||
{ MOD_CLK_ID(809), R8A7795_CLK_S2D1 }, /* VIN2 */
|
||||
{ MOD_CLK_ID(810), R8A7795_CLK_S2D1 }, /* VIN1 */
|
||||
{ MOD_CLK_ID(811), R8A7795_CLK_S2D1 }, /* VIN0 */
|
||||
{ MOD_CLK_ID(812), R8A7795_CLK_S3D2 }, /* EAVB-IF */
|
||||
{ MOD_CLK_ID(820), R8A7795_CLK_S2D1 }, /* IMR3 */
|
||||
{ MOD_CLK_ID(821), R8A7795_CLK_S2D1 }, /* IMR2 */
|
||||
{ MOD_CLK_ID(822), R8A7795_CLK_S2D1 }, /* IMR1 */
|
||||
{ MOD_CLK_ID(823), R8A7795_CLK_S2D1 }, /* IMR0 */
|
||||
{ MOD_CLK_ID(905), R8A7795_CLK_CP }, /* GPIO7 */
|
||||
{ MOD_CLK_ID(906), R8A7795_CLK_CP }, /* GPIO6 */
|
||||
{ MOD_CLK_ID(907), R8A7795_CLK_CP }, /* GPIO5 */
|
||||
{ MOD_CLK_ID(908), R8A7795_CLK_CP }, /* GPIO4 */
|
||||
{ MOD_CLK_ID(909), R8A7795_CLK_CP }, /* GPIO3 */
|
||||
{ MOD_CLK_ID(910), R8A7795_CLK_CP }, /* GPIO2 */
|
||||
{ MOD_CLK_ID(911), R8A7795_CLK_CP }, /* GPIO1 */
|
||||
{ MOD_CLK_ID(912), R8A7795_CLK_CP }, /* GPIO0 */
|
||||
{ MOD_CLK_ID(918), R8A7795_CLK_S3D2 }, /* I2C6 */
|
||||
{ MOD_CLK_ID(919), R8A7795_CLK_S3D2 }, /* I2C5 */
|
||||
{ MOD_CLK_ID(927), R8A7795_CLK_S3D2 }, /* I2C4 */
|
||||
{ MOD_CLK_ID(928), R8A7795_CLK_S3D2 }, /* I2C3 */
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* Fixups for R-Car H3 ES2.x
|
||||
*/
|
||||
|
||||
static const unsigned int r8a7795es2_mod_nullify[] __initconst = {
|
||||
MOD_CLK_ID(117), /* FDP1-2 */
|
||||
MOD_CLK_ID(327), /* USB3-IF1 */
|
||||
MOD_CLK_ID(600), /* FCPVD3 */
|
||||
MOD_CLK_ID(609), /* FCPVI2 */
|
||||
MOD_CLK_ID(613), /* FCPF2 */
|
||||
MOD_CLK_ID(616), /* FCPCI1 */
|
||||
MOD_CLK_ID(617), /* FCPCI0 */
|
||||
MOD_CLK_ID(620), /* VSPD3 */
|
||||
MOD_CLK_ID(629), /* VSPI2 */
|
||||
MOD_CLK_ID(713), /* CSI21 */
|
||||
};
|
||||
|
||||
static int __init r8a7795_cpg_mssr_init(struct device *dev)
|
||||
{
|
||||
const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
|
||||
u32 cpg_mode;
|
||||
int error;
|
||||
|
||||
/*
|
||||
* We panic here to ensure removed SoCs and clk updates are always in
|
||||
* sync to avoid overclocking damages. The panic can only be seen with
|
||||
* commandline args 'earlycon keep_bootcon'. But these SoCs were for
|
||||
* developers only anyhow.
|
||||
*/
|
||||
if (soc_device_match(r8a7795_denylist))
|
||||
panic("SoC not supported anymore!\n");
|
||||
|
||||
error = rcar_rst_read_mode_pins(&cpg_mode);
|
||||
if (error)
|
||||
return error;
|
||||
|
|
@ -457,25 +370,6 @@ static int __init r8a7795_cpg_mssr_init(struct device *dev)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (soc_device_match(r8a7795es1)) {
|
||||
cpg_core_nullify_range(r8a7795_core_clks,
|
||||
ARRAY_SIZE(r8a7795_core_clks),
|
||||
R8A7795_CLK_S0D2, R8A7795_CLK_S0D12);
|
||||
mssr_mod_nullify(r8a7795_mod_clks,
|
||||
ARRAY_SIZE(r8a7795_mod_clks),
|
||||
r8a7795es1_mod_nullify,
|
||||
ARRAY_SIZE(r8a7795es1_mod_nullify));
|
||||
mssr_mod_reparent(r8a7795_mod_clks,
|
||||
ARRAY_SIZE(r8a7795_mod_clks),
|
||||
r8a7795es1_mod_reparent,
|
||||
ARRAY_SIZE(r8a7795es1_mod_reparent));
|
||||
} else {
|
||||
mssr_mod_nullify(r8a7795_mod_clks,
|
||||
ARRAY_SIZE(r8a7795_mod_clks),
|
||||
r8a7795es2_mod_nullify,
|
||||
ARRAY_SIZE(r8a7795es2_mod_nullify));
|
||||
}
|
||||
|
||||
return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -176,8 +176,8 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
|
|||
DEF_MOD("scif3", 704, R8A779A0_CLK_S1D8),
|
||||
DEF_MOD("scif4", 705, R8A779A0_CLK_S1D8),
|
||||
DEF_MOD("sdhi0", 706, R8A779A0_CLK_SD0),
|
||||
DEF_MOD("sydm1", 709, R8A779A0_CLK_S1D2),
|
||||
DEF_MOD("sydm2", 710, R8A779A0_CLK_S1D2),
|
||||
DEF_MOD("sys-dmac1", 709, R8A779A0_CLK_S1D2),
|
||||
DEF_MOD("sys-dmac2", 710, R8A779A0_CLK_S1D2),
|
||||
DEF_MOD("tmu0", 713, R8A779A0_CLK_CL16MCK),
|
||||
DEF_MOD("tmu1", 714, R8A779A0_CLK_S1D4),
|
||||
DEF_MOD("tmu2", 715, R8A779A0_CLK_S1D4),
|
||||
|
|
|
|||
|
|
@ -66,13 +66,13 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
|
|||
DEF_INPUT("extalr", CLK_EXTALR),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN),
|
||||
DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN4_PLL4, CLK_MAIN),
|
||||
DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
|
||||
DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN),
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN4_PLL2_VAR, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN4_PLL3, CLK_MAIN),
|
||||
DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN4_PLL4, CLK_MAIN),
|
||||
DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN),
|
||||
DEF_BASE(".pll6", CLK_PLL6, CLK_TYPE_GEN4_PLL6, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 2, 1),
|
||||
|
|
@ -145,6 +145,9 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
|
|||
DEF_FIXED("viobusd2", R8A779G0_CLK_VIOBUSD2, CLK_VIO, 2, 1),
|
||||
DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1),
|
||||
DEF_FIXED("vcbusd2", R8A779G0_CLK_VCBUSD2, CLK_VC, 2, 1),
|
||||
DEF_DIV6P1("canfd", R8A779G0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
|
||||
DEF_FIXED("dsiref", R8A779G0_CLK_DSIREF, CLK_PLL5_DIV4, 48, 1),
|
||||
DEF_DIV6P1("dsiext", R8A779G0_CLK_DSIEXT, CLK_PLL5_DIV4, 0x884),
|
||||
|
||||
DEF_GEN4_SDH("sd0h", R8A779G0_CLK_SD0H, CLK_SDSRC, 0x870),
|
||||
DEF_GEN4_SD("sd0", R8A779G0_CLK_SD0, R8A779G0_CLK_SD0H, 0x870),
|
||||
|
|
@ -161,6 +164,12 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
|
|||
DEF_MOD("avb0", 211, R8A779G0_CLK_S0D4_HSC),
|
||||
DEF_MOD("avb1", 212, R8A779G0_CLK_S0D4_HSC),
|
||||
DEF_MOD("avb2", 213, R8A779G0_CLK_S0D4_HSC),
|
||||
DEF_MOD("canfd0", 328, R8A779G0_CLK_SASYNCPERD2),
|
||||
DEF_MOD("dis0", 411, R8A779G0_CLK_VIOBUSD2),
|
||||
DEF_MOD("dsitxlink0", 415, R8A779G0_CLK_VIOBUSD2),
|
||||
DEF_MOD("dsitxlink1", 416, R8A779G0_CLK_VIOBUSD2),
|
||||
DEF_MOD("fcpvd0", 508, R8A779G0_CLK_VIOBUSD2),
|
||||
DEF_MOD("fcpvd1", 509, R8A779G0_CLK_VIOBUSD2),
|
||||
DEF_MOD("hscif0", 514, R8A779G0_CLK_SASYNCPERD1),
|
||||
DEF_MOD("hscif1", 515, R8A779G0_CLK_SASYNCPERD1),
|
||||
DEF_MOD("hscif2", 516, R8A779G0_CLK_SASYNCPERD1),
|
||||
|
|
@ -185,14 +194,16 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
|
|||
DEF_MOD("scif3", 704, R8A779G0_CLK_SASYNCPERD4),
|
||||
DEF_MOD("scif4", 705, R8A779G0_CLK_SASYNCPERD4),
|
||||
DEF_MOD("sdhi", 706, R8A779G0_CLK_SD0),
|
||||
DEF_MOD("sydm0", 709, R8A779G0_CLK_S0D6_PER),
|
||||
DEF_MOD("sydm1", 710, R8A779G0_CLK_S0D6_PER),
|
||||
DEF_MOD("sys-dmac0", 709, R8A779G0_CLK_S0D6_PER),
|
||||
DEF_MOD("sys-dmac1", 710, R8A779G0_CLK_S0D6_PER),
|
||||
DEF_MOD("tmu0", 713, R8A779G0_CLK_SASYNCRT),
|
||||
DEF_MOD("tmu1", 714, R8A779G0_CLK_SASYNCPERD2),
|
||||
DEF_MOD("tmu2", 715, R8A779G0_CLK_SASYNCPERD2),
|
||||
DEF_MOD("tmu3", 716, R8A779G0_CLK_SASYNCPERD2),
|
||||
DEF_MOD("tmu4", 717, R8A779G0_CLK_SASYNCPERD2),
|
||||
DEF_MOD("tpu0", 718, R8A779G0_CLK_SASYNCPERD4),
|
||||
DEF_MOD("vspd0", 830, R8A779G0_CLK_VIOBUSD2),
|
||||
DEF_MOD("vspd1", 831, R8A779G0_CLK_VIOBUSD2),
|
||||
DEF_MOD("wdt1:wdt0", 907, R8A779G0_CLK_R),
|
||||
DEF_MOD("cmt0", 910, R8A779G0_CLK_R),
|
||||
DEF_MOD("cmt1", 911, R8A779G0_CLK_R),
|
||||
|
|
@ -211,20 +222,20 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
|
|||
* MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
|
||||
* 14 13 (MHz)
|
||||
* ------------------------------------------------------------------------
|
||||
* 0 0 16.66 / 1 x192 x204 x192 x144 x192 x168 /15
|
||||
* 0 0 16.66 / 1 x192 x204 x192 x144 x192 x168 /16
|
||||
* 0 1 20 / 1 x160 x170 x160 x120 x160 x140 /19
|
||||
* 1 0 Prohibited setting
|
||||
* 1 1 33.33 / 2 x192 x204 x192 x144 x192 x168 /38
|
||||
* 1 1 33.33 / 2 x192 x204 x192 x144 x192 x168 /32
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
|
||||
(((md) & BIT(13)) >> 13))
|
||||
|
||||
static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
|
||||
/* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */
|
||||
{ 1, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1, 15, },
|
||||
{ 1, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1, 16, },
|
||||
{ 1, 160, 1, 170, 1, 160, 1, 120, 1, 160, 1, 140, 1, 19, },
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
|
||||
{ 2, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1, 38, },
|
||||
{ 2, 192, 1, 204, 1, 192, 1, 144, 1, 192, 1, 168, 1, 32, },
|
||||
};
|
||||
|
||||
static int __init r8a779g0_cpg_mssr_init(struct device *dev)
|
||||
|
|
|
|||
|
|
@ -25,6 +25,8 @@
|
|||
#include <linux/spinlock.h>
|
||||
#include <dt-bindings/clock/r9a06g032-sysctrl.h>
|
||||
|
||||
#define R9A06G032_SYSCTRL_USB 0x00
|
||||
#define R9A06G032_SYSCTRL_USB_H2MODE (1<<1)
|
||||
#define R9A06G032_SYSCTRL_DMAMUX 0xA0
|
||||
|
||||
struct r9a06g032_gate {
|
||||
|
|
@ -918,6 +920,29 @@ static void r9a06g032_clocks_del_clk_provider(void *data)
|
|||
of_clk_del_provider(data);
|
||||
}
|
||||
|
||||
static void __init r9a06g032_init_h2mode(struct r9a06g032_priv *clocks)
|
||||
{
|
||||
struct device_node *usbf_np = NULL;
|
||||
u32 usb;
|
||||
|
||||
while ((usbf_np = of_find_compatible_node(usbf_np, NULL,
|
||||
"renesas,rzn1-usbf"))) {
|
||||
if (of_device_is_available(usbf_np))
|
||||
break;
|
||||
}
|
||||
|
||||
usb = readl(clocks->reg + R9A06G032_SYSCTRL_USB);
|
||||
if (usbf_np) {
|
||||
/* 1 host and 1 device mode */
|
||||
usb &= ~R9A06G032_SYSCTRL_USB_H2MODE;
|
||||
of_node_put(usbf_np);
|
||||
} else {
|
||||
/* 2 hosts mode */
|
||||
usb |= R9A06G032_SYSCTRL_USB_H2MODE;
|
||||
}
|
||||
writel(usb, clocks->reg + R9A06G032_SYSCTRL_USB);
|
||||
}
|
||||
|
||||
static int __init r9a06g032_clocks_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
|
|
@ -947,6 +972,9 @@ static int __init r9a06g032_clocks_probe(struct platform_device *pdev)
|
|||
clocks->reg = of_iomap(np, 0);
|
||||
if (WARN_ON(!clocks->reg))
|
||||
return -ENOMEM;
|
||||
|
||||
r9a06g032_init_h2mode(clocks);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(r9a06g032_clocks); ++i) {
|
||||
const struct r9a06g032_clkdesc *d = &r9a06g032_clocks[i];
|
||||
const char *parent_name = d->source ?
|
||||
|
|
|
|||
|
|
@ -182,7 +182,7 @@ static const struct {
|
|||
};
|
||||
|
||||
static const struct {
|
||||
struct rzg2l_mod_clk common[75];
|
||||
struct rzg2l_mod_clk common[79];
|
||||
#ifdef CONFIG_CLK_R9A07G054
|
||||
struct rzg2l_mod_clk drp[0];
|
||||
#endif
|
||||
|
|
@ -250,6 +250,14 @@ static const struct {
|
|||
0x558, 1),
|
||||
DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1,
|
||||
0x558, 2),
|
||||
DEF_MOD("cru_sysclk", R9A07G044_CRU_SYSCLK, CLK_M2_DIV2,
|
||||
0x564, 0),
|
||||
DEF_MOD("cru_vclk", R9A07G044_CRU_VCLK, R9A07G044_CLK_M2,
|
||||
0x564, 1),
|
||||
DEF_MOD("cru_pclk", R9A07G044_CRU_PCLK, R9A07G044_CLK_ZT,
|
||||
0x564, 2),
|
||||
DEF_MOD("cru_aclk", R9A07G044_CRU_ACLK, R9A07G044_CLK_M0,
|
||||
0x564, 3),
|
||||
DEF_MOD("dsi_pll_clk", R9A07G044_MIPI_DSI_PLLCLK, R9A07G044_CLK_M1,
|
||||
0x568, 0),
|
||||
DEF_MOD("dsi_sys_clk", R9A07G044_MIPI_DSI_SYSCLK, CLK_M2_DIV2,
|
||||
|
|
@ -368,6 +376,9 @@ static struct rzg2l_reset r9a07g044_resets[] = {
|
|||
DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0),
|
||||
DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1),
|
||||
DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2),
|
||||
DEF_RST(R9A07G044_CRU_CMN_RSTB, 0x864, 0),
|
||||
DEF_RST(R9A07G044_CRU_PRESETN, 0x864, 1),
|
||||
DEF_RST(R9A07G044_CRU_ARESETN, 0x864, 2),
|
||||
DEF_RST(R9A07G044_MIPI_DSI_CMN_RSTB, 0x868, 0),
|
||||
DEF_RST(R9A07G044_MIPI_DSI_ARESET_N, 0x868, 1),
|
||||
DEF_RST(R9A07G044_MIPI_DSI_PRESET_N, 0x868, 2),
|
||||
|
|
@ -412,6 +423,11 @@ static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
|
|||
MOD_CLK_BASE + R9A07G044_DMAC_ACLK,
|
||||
};
|
||||
|
||||
static const unsigned int r9a07g044_no_pm_mod_clks[] = {
|
||||
MOD_CLK_BASE + R9A07G044_CRU_SYSCLK,
|
||||
MOD_CLK_BASE + R9A07G044_CRU_VCLK,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_CLK_R9A07G044
|
||||
const struct rzg2l_cpg_info r9a07g044_cpg_info = {
|
||||
/* Core Clocks */
|
||||
|
|
@ -429,6 +445,10 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = {
|
|||
.num_mod_clks = ARRAY_SIZE(mod_clks.common),
|
||||
.num_hw_mod_clks = R9A07G044_TSU_PCLK + 1,
|
||||
|
||||
/* No PM Module Clocks */
|
||||
.no_pm_mod_clks = r9a07g044_no_pm_mod_clks,
|
||||
.num_no_pm_mod_clks = ARRAY_SIZE(r9a07g044_no_pm_mod_clks),
|
||||
|
||||
/* Resets */
|
||||
.resets = r9a07g044_resets,
|
||||
.num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */
|
||||
|
|
@ -454,6 +474,10 @@ const struct rzg2l_cpg_info r9a07g054_cpg_info = {
|
|||
.num_mod_clks = ARRAY_SIZE(mod_clks.common) + ARRAY_SIZE(mod_clks.drp),
|
||||
.num_hw_mod_clks = R9A07G054_STPAI_ACLK_DRP + 1,
|
||||
|
||||
/* No PM Module Clocks */
|
||||
.no_pm_mod_clks = r9a07g044_no_pm_mod_clks,
|
||||
.num_no_pm_mod_clks = ARRAY_SIZE(r9a07g044_no_pm_mod_clks),
|
||||
|
||||
/* Resets */
|
||||
.resets = r9a07g044_resets,
|
||||
.num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */
|
||||
|
|
|
|||
|
|
@ -23,11 +23,14 @@
|
|||
|
||||
#define DIV_A DDIV_PACK(0x200, 0, 3)
|
||||
#define DIV_B DDIV_PACK(0x204, 0, 2)
|
||||
#define DIV_D DDIV_PACK(0x204, 4, 2)
|
||||
#define DIV_E DDIV_PACK(0x204, 8, 1)
|
||||
#define DIV_W DDIV_PACK(0x328, 0, 3)
|
||||
|
||||
#define SEL_B SEL_PLL_PACK(0x214, 0, 1)
|
||||
#define SEL_D SEL_PLL_PACK(0x214, 1, 1)
|
||||
#define SEL_E SEL_PLL_PACK(0x214, 2, 1)
|
||||
#define SEL_SDI SEL_PLL_PACK(0x300, 0, 1)
|
||||
#define SEL_W0 SEL_PLL_PACK(0x32C, 0, 1)
|
||||
|
||||
enum clk_ids {
|
||||
|
|
@ -50,11 +53,14 @@ enum clk_ids {
|
|||
CLK_PLL4,
|
||||
CLK_DIV_A,
|
||||
CLK_DIV_B,
|
||||
CLK_DIV_D,
|
||||
CLK_DIV_E,
|
||||
CLK_DIV_W,
|
||||
CLK_SEL_B,
|
||||
CLK_SEL_B_D2,
|
||||
CLK_SEL_D,
|
||||
CLK_SEL_E,
|
||||
CLK_SEL_SDI,
|
||||
CLK_SEL_W0,
|
||||
|
||||
/* Module Clocks */
|
||||
|
|
@ -81,6 +87,14 @@ static const struct clk_div_table dtable_divb[] = {
|
|||
{0, 0},
|
||||
};
|
||||
|
||||
static const struct clk_div_table dtable_divd[] = {
|
||||
{0, 1},
|
||||
{1, 2},
|
||||
{2, 4},
|
||||
{0, 0},
|
||||
};
|
||||
|
||||
|
||||
static const struct clk_div_table dtable_divw[] = {
|
||||
{0, 6},
|
||||
{1, 7},
|
||||
|
|
@ -94,8 +108,10 @@ static const struct clk_div_table dtable_divw[] = {
|
|||
|
||||
/* Mux clock tables */
|
||||
static const char * const sel_b[] = { ".main", ".divb" };
|
||||
static const char * const sel_d[] = { ".main", ".divd" };
|
||||
static const char * const sel_e[] = { ".main", ".dive" };
|
||||
static const char * const sel_w[] = { ".main", ".divw" };
|
||||
static const char * const sel_sdi[] = { ".main", ".pll2_200" };
|
||||
|
||||
static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = {
|
||||
/* External Clock Inputs */
|
||||
|
|
@ -115,11 +131,14 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = {
|
|||
|
||||
DEF_DIV_RO(".diva", CLK_DIV_A, CLK_PLL1, DIV_A, dtable_diva),
|
||||
DEF_DIV_RO(".divb", CLK_DIV_B, CLK_PLL2_400, DIV_B, dtable_divb),
|
||||
DEF_DIV_RO(".divd", CLK_DIV_D, CLK_PLL2_200, DIV_D, dtable_divd),
|
||||
DEF_DIV_RO(".dive", CLK_DIV_E, CLK_PLL2_100, DIV_E, NULL),
|
||||
DEF_DIV_RO(".divw", CLK_DIV_W, CLK_PLL4, DIV_W, dtable_divw),
|
||||
|
||||
DEF_MUX_RO(".selb", CLK_SEL_B, SEL_B, sel_b),
|
||||
DEF_MUX_RO(".seld", CLK_SEL_D, SEL_D, sel_d),
|
||||
DEF_MUX_RO(".sele", CLK_SEL_E, SEL_E, sel_e),
|
||||
DEF_MUX(".selsdi", CLK_SEL_SDI, SEL_SDI, sel_sdi),
|
||||
DEF_MUX(".selw0", CLK_SEL_W0, SEL_W0, sel_w),
|
||||
|
||||
DEF_FIXED(".selb_d2", CLK_SEL_B_D2, CLK_SEL_B, 1, 2),
|
||||
|
|
@ -128,14 +147,55 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = {
|
|||
static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = {
|
||||
DEF_MOD("pfc", R9A09G011_PFC_PCLK, CLK_MAIN, 0x400, 2),
|
||||
DEF_MOD("gic", R9A09G011_GIC_CLK, CLK_SEL_B_D2, 0x400, 5),
|
||||
DEF_MOD("sdi0_aclk", R9A09G011_SDI0_ACLK, CLK_SEL_D, 0x408, 0),
|
||||
DEF_MOD("sdi0_imclk", R9A09G011_SDI0_IMCLK, CLK_SEL_SDI, 0x408, 1),
|
||||
DEF_MOD("sdi0_imclk2", R9A09G011_SDI0_IMCLK2, CLK_SEL_SDI, 0x408, 2),
|
||||
DEF_MOD("sdi0_clk_hs", R9A09G011_SDI0_CLK_HS, CLK_PLL2_800, 0x408, 3),
|
||||
DEF_MOD("sdi1_aclk", R9A09G011_SDI1_ACLK, CLK_SEL_D, 0x408, 4),
|
||||
DEF_MOD("sdi1_imclk", R9A09G011_SDI1_IMCLK, CLK_SEL_SDI, 0x408, 5),
|
||||
DEF_MOD("sdi1_imclk2", R9A09G011_SDI1_IMCLK2, CLK_SEL_SDI, 0x408, 6),
|
||||
DEF_MOD("sdi1_clk_hs", R9A09G011_SDI1_CLK_HS, CLK_PLL2_800, 0x408, 7),
|
||||
DEF_MOD("emm_aclk", R9A09G011_EMM_ACLK, CLK_SEL_D, 0x408, 8),
|
||||
DEF_MOD("emm_imclk", R9A09G011_EMM_IMCLK, CLK_SEL_SDI, 0x408, 9),
|
||||
DEF_MOD("emm_imclk2", R9A09G011_EMM_IMCLK2, CLK_SEL_SDI, 0x408, 10),
|
||||
DEF_MOD("emm_clk_hs", R9A09G011_EMM_CLK_HS, CLK_PLL2_800, 0x408, 11),
|
||||
DEF_COUPLED("eth_axi", R9A09G011_ETH0_CLK_AXI, CLK_PLL2_200, 0x40c, 8),
|
||||
DEF_COUPLED("eth_chi", R9A09G011_ETH0_CLK_CHI, CLK_PLL2_100, 0x40c, 8),
|
||||
DEF_MOD("eth_clk_gptp", R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9),
|
||||
DEF_MOD("usb_aclk_h", R9A09G011_USB_ACLK_H, CLK_SEL_D, 0x40c, 4),
|
||||
DEF_MOD("usb_aclk_p", R9A09G011_USB_ACLK_P, CLK_SEL_D, 0x40c, 5),
|
||||
DEF_MOD("usb_pclk", R9A09G011_USB_PCLK, CLK_SEL_E, 0x40c, 6),
|
||||
DEF_MOD("syc_cnt_clk", R9A09G011_SYC_CNT_CLK, CLK_MAIN_24, 0x41c, 12),
|
||||
DEF_MOD("iic_pclk0", R9A09G011_IIC_PCLK0, CLK_SEL_E, 0x420, 12),
|
||||
DEF_MOD("cperi_grpb", R9A09G011_CPERI_GRPB_PCLK, CLK_SEL_E, 0x424, 0),
|
||||
DEF_MOD("tim_clk_8", R9A09G011_TIM8_CLK, CLK_MAIN_2, 0x424, 4),
|
||||
DEF_MOD("tim_clk_9", R9A09G011_TIM9_CLK, CLK_MAIN_2, 0x424, 5),
|
||||
DEF_MOD("tim_clk_10", R9A09G011_TIM10_CLK, CLK_MAIN_2, 0x424, 6),
|
||||
DEF_MOD("tim_clk_11", R9A09G011_TIM11_CLK, CLK_MAIN_2, 0x424, 7),
|
||||
DEF_MOD("tim_clk_12", R9A09G011_TIM12_CLK, CLK_MAIN_2, 0x424, 8),
|
||||
DEF_MOD("tim_clk_13", R9A09G011_TIM13_CLK, CLK_MAIN_2, 0x424, 9),
|
||||
DEF_MOD("tim_clk_14", R9A09G011_TIM14_CLK, CLK_MAIN_2, 0x424, 10),
|
||||
DEF_MOD("tim_clk_15", R9A09G011_TIM15_CLK, CLK_MAIN_2, 0x424, 11),
|
||||
DEF_MOD("iic_pclk1", R9A09G011_IIC_PCLK1, CLK_SEL_E, 0x424, 12),
|
||||
DEF_MOD("cperi_grpc", R9A09G011_CPERI_GRPC_PCLK, CLK_SEL_E, 0x428, 0),
|
||||
DEF_MOD("tim_clk_16", R9A09G011_TIM16_CLK, CLK_MAIN_2, 0x428, 4),
|
||||
DEF_MOD("tim_clk_17", R9A09G011_TIM17_CLK, CLK_MAIN_2, 0x428, 5),
|
||||
DEF_MOD("tim_clk_18", R9A09G011_TIM18_CLK, CLK_MAIN_2, 0x428, 6),
|
||||
DEF_MOD("tim_clk_19", R9A09G011_TIM19_CLK, CLK_MAIN_2, 0x428, 7),
|
||||
DEF_MOD("tim_clk_20", R9A09G011_TIM20_CLK, CLK_MAIN_2, 0x428, 8),
|
||||
DEF_MOD("tim_clk_21", R9A09G011_TIM21_CLK, CLK_MAIN_2, 0x428, 9),
|
||||
DEF_MOD("tim_clk_22", R9A09G011_TIM22_CLK, CLK_MAIN_2, 0x428, 10),
|
||||
DEF_MOD("tim_clk_23", R9A09G011_TIM23_CLK, CLK_MAIN_2, 0x428, 11),
|
||||
DEF_MOD("wdt0_pclk", R9A09G011_WDT0_PCLK, CLK_SEL_E, 0x428, 12),
|
||||
DEF_MOD("wdt0_clk", R9A09G011_WDT0_CLK, CLK_MAIN, 0x428, 13),
|
||||
DEF_MOD("cperi_grpf", R9A09G011_CPERI_GRPF_PCLK, CLK_SEL_E, 0x434, 0),
|
||||
DEF_MOD("pwm8_clk", R9A09G011_PWM8_CLK, CLK_MAIN, 0x434, 4),
|
||||
DEF_MOD("pwm9_clk", R9A09G011_PWM9_CLK, CLK_MAIN, 0x434, 5),
|
||||
DEF_MOD("pwm10_clk", R9A09G011_PWM10_CLK, CLK_MAIN, 0x434, 6),
|
||||
DEF_MOD("pwm11_clk", R9A09G011_PWM11_CLK, CLK_MAIN, 0x434, 7),
|
||||
DEF_MOD("pwm12_clk", R9A09G011_PWM12_CLK, CLK_MAIN, 0x434, 8),
|
||||
DEF_MOD("pwm13_clk", R9A09G011_PWM13_CLK, CLK_MAIN, 0x434, 9),
|
||||
DEF_MOD("pwm14_clk", R9A09G011_PWM14_CLK, CLK_MAIN, 0x434, 10),
|
||||
DEF_MOD("urt_pclk", R9A09G011_URT_PCLK, CLK_SEL_E, 0x438, 4),
|
||||
DEF_MOD("urt0_clk", R9A09G011_URT0_CLK, CLK_SEL_W0, 0x438, 5),
|
||||
DEF_MOD("ca53", R9A09G011_CA53_CLK, CLK_DIV_A, 0x448, 0),
|
||||
|
|
@ -143,8 +203,18 @@ static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = {
|
|||
|
||||
static const struct rzg2l_reset r9a09g011_resets[] = {
|
||||
DEF_RST(R9A09G011_PFC_PRESETN, 0x600, 2),
|
||||
DEF_RST_MON(R9A09G011_SDI0_IXRST, 0x608, 0, 6),
|
||||
DEF_RST_MON(R9A09G011_SDI1_IXRST, 0x608, 1, 7),
|
||||
DEF_RST_MON(R9A09G011_EMM_IXRST, 0x608, 2, 8),
|
||||
DEF_RST(R9A09G011_USB_PRESET_N, 0x608, 7),
|
||||
DEF_RST(R9A09G011_USB_DRD_RESET, 0x608, 8),
|
||||
DEF_RST(R9A09G011_USB_ARESETN_P, 0x608, 9),
|
||||
DEF_RST(R9A09G011_USB_ARESETN_H, 0x608, 10),
|
||||
DEF_RST_MON(R9A09G011_ETH0_RST_HW_N, 0x608, 11, 11),
|
||||
DEF_RST_MON(R9A09G011_SYC_RST_N, 0x610, 9, 13),
|
||||
DEF_RST(R9A09G011_TIM_GPB_PRESETN, 0x614, 1),
|
||||
DEF_RST(R9A09G011_TIM_GPC_PRESETN, 0x614, 2),
|
||||
DEF_RST_MON(R9A09G011_PWM_GPF_PRESETN, 0x614, 5, 23),
|
||||
DEF_RST(R9A09G011_IIC_GPA_PRESETN, 0x614, 8),
|
||||
DEF_RST(R9A09G011_IIC_GPB_PRESETN, 0x614, 9),
|
||||
DEF_RST_MON(R9A09G011_WDT0_PRESETN, 0x614, 12, 19),
|
||||
|
|
@ -152,6 +222,9 @@ static const struct rzg2l_reset r9a09g011_resets[] = {
|
|||
|
||||
static const unsigned int r9a09g011_crit_mod_clks[] __initconst = {
|
||||
MOD_CLK_BASE + R9A09G011_CA53_CLK,
|
||||
MOD_CLK_BASE + R9A09G011_CPERI_GRPB_PCLK,
|
||||
MOD_CLK_BASE + R9A09G011_CPERI_GRPC_PCLK,
|
||||
MOD_CLK_BASE + R9A09G011_CPERI_GRPF_PCLK,
|
||||
MOD_CLK_BASE + R9A09G011_GIC_CLK,
|
||||
MOD_CLK_BASE + R9A09G011_SYC_CNT_CLK,
|
||||
MOD_CLK_BASE + R9A09G011_URT_PCLK,
|
||||
|
|
|
|||
|
|
@ -310,19 +310,10 @@ static unsigned int cpg_clk_extalr __initdata;
|
|||
static u32 cpg_mode __initdata;
|
||||
static u32 cpg_quirks __initdata;
|
||||
|
||||
#define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */
|
||||
#define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */
|
||||
|
||||
|
||||
static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
|
||||
{
|
||||
.soc_id = "r8a7795", .revision = "ES1.0",
|
||||
.data = (void *)(PLL_ERRATA | RCKCR_CKSEL),
|
||||
},
|
||||
{
|
||||
.soc_id = "r8a7795", .revision = "ES1.*",
|
||||
.data = (void *)(RCKCR_CKSEL),
|
||||
},
|
||||
{
|
||||
.soc_id = "r8a7796", .revision = "ES1.0",
|
||||
.data = (void *)(RCKCR_CKSEL),
|
||||
|
|
@ -355,9 +346,8 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
|
|||
* multiplier when cpufreq changes between normal and boost
|
||||
* modes.
|
||||
*/
|
||||
mult = (cpg_quirks & PLL_ERRATA) ? 4 : 2;
|
||||
return cpg_pll_clk_register(core->name, __clk_get_name(parent),
|
||||
base, mult, CPG_PLL0CR, 0);
|
||||
base, 2, CPG_PLL0CR, 0);
|
||||
|
||||
case CLK_TYPE_GEN3_PLL1:
|
||||
mult = cpg_pll_config->pll1_mult;
|
||||
|
|
@ -370,9 +360,8 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
|
|||
* multiplier when cpufreq changes between normal and boost
|
||||
* modes.
|
||||
*/
|
||||
mult = (cpg_quirks & PLL_ERRATA) ? 4 : 2;
|
||||
return cpg_pll_clk_register(core->name, __clk_get_name(parent),
|
||||
base, mult, CPG_PLL2CR, 2);
|
||||
base, 2, CPG_PLL2CR, 2);
|
||||
|
||||
case CLK_TYPE_GEN3_PLL3:
|
||||
mult = cpg_pll_config->pll3_mult;
|
||||
|
|
@ -388,8 +377,6 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
|
|||
*/
|
||||
value = readl(base + CPG_PLL4CR);
|
||||
mult = (((value >> 24) & 0x7f) + 1) * 2;
|
||||
if (cpg_quirks & PLL_ERRATA)
|
||||
mult *= 2;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN3_SDH:
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@
|
|||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/iopoll.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
|
|
@ -27,6 +28,152 @@ static const struct rcar_gen4_cpg_pll_config *cpg_pll_config __initdata;
|
|||
static unsigned int cpg_clk_extalr __initdata;
|
||||
static u32 cpg_mode __initdata;
|
||||
|
||||
#define CPG_PLLECR 0x0820 /* PLL Enable Control Register */
|
||||
|
||||
#define CPG_PLLECR_PLLST(n) BIT(8 + ((n) < 3 ? (n) - 1 : \
|
||||
(n) > 3 ? (n) + 1 : n)) /* PLLn Circuit Status */
|
||||
|
||||
#define CPG_PLL1CR0 0x830 /* PLLn Control Registers */
|
||||
#define CPG_PLL1CR1 0x8b0
|
||||
#define CPG_PLL2CR0 0x834
|
||||
#define CPG_PLL2CR1 0x8b8
|
||||
#define CPG_PLL3CR0 0x83c
|
||||
#define CPG_PLL3CR1 0x8c0
|
||||
#define CPG_PLL4CR0 0x844
|
||||
#define CPG_PLL4CR1 0x8c8
|
||||
#define CPG_PLL6CR0 0x84c
|
||||
#define CPG_PLL6CR1 0x8d8
|
||||
|
||||
#define CPG_PLLxCR0_KICK BIT(31)
|
||||
#define CPG_PLLxCR0_NI GENMASK(27, 20) /* Integer mult. factor */
|
||||
#define CPG_PLLxCR0_SSMODE GENMASK(18, 16) /* PLL mode */
|
||||
#define CPG_PLLxCR0_SSMODE_FM BIT(18) /* Fractional Multiplication */
|
||||
#define CPG_PLLxCR0_SSMODE_DITH BIT(17) /* Frequency Dithering */
|
||||
#define CPG_PLLxCR0_SSMODE_CENT BIT(16) /* Center (vs. Down) Spread Dithering */
|
||||
#define CPG_PLLxCR0_SSFREQ GENMASK(14, 8) /* SSCG Modulation Frequency */
|
||||
#define CPG_PLLxCR0_SSDEPT GENMASK(6, 0) /* SSCG Modulation Depth */
|
||||
|
||||
#define SSMODE_FM BIT(2) /* Fractional Multiplication */
|
||||
#define SSMODE_DITHER BIT(1) /* Frequency Dithering */
|
||||
#define SSMODE_CENTER BIT(0) /* Center (vs. Down) Spread Dithering */
|
||||
|
||||
/* PLL Clocks */
|
||||
struct cpg_pll_clk {
|
||||
struct clk_hw hw;
|
||||
void __iomem *pllcr0_reg;
|
||||
void __iomem *pllecr_reg;
|
||||
u32 pllecr_pllst_mask;
|
||||
};
|
||||
|
||||
#define to_pll_clk(_hw) container_of(_hw, struct cpg_pll_clk, hw)
|
||||
|
||||
static unsigned long cpg_pll_clk_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
|
||||
unsigned int mult;
|
||||
|
||||
mult = FIELD_GET(CPG_PLLxCR0_NI, readl(pll_clk->pllcr0_reg)) + 1;
|
||||
|
||||
return parent_rate * mult * 2;
|
||||
}
|
||||
|
||||
static int cpg_pll_clk_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
unsigned int min_mult, max_mult, mult;
|
||||
unsigned long prate;
|
||||
|
||||
prate = req->best_parent_rate * 2;
|
||||
min_mult = max(div64_ul(req->min_rate, prate), 1ULL);
|
||||
max_mult = min(div64_ul(req->max_rate, prate), 256ULL);
|
||||
if (max_mult < min_mult)
|
||||
return -EINVAL;
|
||||
|
||||
mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate);
|
||||
mult = clamp(mult, min_mult, max_mult);
|
||||
|
||||
req->rate = prate * mult;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cpg_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
|
||||
unsigned int mult;
|
||||
u32 val;
|
||||
|
||||
mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * 2);
|
||||
mult = clamp(mult, 1U, 256U);
|
||||
|
||||
if (readl(pll_clk->pllcr0_reg) & CPG_PLLxCR0_KICK)
|
||||
return -EBUSY;
|
||||
|
||||
cpg_reg_modify(pll_clk->pllcr0_reg, CPG_PLLxCR0_NI,
|
||||
FIELD_PREP(CPG_PLLxCR0_NI, mult - 1));
|
||||
|
||||
/*
|
||||
* Set KICK bit in PLLxCR0 to update hardware setting and wait for
|
||||
* clock change completion.
|
||||
*/
|
||||
cpg_reg_modify(pll_clk->pllcr0_reg, 0, CPG_PLLxCR0_KICK);
|
||||
|
||||
/*
|
||||
* Note: There is no HW information about the worst case latency.
|
||||
*
|
||||
* Using experimental measurements, it seems that no more than
|
||||
* ~45 µs are needed, independently of the CPU rate.
|
||||
* Since this value might be dependent on external xtal rate, pll
|
||||
* rate or even the other emulation clocks rate, use 1000 as a
|
||||
* "super" safe value.
|
||||
*/
|
||||
return readl_poll_timeout(pll_clk->pllecr_reg, val,
|
||||
val & pll_clk->pllecr_pllst_mask, 0, 1000);
|
||||
}
|
||||
|
||||
static const struct clk_ops cpg_pll_clk_ops = {
|
||||
.recalc_rate = cpg_pll_clk_recalc_rate,
|
||||
.determine_rate = cpg_pll_clk_determine_rate,
|
||||
.set_rate = cpg_pll_clk_set_rate,
|
||||
};
|
||||
|
||||
static struct clk * __init cpg_pll_clk_register(const char *name,
|
||||
const char *parent_name,
|
||||
void __iomem *base,
|
||||
unsigned int cr0_offset,
|
||||
unsigned int cr1_offset,
|
||||
unsigned int index)
|
||||
|
||||
{
|
||||
struct cpg_pll_clk *pll_clk;
|
||||
struct clk_init_data init = {};
|
||||
struct clk *clk;
|
||||
|
||||
pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
|
||||
if (!pll_clk)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
init.name = name;
|
||||
init.ops = &cpg_pll_clk_ops;
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
|
||||
pll_clk->hw.init = &init;
|
||||
pll_clk->pllcr0_reg = base + cr0_offset;
|
||||
pll_clk->pllecr_reg = base + CPG_PLLECR;
|
||||
pll_clk->pllecr_pllst_mask = CPG_PLLECR_PLLST(index);
|
||||
|
||||
/* Disable Fractional Multiplication and Frequency Dithering */
|
||||
writel(0, base + cr1_offset);
|
||||
cpg_reg_modify(pll_clk->pllcr0_reg, CPG_PLLxCR0_SSMODE, 0);
|
||||
|
||||
clk = clk_register(NULL, &pll_clk->hw);
|
||||
if (IS_ERR(clk))
|
||||
kfree(pll_clk);
|
||||
|
||||
return clk;
|
||||
}
|
||||
/*
|
||||
* Z0 Clock & Z1 Clock
|
||||
*/
|
||||
|
|
@ -205,6 +352,15 @@ struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev,
|
|||
div = cpg_pll_config->pll1_div;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN4_PLL2_VAR:
|
||||
/*
|
||||
* PLL2 is implemented as a custom clock, to change the
|
||||
* multiplier when cpufreq changes between normal and boost
|
||||
* modes.
|
||||
*/
|
||||
return cpg_pll_clk_register(core->name, __clk_get_name(parent),
|
||||
base, CPG_PLL2CR0, CPG_PLL2CR1, 2);
|
||||
|
||||
case CLK_TYPE_GEN4_PLL2:
|
||||
mult = cpg_pll_config->pll2_mult;
|
||||
div = cpg_pll_config->pll2_div;
|
||||
|
|
|
|||
|
|
@ -13,10 +13,11 @@ enum rcar_gen4_clk_types {
|
|||
CLK_TYPE_GEN4_MAIN = CLK_TYPE_CUSTOM,
|
||||
CLK_TYPE_GEN4_PLL1,
|
||||
CLK_TYPE_GEN4_PLL2,
|
||||
CLK_TYPE_GEN4_PLL2_VAR,
|
||||
CLK_TYPE_GEN4_PLL2X_3X, /* r8a779a0 only */
|
||||
CLK_TYPE_GEN4_PLL3,
|
||||
CLK_TYPE_GEN4_PLL5,
|
||||
CLK_TYPE_GEN4_PLL4,
|
||||
CLK_TYPE_GEN4_PLL5,
|
||||
CLK_TYPE_GEN4_PLL6,
|
||||
CLK_TYPE_GEN4_SDSRC,
|
||||
CLK_TYPE_GEN4_SDH,
|
||||
|
|
|
|||
|
|
@ -943,9 +943,8 @@ static int cpg_mssr_resume_noirq(struct device *dev)
|
|||
}
|
||||
|
||||
if (!i)
|
||||
dev_warn(dev, "Failed to enable %s%u[0x%x]\n",
|
||||
priv->reg_layout == CLK_REG_LAYOUT_RZ_A ?
|
||||
"STB" : "SMSTP", reg, oldval & mask);
|
||||
dev_warn(dev, "Failed to enable SMSTP%u[0x%x]\n", reg,
|
||||
oldval & mask);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -989,7 +988,6 @@ static int __init cpg_mssr_common_init(struct device *dev,
|
|||
goto out_err;
|
||||
}
|
||||
|
||||
cpg_mssr_priv = priv;
|
||||
priv->num_core_clks = info->num_total_core_clks;
|
||||
priv->num_mod_clks = info->num_hw_mod_clks;
|
||||
priv->last_dt_core_clk = info->last_dt_core_clk;
|
||||
|
|
@ -1019,6 +1017,8 @@ static int __init cpg_mssr_common_init(struct device *dev,
|
|||
if (error)
|
||||
goto out_err;
|
||||
|
||||
cpg_mssr_priv = priv;
|
||||
|
||||
return 0;
|
||||
|
||||
out_err:
|
||||
|
|
@ -1113,19 +1113,6 @@ static int __init cpg_mssr_init(void)
|
|||
|
||||
subsys_initcall(cpg_mssr_init);
|
||||
|
||||
void __init cpg_core_nullify_range(struct cpg_core_clk *core_clks,
|
||||
unsigned int num_core_clks,
|
||||
unsigned int first_clk,
|
||||
unsigned int last_clk)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < num_core_clks; i++)
|
||||
if (core_clks[i].id >= first_clk &&
|
||||
core_clks[i].id <= last_clk)
|
||||
core_clks[i].name = NULL;
|
||||
}
|
||||
|
||||
void __init mssr_mod_nullify(struct mssr_mod_clk *mod_clks,
|
||||
unsigned int num_mod_clks,
|
||||
const unsigned int *clks, unsigned int n)
|
||||
|
|
@ -1139,19 +1126,5 @@ void __init mssr_mod_nullify(struct mssr_mod_clk *mod_clks,
|
|||
}
|
||||
}
|
||||
|
||||
void __init mssr_mod_reparent(struct mssr_mod_clk *mod_clks,
|
||||
unsigned int num_mod_clks,
|
||||
const struct mssr_mod_reparent *clks,
|
||||
unsigned int n)
|
||||
{
|
||||
unsigned int i, j;
|
||||
|
||||
for (i = 0, j = 0; i < num_mod_clks && j < n; i++)
|
||||
if (mod_clks[i].id == clks[j].clk) {
|
||||
mod_clks[i].parent = clks[j].parent;
|
||||
j++;
|
||||
}
|
||||
}
|
||||
|
||||
MODULE_DESCRIPTION("Renesas CPG/MSSR Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
|
|||
|
|
@ -187,21 +187,7 @@ void __init cpg_mssr_early_init(struct device_node *np,
|
|||
/*
|
||||
* Helpers for fixing up clock tables depending on SoC revision
|
||||
*/
|
||||
|
||||
struct mssr_mod_reparent {
|
||||
unsigned int clk, parent;
|
||||
};
|
||||
|
||||
|
||||
extern void cpg_core_nullify_range(struct cpg_core_clk *core_clks,
|
||||
unsigned int num_core_clks,
|
||||
unsigned int first_clk,
|
||||
unsigned int last_clk);
|
||||
extern void mssr_mod_nullify(struct mssr_mod_clk *mod_clks,
|
||||
unsigned int num_mod_clks,
|
||||
const unsigned int *clks, unsigned int n);
|
||||
extern void mssr_mod_reparent(struct mssr_mod_clk *mod_clks,
|
||||
unsigned int num_mod_clks,
|
||||
const struct mssr_mod_reparent *clks,
|
||||
unsigned int n);
|
||||
#endif
|
||||
|
|
|
|||
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