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mt8173: 

- split hardware encoder block into two devices.
 
 mt8167:
 - add pm domains, multi-media system (mmsys), SMI, local arbiter
   (larb) and IOMMU nodes.
 
 mt8183:
 - Add new chromebooks: HP Chromebook 11a, Acer Chromebook 311, HP
   Chromebook x360 11MK G3 EE, Lenovo IdeaPad Flex 3.
 - add power domain to SMI common node.
 - add power supplies for EEPROM node.
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Merge tag 'v5.13-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt

mt8173:
- split hardware encoder block into two devices.

mt8167:
- add pm domains, multi-media system (mmsys), SMI, local arbiter
  (larb) and IOMMU nodes.

mt8183:
- Add new chromebooks: HP Chromebook 11a, Acer Chromebook 311, HP
  Chromebook x360 11MK G3 EE, Lenovo IdeaPad Flex 3.
- add power domain to SMI common node.
- add power supplies for EEPROM node.

* tag 'v5.13-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: (21 commits)
  arm64: dts: mt8183: Add node for the Mali GPU
  arm64: dts: mt8183-kukui: Add tboard thermal zones
  arm64: dts: mt8183: add cbas node under cros_ec
  arm64: dts: mt8183: add supply name for eeprom
  arm64: dts: mt8183: remove syscon from smi_common node
  arm64: dts: mt8183: Add kukui-jacuzzi-fennel board
  arm64: dts: mt8183: Add kukui-jacuzzi-kenzo board
  arm64: dts: mt8183: Add kukui-jacuzzi-burnet board
  arm64: dts: mt8183: Add kukui-jacuzzi-willow board
  arm64: dts: mt8183: Add kukui-jacuzzi-kappa board
  dt-bindings: arm64: dts: mediatek: Add mt8183-kukui-jacuzzi-fennel
  dt-bindings: arm64: dts: mediatek: Add mt8183-kukui-jacuzzi-kenzo
  dt-bindings: arm64: dts: mediatek: Add mt8183-kukui-jacuzzi-burnet
  dt-bindings: arm64: dts: mediatek: Add mt8183-kukui-jacuzzi-willow
  dt-bindings: arm64: dts: mediatek: Add mt8183-kukui-jacuzzi-kappa
  arm64: dts: mediatek: mt8167: add iommu node
  arm64: dts: mediatek: mt8167: add larb nodes
  arm64: dts: mediatek: mt8167: add smi_common node
  arm64: dts: mediatek: mt8167: add mmsys node
  arm64: dts: mediatek: mt8167: add power domains
  ...

Link: https://lore.kernel.org/r/117d5eb5-bc99-70bb-a1a9-d7141fe96527@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2021-06-12 08:47:54 -07:00
Родитель a3c52f08ab a8168cebf1
Коммит 796f0ae8e7
22 изменённых файлов: 576 добавлений и 33 удалений
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29
Documentation/devicetree/bindings/arm/mediatek.yaml
Просмотреть файл

@ -122,6 +122,10 @@ properties:
- enum:
- mediatek,mt8195-evb
- const: mediatek,mt8195
- description: Google Burnet (HP Chromebook x360 11MK G3 EE)
items:
- const: google,burnet
- const: mediatek,mt8183
- description: Google Krane (Lenovo IdeaPad Duet, 10e,...)
items:
- enum:
@ -133,9 +137,19 @@ properties:
items:
- const: google,damu
- const: mediatek,mt8183
- description: Google Juniper (Acer Chromebook Spin 311)
- description: Google Fennel (Lenovo IdeaPad 3 Chromebook)
items:
- const: google,juniper-sku16
- enum:
- google,fennel-sku0
- google,fennel-sku1
- google,fennel-sku6
- const: google,fennel
- const: mediatek,mt8183
- description: Google Juniper (Acer Chromebook Spin 311) / Kenzo (Acer Chromebook 311)
items:
- enum:
- google,juniper-sku16
- google,juniper-sku17
- const: google,juniper
- const: mediatek,mt8183
- description: Google Kakadu (ASUS Chromebook Detachable CM3)
@ -144,6 +158,10 @@ properties:
- const: google,kakadu-rev2
- const: google,kakadu
- const: mediatek,mt8183
- description: Google Kappa (HP Chromebook 11a)
items:
- const: google,kappa
- const: mediatek,mt8183
- description: Google Kodama (Lenovo 10e Chromebook Tablet)
items:
- enum:
@ -153,6 +171,13 @@ properties:
- google,kodama-sku32
- const: google,kodama
- const: mediatek,mt8183
- description: Google Willow (Acer Chromebook 311 C722/C722T)
items:
- enum:
- google,willow-sku0
- google,willow-sku1
- const: google,willow
- const: mediatek,mt8183
- items:
- enum:
- mediatek,mt8183-pumpkin

8
arch/arm64/boot/dts/mediatek/Makefile
Просмотреть файл

@ -13,8 +13,16 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-burnet.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-damu.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel-sku6.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-fennel14.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-juniper-sku16.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kappa.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-kenzo.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-jacuzzi-willow-sku1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kakadu.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku16.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku272.dtb

121
arch/arm64/boot/dts/mediatek/mt8167.dtsi
Просмотреть файл

@ -7,6 +7,7 @@
#include <dt-bindings/clock/mt8167-clk.h>
#include <dt-bindings/memory/mt8167-larb-port.h>
#include <dt-bindings/power/mt8167-power.h>
#include "mt8167-pinfunc.h"
@ -34,6 +35,73 @@
#clock-cells = <1>;
};
scpsys: syscon@10006000 {
compatible = "syscon", "simple-mfd";
reg = <0 0x10006000 0 0x1000>;
#power-domain-cells = <1>;
spm: power-controller {
compatible = "mediatek,mt8167-power-controller";
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
/* power domains of the SoC */
power-domain@MT8167_POWER_DOMAIN_MM {
reg = <MT8167_POWER_DOMAIN_MM>;
clocks = <&topckgen CLK_TOP_SMI_MM>;
clock-names = "mm";
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
};
power-domain@MT8167_POWER_DOMAIN_VDEC {
reg = <MT8167_POWER_DOMAIN_VDEC>;
clocks = <&topckgen CLK_TOP_SMI_MM>,
<&topckgen CLK_TOP_RG_VDEC>;
clock-names = "mm", "vdec";
#power-domain-cells = <0>;
};
power-domain@MT8167_POWER_DOMAIN_ISP {
reg = <MT8167_POWER_DOMAIN_ISP>;
clocks = <&topckgen CLK_TOP_SMI_MM>;
clock-names = "mm";
#power-domain-cells = <0>;
};
power-domain@MT8167_POWER_DOMAIN_MFG_ASYNC {
reg = <MT8167_POWER_DOMAIN_MFG_ASYNC>;
clocks = <&topckgen CLK_TOP_RG_AXI_MFG>,
<&topckgen CLK_TOP_RG_SLOW_MFG>;
clock-names = "axi_mfg", "mfg";
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
mediatek,infracfg = <&infracfg>;
power-domain@MT8167_POWER_DOMAIN_MFG_2D {
reg = <MT8167_POWER_DOMAIN_MFG_2D>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
power-domain@MT8167_POWER_DOMAIN_MFG {
reg = <MT8167_POWER_DOMAIN_MFG>;
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
};
};
};
power-domain@MT8167_POWER_DOMAIN_CONN {
reg = <MT8167_POWER_DOMAIN_CONN>;
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
};
};
};
imgsys: syscon@15000000 {
compatible = "mediatek,mt8167-imgsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
@ -57,5 +125,58 @@
#interrupt-cells = <2>;
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
};
mmsys: mmsys@14000000 {
compatible = "mediatek,mt8167-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
};
smi_common: smi@14017000 {
compatible = "mediatek,mt8167-smi-common";
reg = <0 0x14017000 0 0x1000>;
clocks = <&mmsys CLK_MM_SMI_COMMON>,
<&mmsys CLK_MM_SMI_COMMON>;
clock-names = "apb", "smi";
power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
};
larb0: larb@14016000 {
compatible = "mediatek,mt8167-smi-larb";
reg = <0 0x14016000 0 0x1000>;
mediatek,smi = <&smi_common>;
clocks = <&mmsys CLK_MM_SMI_LARB0>,
<&mmsys CLK_MM_SMI_LARB0>;
clock-names = "apb", "smi";
power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
};
larb1: larb@15001000 {
compatible = "mediatek,mt8167-smi-larb";
reg = <0 0x15001000 0 0x1000>;
mediatek,smi = <&smi_common>;
clocks = <&imgsys CLK_IMG_LARB1_SMI>,
<&imgsys CLK_IMG_LARB1_SMI>;
clock-names = "apb", "smi";
power-domains = <&spm MT8167_POWER_DOMAIN_ISP>;
};
larb2: larb@16010000 {
compatible = "mediatek,mt8167-smi-larb";
reg = <0 0x16010000 0 0x1000>;
mediatek,smi = <&smi_common>;
clocks = <&vdecsys CLK_VDEC_CKEN>,
<&vdecsys CLK_VDEC_LARB1_CKEN>;
clock-names = "apb", "smi";
power-domains = <&spm MT8167_POWER_DOMAIN_VDEC>;
};
iommu: m4u@10203000 {
compatible = "mediatek,mt8167-m4u";
reg = <0 0x10203000 0 0x1000>;
mediatek,larbs = <&larb0 &larb1 &larb2>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>;
#iommu-cells = <1>;
};
};
};

60
arch/arm64/boot/dts/mediatek/mt8173.dtsi
Просмотреть файл

@ -1459,14 +1459,11 @@
clock-names = "apb", "smi";
};
vcodec_enc: vcodec@18002000 {
vcodec_enc_avc: vcodec@18002000 {
compatible = "mediatek,mt8173-vcodec-enc";
reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */
<0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
mediatek,larb = <&larb3>,
<&larb5>;
reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
mediatek,larb = <&larb3>;
iommus = <&iommu M4U_PORT_VENC_RCPU>,
<&iommu M4U_PORT_VENC_REC>,
<&iommu M4U_PORT_VENC_BSDMA>,
@ -1477,29 +1474,12 @@
<&iommu M4U_PORT_VENC_REF_LUMA>,
<&iommu M4U_PORT_VENC_REF_CHROMA>,
<&iommu M4U_PORT_VENC_NBM_RDMA>,
<&iommu M4U_PORT_VENC_NBM_WDMA>,
<&iommu M4U_PORT_VENC_RCPU_SET2>,
<&iommu M4U_PORT_VENC_REC_FRM_SET2>,
<&iommu M4U_PORT_VENC_BSDMA_SET2>,
<&iommu M4U_PORT_VENC_SV_COMA_SET2>,
<&iommu M4U_PORT_VENC_RD_COMA_SET2>,
<&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
<&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
<&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
<&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
<&iommu M4U_PORT_VENC_NBM_WDMA>;
mediatek,vpu = <&vpu>;
clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
<&topckgen CLK_TOP_VENC_SEL>,
<&topckgen CLK_TOP_UNIVPLL1_D2>,
<&topckgen CLK_TOP_VENC_LT_SEL>;
clock-names = "venc_sel_src",
"venc_sel",
"venc_lt_sel_src",
"venc_lt_sel";
assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
<&topckgen CLK_TOP_VENC_LT_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>,
<&topckgen CLK_TOP_VCODECPLL_370P5>;
clocks = <&topckgen CLK_TOP_VENC_SEL>;
clock-names = "venc_sel";
assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
};
jpegdec: jpegdec@18004000 {
@ -1531,5 +1511,27 @@
<&vencltsys CLK_VENCLT_CKE0>;
clock-names = "apb", "smi";
};
vcodec_enc_vp8: vcodec@19002000 {
compatible = "mediatek,mt8173-vcodec-enc-vp8";
reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
<&iommu M4U_PORT_VENC_REC_FRM_SET2>,
<&iommu M4U_PORT_VENC_BSDMA_SET2>,
<&iommu M4U_PORT_VENC_SV_COMA_SET2>,
<&iommu M4U_PORT_VENC_RD_COMA_SET2>,
<&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
<&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
<&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
<&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
mediatek,larb = <&larb5>;
mediatek,vpu = <&vpu>;
clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
clock-names = "venc_lt_sel";
assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
assigned-clock-parents =
<&topckgen CLK_TOP_VCODECPLL_370P5>;
};
};
};

5
arch/arm64/boot/dts/mediatek/mt8183-evb.dts
Просмотреть файл

@ -42,6 +42,11 @@
status = "okay";
};
&gpu {
mali-supply = <&mt6358_vgpu_reg>;
sram-supply = <&mt6358_vsram_gpu_reg>;
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c_pins_0>;

30
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts Normal file
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@ -0,0 +1,30 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2021 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi.dtsi"
/ {
model = "Google burnet board";
compatible = "google,burnet", "mediatek,mt8183";
};
&mt6358codec {
mediatek,dmic-mode = <1>; /* one-wire */
};
&i2c0 {
touchscreen@2c {
compatible = "hid-over-i2c";
reg = <0x2c>;
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
post-power-on-delay-ms = <200>;
hid-descr-addr = <0x0020>;
};
};

44
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts Normal file
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@ -0,0 +1,44 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2021 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi-fennel.dtsi"
/ {
model = "Google fennel sku1 board";
compatible = "google,fennel-sku1", "google,fennel", "mediatek,mt8183";
pwmleds {
compatible = "pwm-leds";
keyboard_backlight: keyboard-backlight {
label = "cros_ec::kbd_backlight";
pwms = <&cros_ec_pwm 0>;
max-brightness = <1023>;
};
};
};
&cros_ec_pwm {
status = "okay";
};
&touchscreen {
status = "okay";
compatible = "hid-over-i2c";
reg = <0x10>;
interrupt-parent = <&pio>;
interrupts = <155 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
post-power-on-delay-ms = <10>;
hid-descr-addr = <0x0001>;
};
&qca_wifi {
qcom,ath10k-calibration-variant = "GO_FENNEL";
};

32
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts Normal file
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@ -0,0 +1,32 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2021 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi-fennel.dtsi"
/ {
model = "Google fennel sku6 board";
compatible = "google,fennel-sku6", "google,fennel", "mediatek,mt8183";
};
&touchscreen {
status = "okay";
compatible = "hid-over-i2c";
reg = <0x10>;
interrupt-parent = <&pio>;
interrupts = <155 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
post-power-on-delay-ms = <10>;
hid-descr-addr = <0x0001>;
};
&qca_wifi {
qcom,ath10k-calibration-variant = "GO_FENNEL";
};

27
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi Normal file
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@ -0,0 +1,27 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2021 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi.dtsi"
&mt6358codec {
mediatek,dmic-mode = <1>; /* one-wire */
};
&i2c2 {
trackpad@2c {
compatible = "hid-over-i2c";
reg = <0x2c>;
hid-descr-addr = <0x20>;
pinctrl-names = "default";
pinctrl-0 = <&trackpad_pins>;
interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>;
wakeup-source;
};
};

16
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts Normal file
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@ -0,0 +1,16 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2021 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi-fennel.dtsi"
/ {
model = "Google fennel14 sku0 board";
compatible = "google,fennel-sku0", "google,fennel", "mediatek,mt8183";
};
&qca_wifi {
qcom,ath10k-calibration-variant = "GO_FENNEL14";
};

16
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts Normal file
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@ -0,0 +1,16 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2021 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi.dtsi"
/ {
model = "Google kappa board";
compatible = "google,kappa", "mediatek,mt8183";
};
&mt6358codec {
mediatek,dmic-mode = <1>; /* one-wire */
};

12
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts Normal file
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@ -0,0 +1,12 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2021 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi-juniper.dtsi"
/ {
model = "Google kenzo sku17 board";
compatible = "google,juniper-sku17", "google,juniper", "mediatek,mt8183";
};

13
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts Normal file
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@ -0,0 +1,13 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2021 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi-willow.dtsi"
/ {
model = "Google willow board sku0";
compatible = "google,willow-sku0", "google,willow", "mediatek,mt8183";
};

12
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts Normal file
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@ -0,0 +1,12 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2021 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi-willow.dtsi"
/ {
model = "Google willow board sku1";
compatible = "google,willow-sku1", "google,willow", "mediatek,mt8183";
};

26
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi Normal file
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@ -0,0 +1,26 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2021 Google LLC
*/
/dts-v1/;
#include "mt8183-kukui-jacuzzi.dtsi"
&i2c2 {
trackpad@2c {
compatible = "hid-over-i2c";
reg = <0x2c>;
hid-descr-addr = <0x20>;
pinctrl-names = "default";
pinctrl-0 = <&trackpad_pins>;
interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>;
wakeup-source;
};
};
&qca_wifi {
qcom,ath10k-calibration-variant = "GO_JUNIPER";
};

8
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi
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@ -92,6 +92,14 @@
};
};
&cros_ec {
cros_ec_pwm: ec-pwm {
compatible = "google,cros-ec-pwm";
#pwm-cells = <1>;
status = "disabled";
};
};
&dsi0 {
status = "okay";
/delete-node/panel@0;

4
arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi
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@ -88,11 +88,13 @@
pinctrl-0 = <&i2c2_pins>;
status = "okay";
clock-frequency = <400000>;
vbus-supply = <&mt6358_vcamio_reg>;
eeprom@58 {
compatible = "atmel,24c32";
reg = <0x58>;
pagesize = <32>;
vcc-supply = <&mt6358_vcama2_reg>;
};
};
@ -101,11 +103,13 @@
pinctrl-0 = <&i2c4_pins>;
status = "okay";
clock-frequency = <400000>;
vbus-supply = <&mt6358_vcn18_reg>;
eeprom@54 {
compatible = "atmel,24c32";
reg = <0x54>;
pagesize = <32>;
vcc-supply = <&mt6358_vcn18_reg>;
};
};

4
arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi
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@ -62,11 +62,13 @@
pinctrl-0 = <&i2c2_pins>;
status = "okay";
clock-frequency = <400000>;
vbus-supply = <&mt6358_vcamio_reg>;
eeprom@58 {
compatible = "atmel,24c64";
reg = <0x58>;
pagesize = <32>;
vcc-supply = <&mt6358_vcamio_reg>;
};
};
@ -75,11 +77,13 @@
pinctrl-0 = <&i2c4_pins>;
status = "okay";
clock-frequency = <400000>;
vbus-supply = <&mt6358_vcn18_reg>;
eeprom@54 {
compatible = "atmel,24c64";
reg = <0x54>;
pagesize = <32>;
vcc-supply = <&mt6358_vcn18_reg>;
};
};

4
arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi
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@ -71,11 +71,13 @@
pinctrl-0 = <&i2c2_pins>;
status = "okay";
clock-frequency = <400000>;
vbus-supply = <&mt6358_vcamio_reg>;
eeprom@58 {
compatible = "atmel,24c32";
reg = <0x58>;
pagesize = <32>;
vcc-supply = <&mt6358_vcama2_reg>;
};
};
@ -84,11 +86,13 @@
pinctrl-0 = <&i2c4_pins>;
status = "okay";
clock-frequency = <400000>;
vbus-supply = <&mt6358_vcn18_reg>;
eeprom@54 {
compatible = "atmel,24c32";
reg = <0x54>;
pagesize = <32>;
vcc-supply = <&mt6358_vcn18_reg>;
};
};

23
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
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@ -279,6 +279,11 @@
};
};
&gpu {
mali-supply = <&mt6358_vgpu_reg>;
sram-supply = <&mt6358_vsram_gpu_reg>;
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
@ -816,6 +821,10 @@
compatible = "google,extcon-usbc-cros-ec";
google,usb-port-id = <0>;
};
cbas {
compatible = "google,cros-cbas";
};
};
};
@ -847,6 +856,20 @@
status = "okay";
};
&thermal_zones {
tboard1 {
polling-delay = <1000>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&tboard_thermistor1>;
};
tboard2 {
polling-delay = <1000>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&tboard_thermistor2>;
};
};
&u3phy {
status = "okay";
};

5
arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
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@ -68,6 +68,11 @@
status = "okay";
};
&gpu {
mali-supply = <&mt6358_vgpu_reg>;
sram-supply = <&mt6358_vsram_gpu_reg>;
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c_pins_0>;

110
arch/arm64/boot/dts/mediatek/mt8183.dtsi
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@ -197,6 +197,91 @@
};
};
gpu_opp_table: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <625000>, <850000>;
};
opp-320000000 {
opp-hz = /bits/ 64 <320000000>;
opp-microvolt = <631250>, <850000>;
};
opp-340000000 {
opp-hz = /bits/ 64 <340000000>;
opp-microvolt = <637500>, <850000>;
};
opp-360000000 {
opp-hz = /bits/ 64 <360000000>;
opp-microvolt = <643750>, <850000>;
};
opp-380000000 {
opp-hz = /bits/ 64 <380000000>;
opp-microvolt = <650000>, <850000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <656250>, <850000>;
};
opp-420000000 {
opp-hz = /bits/ 64 <420000000>;
opp-microvolt = <662500>, <850000>;
};
opp-460000000 {
opp-hz = /bits/ 64 <460000000>;
opp-microvolt = <675000>, <850000>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <687500>, <850000>;
};
opp-540000000 {
opp-hz = /bits/ 64 <540000000>;
opp-microvolt = <700000>, <850000>;
};
opp-580000000 {
opp-hz = /bits/ 64 <580000000>;
opp-microvolt = <712500>, <850000>;
};
opp-620000000 {
opp-hz = /bits/ 64 <620000000>;
opp-microvolt = <725000>, <850000>;
};
opp-653000000 {
opp-hz = /bits/ 64 <653000000>;
opp-microvolt = <743750>, <850000>;
};
opp-698000000 {
opp-hz = /bits/ 64 <698000000>;
opp-microvolt = <768750>, <868750>;
};
opp-743000000 {
opp-hz = /bits/ 64 <743000000>;
opp-microvolt = <793750>, <893750>;
};
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <825000>, <925000>;
};
};
pmu-a53 {
compatible = "arm,cortex-a53-pmu";
interrupt-parent = <&gic>;
@ -673,7 +758,7 @@
nvmem-cell-names = "calibration-data";
};
thermal-zones {
thermal_zones: thermal-zones {
cpu_thermal: cpu_thermal {
polling-delay-passive = <100>;
polling-delay = <500>;
@ -1118,6 +1203,26 @@
#clock-cells = <1>;
};
gpu: gpu@13040000 {
compatible = "mediatek,mt8183-mali", "arm,mali-bifrost";
reg = <0 0x13040000 0 0x4000>;
interrupts =
<GIC_SPI 280 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 279 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "job", "mmu", "gpu";
clocks = <&topckgen CLK_TOP_MFGPLL_CK>;
power-domains =
<&spm MT8183_POWER_DOMAIN_MFG_CORE0>,
<&spm MT8183_POWER_DOMAIN_MFG_CORE1>,
<&spm MT8183_POWER_DOMAIN_MFG_2D>;
power-domain-names = "core0", "core1", "core2";
operating-points-v2 = <&gpu_opp_table>;
};
mmsys: syscon@14000000 {
compatible = "mediatek,mt8183-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
@ -1263,13 +1368,14 @@
};
smi_common: smi@14019000 {
compatible = "mediatek,mt8183-smi-common", "syscon";
compatible = "mediatek,mt8183-smi-common";
reg = <0 0x14019000 0 0x1000>;
clocks = <&mmsys CLK_MM_SMI_COMMON>,
<&mmsys CLK_MM_SMI_COMMON>,
<&mmsys CLK_MM_GALS_COMM0>,
<&mmsys CLK_MM_GALS_COMM1>;
clock-names = "apb", "smi", "gals0", "gals1";
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
};
imgsys: syscon@15020000 {