drm/radeon: use hw cts/n values for deep color
I'm not really sure how these should be calculated for deep color. The hw generated values seem to work. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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7d5ab3009a
Коммит
79766915d9
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@ -293,10 +293,12 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
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u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
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struct hdmi_avi_infoframe frame;
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uint32_t offset;
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ssize_t err;
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int bpc = 8;
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if (!dig || !dig->afmt)
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return;
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@ -306,6 +308,12 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
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return;
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offset = dig->afmt->offset;
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/* hdmi deep color mode general control packets setup, if bpc > 8 */
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if (encoder->crtc) {
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
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bpc = radeon_crtc->bpc;
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}
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/* disable audio prior to setting up hw */
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if (ASIC_IS_DCE6(rdev)) {
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dig->afmt->pin = dce6_audio_get_pin(rdev);
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@ -348,9 +356,13 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
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/* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
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WREG32(HDMI_ACR_PACKET_CONTROL + offset,
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HDMI_ACR_SOURCE | /* select SW CTS value */
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HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
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if (bpc > 8)
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WREG32(HDMI_ACR_PACKET_CONTROL + offset,
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HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
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else
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WREG32(HDMI_ACR_PACKET_CONTROL + offset,
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HDMI_ACR_SOURCE | /* select SW CTS value */
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HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
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evergreen_hdmi_update_ACR(encoder, mode->clock);
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