media: i2c: imx290: Define more register macros
Define macros for all registers programmed by the driver for which documentation is available to increase readability. This starts making use of 16-bit registers in the register arrays, so the value field has to be increased to 32 bits. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
This commit is contained in:
Laurent Pinchart
Sakari Ailus
Родитель
e611f3dac5
Коммит
79d99ae8a7
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@ -31,14 +31,73 @@
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#define IMX290_STANDBY IMX290_REG_8BIT(0x3000)
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#define IMX290_REGHOLD IMX290_REG_8BIT(0x3001)
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#define IMX290_XMSTA IMX290_REG_8BIT(0x3002)
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#define IMX290_ADBIT IMX290_REG_8BIT(0x3005)
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#define IMX290_ADBIT_10BIT (0 << 0)
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#define IMX290_ADBIT_12BIT (1 << 0)
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#define IMX290_CTRL_07 IMX290_REG_8BIT(0x3007)
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#define IMX290_VREVERSE BIT(0)
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#define IMX290_HREVERSE BIT(1)
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#define IMX290_WINMODE_1080P (0 << 4)
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#define IMX290_WINMODE_720P (1 << 4)
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#define IMX290_WINMODE_CROP (4 << 4)
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#define IMX290_FR_FDG_SEL IMX290_REG_8BIT(0x3009)
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#define IMX290_BLKLEVEL IMX290_REG_16BIT(0x300a)
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#define IMX290_GAIN IMX290_REG_8BIT(0x3014)
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#define IMX290_VMAX IMX290_REG_24BIT(0x3018)
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#define IMX290_HMAX IMX290_REG_16BIT(0x301c)
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#define IMX290_SHS1 IMX290_REG_24BIT(0x3020)
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#define IMX290_WINWV_OB IMX290_REG_8BIT(0x303a)
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#define IMX290_WINPV IMX290_REG_16BIT(0x303c)
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#define IMX290_WINWV IMX290_REG_16BIT(0x303e)
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#define IMX290_WINPH IMX290_REG_16BIT(0x3040)
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#define IMX290_WINWH IMX290_REG_16BIT(0x3042)
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#define IMX290_OUT_CTRL IMX290_REG_8BIT(0x3046)
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#define IMX290_ODBIT_10BIT (0 << 0)
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#define IMX290_ODBIT_12BIT (1 << 0)
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#define IMX290_OPORTSEL_PARALLEL (0x0 << 4)
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#define IMX290_OPORTSEL_LVDS_2CH (0xd << 4)
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#define IMX290_OPORTSEL_LVDS_4CH (0xe << 4)
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#define IMX290_OPORTSEL_LVDS_8CH (0xf << 4)
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#define IMX290_XSOUTSEL IMX290_REG_8BIT(0x304b)
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#define IMX290_XSOUTSEL_XVSOUTSEL_HIGH (0 << 0)
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#define IMX290_XSOUTSEL_XVSOUTSEL_VSYNC (2 << 0)
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#define IMX290_XSOUTSEL_XHSOUTSEL_HIGH (0 << 2)
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#define IMX290_XSOUTSEL_XHSOUTSEL_HSYNC (2 << 2)
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#define IMX290_INCKSEL1 IMX290_REG_8BIT(0x305c)
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#define IMX290_INCKSEL2 IMX290_REG_8BIT(0x305d)
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#define IMX290_INCKSEL3 IMX290_REG_8BIT(0x305e)
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#define IMX290_INCKSEL4 IMX290_REG_8BIT(0x305f)
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#define IMX290_PGCTRL IMX290_REG_8BIT(0x308c)
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#define IMX290_ADBIT1 IMX290_REG_8BIT(0x3129)
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#define IMX290_ADBIT1_10BIT 0x1d
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#define IMX290_ADBIT1_12BIT 0x00
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#define IMX290_INCKSEL5 IMX290_REG_8BIT(0x315e)
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#define IMX290_INCKSEL6 IMX290_REG_8BIT(0x3164)
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#define IMX290_ADBIT2 IMX290_REG_8BIT(0x317c)
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#define IMX290_ADBIT2_10BIT 0x12
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#define IMX290_ADBIT2_12BIT 0x00
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#define IMX290_CHIP_ID IMX290_REG_16BIT(0x319a)
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#define IMX290_ADBIT3 IMX290_REG_8BIT(0x31ec)
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#define IMX290_ADBIT3_10BIT 0x37
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#define IMX290_ADBIT3_12BIT 0x0e
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#define IMX290_REPETITION IMX290_REG_8BIT(0x3405)
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#define IMX290_PHY_LANE_NUM IMX290_REG_8BIT(0x3407)
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#define IMX290_OPB_SIZE_V IMX290_REG_8BIT(0x3414)
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#define IMX290_Y_OUT_SIZE IMX290_REG_16BIT(0x3418)
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#define IMX290_CSI_DT_FMT IMX290_REG_16BIT(0x3441)
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#define IMX290_CSI_DT_FMT_RAW10 0x0a0a
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#define IMX290_CSI_DT_FMT_RAW12 0x0c0c
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#define IMX290_CSI_LANE_MODE IMX290_REG_8BIT(0x3443)
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#define IMX290_EXTCK_FREQ IMX290_REG_16BIT(0x3444)
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#define IMX290_TCLKPOST IMX290_REG_16BIT(0x3446)
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#define IMX290_THSZERO IMX290_REG_16BIT(0x3448)
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#define IMX290_THSPREPARE IMX290_REG_16BIT(0x344a)
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#define IMX290_TCLKTRAIL IMX290_REG_16BIT(0x344c)
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#define IMX290_THSTRAIL IMX290_REG_16BIT(0x344e)
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#define IMX290_TCLKZERO IMX290_REG_16BIT(0x3450)
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#define IMX290_TCLKPREPARE IMX290_REG_16BIT(0x3452)
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#define IMX290_TLPX IMX290_REG_16BIT(0x3454)
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#define IMX290_X_OUT_SIZE IMX290_REG_16BIT(0x3472)
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#define IMX290_PGCTRL_REGEN BIT(0)
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#define IMX290_PGCTRL_THRU BIT(1)
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@ -54,7 +113,7 @@ static const char * const imx290_supply_name[] = {
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struct imx290_regval {
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u32 reg;
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u8 val;
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u32 val;
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};
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struct imx290_mode {
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@ -116,22 +175,16 @@ static const char * const imx290_test_pattern_menu[] = {
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};
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static const struct imx290_regval imx290_global_init_settings[] = {
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{ IMX290_REG_8BIT(0x3007), 0x00 },
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{ IMX290_REG_8BIT(0x3018), 0x65 },
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{ IMX290_REG_8BIT(0x3019), 0x04 },
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{ IMX290_REG_8BIT(0x301a), 0x00 },
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{ IMX290_REG_8BIT(0x3444), 0x20 },
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{ IMX290_REG_8BIT(0x3445), 0x25 },
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{ IMX290_REG_8BIT(0x303a), 0x0c },
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{ IMX290_REG_8BIT(0x3040), 0x00 },
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{ IMX290_REG_8BIT(0x3041), 0x00 },
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{ IMX290_REG_8BIT(0x303c), 0x00 },
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{ IMX290_REG_8BIT(0x303d), 0x00 },
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{ IMX290_REG_8BIT(0x3042), 0x9c },
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{ IMX290_REG_8BIT(0x3043), 0x07 },
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{ IMX290_REG_8BIT(0x303e), 0x49 },
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{ IMX290_REG_8BIT(0x303f), 0x04 },
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{ IMX290_REG_8BIT(0x304b), 0x0a },
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{ IMX290_CTRL_07, IMX290_WINMODE_1080P },
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{ IMX290_VMAX, 1125 },
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{ IMX290_EXTCK_FREQ, 0x2520 },
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{ IMX290_WINWV_OB, 12 },
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{ IMX290_WINPH, 0 },
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{ IMX290_WINPV, 0 },
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{ IMX290_WINWH, 1948 },
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{ IMX290_WINWV, 1097 },
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{ IMX290_XSOUTSEL, IMX290_XSOUTSEL_XVSOUTSEL_VSYNC |
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IMX290_XSOUTSEL_XHSOUTSEL_HSYNC },
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{ IMX290_REG_8BIT(0x300f), 0x00 },
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{ IMX290_REG_8BIT(0x3010), 0x21 },
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{ IMX290_REG_8BIT(0x3012), 0x64 },
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@ -177,102 +230,78 @@ static const struct imx290_regval imx290_global_init_settings[] = {
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static const struct imx290_regval imx290_1080p_settings[] = {
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/* mode settings */
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{ IMX290_REG_8BIT(0x3007), 0x00 },
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{ IMX290_REG_8BIT(0x303a), 0x0c },
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{ IMX290_REG_8BIT(0x3414), 0x0a },
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{ IMX290_REG_8BIT(0x3472), 0x80 },
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{ IMX290_REG_8BIT(0x3473), 0x07 },
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{ IMX290_REG_8BIT(0x3418), 0x38 },
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{ IMX290_REG_8BIT(0x3419), 0x04 },
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{ IMX290_CTRL_07, IMX290_WINMODE_1080P },
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{ IMX290_WINWV_OB, 12 },
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{ IMX290_OPB_SIZE_V, 10 },
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{ IMX290_X_OUT_SIZE, 1920 },
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{ IMX290_Y_OUT_SIZE, 1080 },
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{ IMX290_REG_8BIT(0x3012), 0x64 },
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{ IMX290_REG_8BIT(0x3013), 0x00 },
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{ IMX290_REG_8BIT(0x305c), 0x18 },
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{ IMX290_REG_8BIT(0x305d), 0x03 },
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{ IMX290_REG_8BIT(0x305e), 0x20 },
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{ IMX290_REG_8BIT(0x305f), 0x01 },
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{ IMX290_REG_8BIT(0x315e), 0x1a },
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{ IMX290_REG_8BIT(0x3164), 0x1a },
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{ IMX290_INCKSEL1, 0x18 },
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{ IMX290_INCKSEL2, 0x03 },
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{ IMX290_INCKSEL3, 0x20 },
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{ IMX290_INCKSEL4, 0x01 },
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{ IMX290_INCKSEL5, 0x1a },
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{ IMX290_INCKSEL6, 0x1a },
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{ IMX290_REG_8BIT(0x3480), 0x49 },
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/* data rate settings */
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{ IMX290_REG_8BIT(0x3405), 0x10 },
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{ IMX290_REG_8BIT(0x3446), 0x57 },
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{ IMX290_REG_8BIT(0x3447), 0x00 },
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{ IMX290_REG_8BIT(0x3448), 0x37 },
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{ IMX290_REG_8BIT(0x3449), 0x00 },
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{ IMX290_REG_8BIT(0x344a), 0x1f },
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{ IMX290_REG_8BIT(0x344b), 0x00 },
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{ IMX290_REG_8BIT(0x344c), 0x1f },
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{ IMX290_REG_8BIT(0x344d), 0x00 },
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{ IMX290_REG_8BIT(0x344e), 0x1f },
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{ IMX290_REG_8BIT(0x344f), 0x00 },
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{ IMX290_REG_8BIT(0x3450), 0x77 },
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{ IMX290_REG_8BIT(0x3451), 0x00 },
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{ IMX290_REG_8BIT(0x3452), 0x1f },
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{ IMX290_REG_8BIT(0x3453), 0x00 },
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{ IMX290_REG_8BIT(0x3454), 0x17 },
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{ IMX290_REG_8BIT(0x3455), 0x00 },
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{ IMX290_REPETITION, 0x10 },
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{ IMX290_TCLKPOST, 87 },
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{ IMX290_THSZERO, 55 },
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{ IMX290_THSPREPARE, 31 },
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{ IMX290_TCLKTRAIL, 31 },
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{ IMX290_THSTRAIL, 31 },
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{ IMX290_TCLKZERO, 119 },
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{ IMX290_TCLKPREPARE, 31 },
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{ IMX290_TLPX, 23 },
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};
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static const struct imx290_regval imx290_720p_settings[] = {
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/* mode settings */
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{ IMX290_REG_8BIT(0x3007), 0x10 },
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{ IMX290_REG_8BIT(0x303a), 0x06 },
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{ IMX290_REG_8BIT(0x3414), 0x04 },
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{ IMX290_REG_8BIT(0x3472), 0x00 },
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{ IMX290_REG_8BIT(0x3473), 0x05 },
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{ IMX290_REG_8BIT(0x3418), 0xd0 },
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{ IMX290_REG_8BIT(0x3419), 0x02 },
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{ IMX290_CTRL_07, IMX290_WINMODE_720P },
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{ IMX290_WINWV_OB, 6 },
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{ IMX290_OPB_SIZE_V, 4 },
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{ IMX290_X_OUT_SIZE, 1280 },
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{ IMX290_Y_OUT_SIZE, 720 },
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{ IMX290_REG_8BIT(0x3012), 0x64 },
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{ IMX290_REG_8BIT(0x3013), 0x00 },
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{ IMX290_REG_8BIT(0x305c), 0x20 },
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{ IMX290_REG_8BIT(0x305d), 0x00 },
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{ IMX290_REG_8BIT(0x305e), 0x20 },
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{ IMX290_REG_8BIT(0x305f), 0x01 },
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{ IMX290_REG_8BIT(0x315e), 0x1a },
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{ IMX290_REG_8BIT(0x3164), 0x1a },
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{ IMX290_INCKSEL1, 0x20 },
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{ IMX290_INCKSEL2, 0x00 },
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{ IMX290_INCKSEL3, 0x20 },
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{ IMX290_INCKSEL4, 0x01 },
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{ IMX290_INCKSEL5, 0x1a },
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{ IMX290_INCKSEL6, 0x1a },
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{ IMX290_REG_8BIT(0x3480), 0x49 },
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/* data rate settings */
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{ IMX290_REG_8BIT(0x3405), 0x10 },
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{ IMX290_REG_8BIT(0x3446), 0x4f },
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{ IMX290_REG_8BIT(0x3447), 0x00 },
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{ IMX290_REG_8BIT(0x3448), 0x2f },
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{ IMX290_REG_8BIT(0x3449), 0x00 },
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{ IMX290_REG_8BIT(0x344a), 0x17 },
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{ IMX290_REG_8BIT(0x344b), 0x00 },
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{ IMX290_REG_8BIT(0x344c), 0x17 },
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{ IMX290_REG_8BIT(0x344d), 0x00 },
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{ IMX290_REG_8BIT(0x344e), 0x17 },
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{ IMX290_REG_8BIT(0x344f), 0x00 },
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{ IMX290_REG_8BIT(0x3450), 0x57 },
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{ IMX290_REG_8BIT(0x3451), 0x00 },
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{ IMX290_REG_8BIT(0x3452), 0x17 },
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{ IMX290_REG_8BIT(0x3453), 0x00 },
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{ IMX290_REG_8BIT(0x3454), 0x17 },
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{ IMX290_REG_8BIT(0x3455), 0x00 },
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{ IMX290_REPETITION, 0x10 },
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{ IMX290_TCLKPOST, 79 },
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{ IMX290_THSZERO, 47 },
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{ IMX290_THSPREPARE, 23 },
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{ IMX290_TCLKTRAIL, 23 },
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{ IMX290_THSTRAIL, 23 },
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{ IMX290_TCLKZERO, 87 },
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{ IMX290_TCLKPREPARE, 23 },
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{ IMX290_TLPX, 23 },
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};
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static const struct imx290_regval imx290_10bit_settings[] = {
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{ IMX290_REG_8BIT(0x3005), 0x00},
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{ IMX290_REG_8BIT(0x3046), 0x00},
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{ IMX290_REG_8BIT(0x3129), 0x1d},
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{ IMX290_REG_8BIT(0x317c), 0x12},
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{ IMX290_REG_8BIT(0x31ec), 0x37},
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{ IMX290_REG_8BIT(0x3441), 0x0a},
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{ IMX290_REG_8BIT(0x3442), 0x0a},
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{ IMX290_REG_8BIT(0x300a), 0x3c},
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{ IMX290_REG_8BIT(0x300b), 0x00},
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{ IMX290_ADBIT, IMX290_ADBIT_10BIT },
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{ IMX290_OUT_CTRL, IMX290_ODBIT_10BIT },
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{ IMX290_ADBIT1, IMX290_ADBIT1_10BIT },
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{ IMX290_ADBIT2, IMX290_ADBIT2_10BIT },
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{ IMX290_ADBIT3, IMX290_ADBIT3_10BIT },
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{ IMX290_CSI_DT_FMT, IMX290_CSI_DT_FMT_RAW10 },
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{ IMX290_BLKLEVEL, 60 },
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};
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static const struct imx290_regval imx290_12bit_settings[] = {
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{ IMX290_REG_8BIT(0x3005), 0x01 },
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{ IMX290_REG_8BIT(0x3046), 0x01 },
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{ IMX290_REG_8BIT(0x3129), 0x00 },
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{ IMX290_REG_8BIT(0x317c), 0x00 },
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{ IMX290_REG_8BIT(0x31ec), 0x0e },
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{ IMX290_REG_8BIT(0x3441), 0x0c },
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{ IMX290_REG_8BIT(0x3442), 0x0c },
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{ IMX290_REG_8BIT(0x300a), 0xf0 },
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{ IMX290_REG_8BIT(0x300b), 0x00 },
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{ IMX290_ADBIT, IMX290_ADBIT_12BIT },
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{ IMX290_OUT_CTRL, IMX290_ODBIT_12BIT },
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{ IMX290_ADBIT1, IMX290_ADBIT1_12BIT },
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{ IMX290_ADBIT2, IMX290_ADBIT2_12BIT },
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{ IMX290_ADBIT3, IMX290_ADBIT3_12BIT },
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{ IMX290_CSI_DT_FMT, IMX290_CSI_DT_FMT_RAW12 },
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{ IMX290_BLKLEVEL, 240 },
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};
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/* supported link frequencies */
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