Blackfin: BF51x/BF52x: support GPIO Hysteresis/Schmitt Trigger options
Newer parts have optional Hysteresis/Schmitt Trigger options to help with dirty signals. So add some kconfig options for tuning this and enable it by default for people. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Michael Hennerich
Mike Frysinger
Родитель
812ae98f08
Коммит
7a4a207e74
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@ -864,6 +864,13 @@ void __init setup_arch(char **cmdline_p)
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bfin_write_EBIU_MODE(CONFIG_EBIU_MODEVAL);
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bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL);
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#endif
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#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
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bfin_write_PORTF_HYSTERISIS(HYST_PORTF_0_15);
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bfin_write_PORTG_HYSTERISIS(HYST_PORTG_0_15);
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bfin_write_PORTH_HYSTERISIS(HYST_PORTH_0_15);
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bfin_write_MISCPORT_HYSTERISIS((bfin_read_MISCPORT_HYSTERISIS() &
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~HYST_NONEGPIO_MASK) | HYST_NONEGPIO);
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#endif
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cclk = get_cclk();
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sclk = get_sclk();
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@ -62,6 +62,67 @@ config BF518_UART1_PORTG
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PORT G
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endchoice
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comment "Hysteresis/Schmitt Trigger Control"
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config BFIN_HYSTERESIS_CONTROL
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bool "Enable Hysteresis Control"
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help
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The ADSP-BF51x allows to control input hysteresis for Port F,
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Port G and Port H and other processor signal inputs.
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The Schmitt trigger enables can be set only for pin groups.
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Saying Y will overwrite the default reset or boot loader
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initialization.
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menu "PORT F"
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depends on BFIN_HYSTERESIS_CONTROL
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config GPIO_HYST_PORTF_0_7
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bool "Enable Hysteresis on PORTF {0...7}"
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config GPIO_HYST_PORTF_8_9
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bool "Enable Hysteresis on PORTF {8, 9}"
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config GPIO_HYST_PORTF_10
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bool "Enable Hysteresis on PORTF 10"
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config GPIO_HYST_PORTF_11
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bool "Enable Hysteresis on PORTF 11"
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config GPIO_HYST_PORTF_12_13
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bool "Enable Hysteresis on PORTF {12, 13}"
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config GPIO_HYST_PORTF_14_15
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bool "Enable Hysteresis on PORTF {14, 15}"
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endmenu
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menu "PORT G"
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depends on BFIN_HYSTERESIS_CONTROL
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config GPIO_HYST_PORTG_0
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bool "Enable Hysteresis on PORTG 0"
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config GPIO_HYST_PORTG_1_4
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bool "Enable Hysteresis on PORTG {1...4}"
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config GPIO_HYST_PORTG_5_6
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bool "Enable Hysteresis on PORTG {5, 6}"
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config GPIO_HYST_PORTG_7_8
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bool "Enable Hysteresis on PORTG {7, 8}"
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config GPIO_HYST_PORTG_9
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bool "Enable Hysteresis on PORTG 9"
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config GPIO_HYST_PORTG_10
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bool "Enable Hysteresis on PORTG 10"
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config GPIO_HYST_PORTG_11_13
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bool "Enable Hysteresis on PORTG {11...13}"
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config GPIO_HYST_PORTG_14_15
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bool "Enable Hysteresis on PORTG {14, 15}"
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endmenu
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menu "PORT H"
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depends on BFIN_HYSTERESIS_CONTROL
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config GPIO_HYST_PORTH_0_7
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bool "Enable Hysteresis on PORTH {0...7}"
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endmenu
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menu "None-GPIO"
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depends on BFIN_HYSTERESIS_CONTROL
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config NONEGPIO_HYST_NMI_RST_BMODE
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bool "Enable Hysteresis on {NMI, RESET, BMODE}"
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config NONEGPIO_HYST_JTAG
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bool "Enable Hysteresis on JTAG"
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endmenu
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comment "Interrupt Priority Assignment"
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menu "Priority"
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@ -85,6 +85,111 @@
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#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
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/**************************** Hysteresis Settings ****************************/
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#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
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#ifdef CONFIG_GPIO_HYST_PORTF_0_7
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#define HYST_PORTF_0_7 (1 << 0)
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#else
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#define HYST_PORTF_0_7 (0 << 0)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTF_8_9
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#define HYST_PORTF_8_9 (1 << 2)
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#else
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#define HYST_PORTF_8_9 (0 << 2)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTF_10
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#define HYST_PORTF_10 (1 << 4)
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#else
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#define HYST_PORTF_10 (0 << 4)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTF_11
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#define HYST_PORTF_11 (1 << 6)
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#else
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#define HYST_PORTF_11 (0 << 6)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTF_12_13
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#define HYST_PORTF_12_13 (1 << 8)
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#else
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#define HYST_PORTF_12_13 (0 << 8)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTF_14_15
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#define HYST_PORTF_14_15 (1 << 10)
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#else
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#define HYST_PORTF_14_15 (0 << 10)
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#endif
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#define HYST_PORTF_0_15 (HYST_PORTF_0_7 | HYST_PORTF_8_9 | HYST_PORTF_10 | \
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HYST_PORTF_11 | HYST_PORTF_12_13 | HYST_PORTF_14_15)
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#ifdef CONFIG_GPIO_HYST_PORTG_0
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#define HYST_PORTG_0 (1 << 0)
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#else
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#define HYST_PORTG_0 (0 << 0)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTG_1_4
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#define HYST_PORTG_1_4 (1 << 2)
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#else
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#define HYST_PORTG_1_4 (0 << 2)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTG_5_6
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#define HYST_PORTG_5_6 (1 << 4)
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#else
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#define HYST_PORTG_5_6 (0 << 4)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTG_7_8
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#define HYST_PORTG_7_8 (1 << 6)
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#else
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#define HYST_PORTG_7_8 (0 << 6)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTG_9
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#define HYST_PORTG_9 (1 << 8)
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#else
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#define HYST_PORTG_9 (0 << 8)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTG_10
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#define HYST_PORTG_10 (1 << 10)
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#else
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#define HYST_PORTG_10 (0 << 10)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTG_11_13
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#define HYST_PORTG_11_13 (1 << 12)
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#else
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#define HYST_PORTG_11_13 (0 << 12)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTG_14_15
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#define HYST_PORTG_14_15 (1 << 14)
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#else
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#define HYST_PORTG_14_15 (0 << 14)
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#endif
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#define HYST_PORTG_0_15 (HYST_PORTG_0 | HYST_PORTG_1_4 | HYST_PORTG_5_6 | \
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HYST_PORTG_7_8 | HYST_PORTG_9 | HYST_PORTG_10 | \
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HYST_PORTG_11_13 | HYST_PORTG_14_15)
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#ifdef CONFIG_GPIO_HYST_PORTH_0_7
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#define HYST_PORTH_0_7 (1 << 0)
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#else
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#define HYST_PORTH_0_7 (0 << 0)
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#endif
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#define HYST_PORTH_0_15 (HYST_PORTH_0_7)
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#ifdef CONFIG_NONEGPIO_HYST_NMI_RST_BMODE
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#define HYST_NMI_RST_BMODE (1 << 2)
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#else
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#define HYST_NMI_RST_BMODE (0 << 2)
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#endif
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#ifdef CONFIG_NONEGPIO_HYST_JTAG
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#define HYST_JTAG (1 << 4)
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#else
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#define HYST_JTAG (0 << 4)
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#endif
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#define HYST_NONEGPIO (HYST_NMI_RST_BMODE | HYST_JTAG)
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#define HYST_NONEGPIO_MASK (0x3C)
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#endif /* CONFIG_BFIN_HYSTERESIS_CONTROL */
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#ifdef CONFIG_BF518
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#define CPU "BF518"
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#define CPUID 0x27e8
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@ -79,6 +79,72 @@ config BF527_NAND_D_PORTH
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PORT H
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endchoice
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comment "Hysteresis/Schmitt Trigger Control"
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config BFIN_HYSTERESIS_CONTROL
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bool "Enable Hysteresis Control"
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help
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The ADSP-BF52x allows to control input hysteresis for Port F,
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Port G and Port H and other processor signal inputs.
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The Schmitt trigger enables can be set only for pin groups.
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Saying Y will overwrite the default reset or boot loader
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initialization.
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menu "PORT F"
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depends on BFIN_HYSTERESIS_CONTROL
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config GPIO_HYST_PORTF_0_7
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bool "Enable Hysteresis on PORTF {0...7}"
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config GPIO_HYST_PORTF_8_9
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bool "Enable Hysteresis on PORTF {8, 9}"
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config GPIO_HYST_PORTF_10
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bool "Enable Hysteresis on PORTF 10"
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config GPIO_HYST_PORTF_11
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bool "Enable Hysteresis on PORTF 11"
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config GPIO_HYST_PORTF_12_13
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bool "Enable Hysteresis on PORTF {12, 13}"
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config GPIO_HYST_PORTF_14_15
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bool "Enable Hysteresis on PORTF {14, 15}"
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endmenu
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menu "PORT G"
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depends on BFIN_HYSTERESIS_CONTROL
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config GPIO_HYST_PORTG_0
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bool "Enable Hysteresis on PORTG 0"
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config GPIO_HYST_PORTG_1_4
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bool "Enable Hysteresis on PORTG {1...4}"
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config GPIO_HYST_PORTG_5_6
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bool "Enable Hysteresis on PORTG {5, 6}"
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config GPIO_HYST_PORTG_7_8
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bool "Enable Hysteresis on PORTG {7, 8}"
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config GPIO_HYST_PORTG_9
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bool "Enable Hysteresis on PORTG 9"
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config GPIO_HYST_PORTG_10
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bool "Enable Hysteresis on PORTG 10"
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config GPIO_HYST_PORTG_11_13
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bool "Enable Hysteresis on PORTG {11...13}"
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config GPIO_HYST_PORTG_14_15
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bool "Enable Hysteresis on PORTG {14, 15}"
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endmenu
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menu "PORT H"
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depends on BFIN_HYSTERESIS_CONTROL
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config GPIO_HYST_PORTH_0_7
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bool "Enable Hysteresis on PORTH {0...7}"
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config GPIO_HYST_PORTH_8
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bool "Enable Hysteresis on PORTH 8"
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config GPIO_HYST_PORTH_9_15
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bool "Enable Hysteresis on PORTH {9...15}"
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endmenu
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menu "None-GPIO"
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depends on BFIN_HYSTERESIS_CONTROL
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config NONEGPIO_HYST_TMR0_FS1_PPICLK
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bool "Enable Hysteresis on {TMR0, PPI_FS1, PPI_CLK}"
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config NONEGPIO_HYST_NMI_RST_BMODE
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bool "Enable Hysteresis on {NMI, RESET, BMODE}"
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config NONEGPIO_HYST_JTAG
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bool "Enable Hysteresis on JTAG"
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endmenu
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comment "Interrupt Priority Assignment"
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menu "Priority"
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@ -85,6 +85,126 @@
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#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
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/**************************** Hysteresis Settings ****************************/
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#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
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#ifdef CONFIG_GPIO_HYST_PORTF_0_7
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#define HYST_PORTF_0_7 (1 << 0)
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#else
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#define HYST_PORTF_0_7 (0 << 0)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTF_8_9
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#define HYST_PORTF_8_9 (1 << 2)
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#else
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#define HYST_PORTF_8_9 (0 << 2)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTF_10
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#define HYST_PORTF_10 (1 << 4)
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#else
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#define HYST_PORTF_10 (0 << 4)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTF_11
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#define HYST_PORTF_11 (1 << 6)
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#else
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#define HYST_PORTF_11 (0 << 6)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTF_12_13
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#define HYST_PORTF_12_13 (1 << 8)
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#else
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#define HYST_PORTF_12_13 (0 << 8)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTF_14_15
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#define HYST_PORTF_14_15 (1 << 10)
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#else
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#define HYST_PORTF_14_15 (0 << 10)
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#endif
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#define HYST_PORTF_0_15 (HYST_PORTF_0_7 | HYST_PORTF_8_9 | HYST_PORTF_10 | \
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HYST_PORTF_11 | HYST_PORTF_12_13 | HYST_PORTF_14_15)
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#ifdef CONFIG_GPIO_HYST_PORTG_0
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#define HYST_PORTG_0 (1 << 0)
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#else
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#define HYST_PORTG_0 (0 << 0)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTG_1_4
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#define HYST_PORTG_1_4 (1 << 2)
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#else
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#define HYST_PORTG_1_4 (0 << 2)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTG_5_6
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#define HYST_PORTG_5_6 (1 << 4)
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#else
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#define HYST_PORTG_5_6 (0 << 4)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTG_7_8
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#define HYST_PORTG_7_8 (1 << 6)
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#else
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#define HYST_PORTG_7_8 (0 << 6)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTG_9
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#define HYST_PORTG_9 (1 << 8)
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#else
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#define HYST_PORTG_9 (0 << 8)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTG_10
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#define HYST_PORTG_10 (1 << 10)
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#else
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#define HYST_PORTG_10 (0 << 10)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTG_11_13
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#define HYST_PORTG_11_13 (1 << 12)
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#else
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#define HYST_PORTG_11_13 (0 << 12)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTG_14_15
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#define HYST_PORTG_14_15 (1 << 14)
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#else
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#define HYST_PORTG_14_15 (0 << 14)
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#endif
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#define HYST_PORTG_0_15 (HYST_PORTG_0 | HYST_PORTG_1_4 | HYST_PORTG_5_6 | \
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HYST_PORTG_7_8 | HYST_PORTG_9 | HYST_PORTG_10 | \
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HYST_PORTG_11_13 | HYST_PORTG_14_15)
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#ifdef CONFIG_GPIO_HYST_PORTH_0_7
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#define HYST_PORTH_0_7 (1 << 0)
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#else
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#define HYST_PORTH_0_7 (0 << 0)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTH_8
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#define HYST_PORTH_8 (1 << 2)
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#else
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#define HYST_PORTH_8 (0 << 2)
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#endif
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#ifdef CONFIG_GPIO_HYST_PORTH_9_15
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#define HYST_PORTH_9_15 (1 << 4)
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#else
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#define HYST_PORTH_9_15 (0 << 4)
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#endif
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#define HYST_PORTH_0_15 (HYST_PORTH_0_7 | HYST_PORTH_8 | HYST_PORTH_9_15)
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#ifdef CONFIG_NONEGPIO_HYST_TMR0_FS1_PPICLK
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#define HYST_TMR0_FS1_PPICLK (1 << 0)
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#else
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#define HYST_TMR0_FS1_PPICLK (0 << 0)
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#endif
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#ifdef CONFIG_NONEGPIO_HYST_NMI_RST_BMODE
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#define HYST_NMI_RST_BMODE (1 << 2)
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#else
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#define HYST_NMI_RST_BMODE (0 << 2)
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#endif
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#ifdef CONFIG_NONEGPIO_HYST_JTAG
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#define HYST_JTAG (1 << 4)
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#else
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#define HYST_JTAG (0 << 4)
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#endif
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#define HYST_NONEGPIO (HYST_TMR0_FS1_PPICLK | HYST_NMI_RST_BMODE | HYST_JTAG)
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#define HYST_NONEGPIO_MASK (0x3F)
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#endif /* CONFIG_BFIN_HYSTERESIS_CONTROL */
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#ifdef CONFIG_BF527
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#define CPU "BF527"
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#define CPUID 0x27e0
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