mtd/ifc: Add support for IFC controller version 2.0
The new IFC controller version 2.0 has a different memory map page. Upto IFC 1.4 PAGE size is 4 KB and from IFC2.0 PAGE size is 64KB. This patch segregates the IFC global and runtime registers to appropriate PAGE sizes. Signed-off-by: Jaiprakash Singh <b44839@freescale.com> Signed-off-by: Raghav Dogra <raghav@freescale.com> Acked-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Acked-by: Scott Wood <oss@buserror.net> Acked-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This commit is contained in:
Raghav Dogra
Boris Brezillon
Родитель
11eaf6df1c
Коммит
7a65417216
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@ -59,11 +59,11 @@ int fsl_ifc_find(phys_addr_t addr_base)
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{
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int i = 0;
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if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->regs)
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if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->gregs)
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return -ENODEV;
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for (i = 0; i < fsl_ifc_ctrl_dev->banks; i++) {
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u32 cspr = ifc_in32(&fsl_ifc_ctrl_dev->regs->cspr_cs[i].cspr);
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u32 cspr = ifc_in32(&fsl_ifc_ctrl_dev->gregs->cspr_cs[i].cspr);
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if (cspr & CSPR_V && (cspr & CSPR_BA) ==
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convert_ifc_address(addr_base))
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return i;
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@ -75,7 +75,7 @@ EXPORT_SYMBOL(fsl_ifc_find);
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static int fsl_ifc_ctrl_init(struct fsl_ifc_ctrl *ctrl)
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{
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struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
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struct fsl_ifc_global __iomem *ifc = ctrl->gregs;
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/*
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* Clear all the common status and event registers
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@ -104,7 +104,7 @@ static int fsl_ifc_ctrl_remove(struct platform_device *dev)
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irq_dispose_mapping(ctrl->nand_irq);
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irq_dispose_mapping(ctrl->irq);
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iounmap(ctrl->regs);
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iounmap(ctrl->gregs);
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dev_set_drvdata(&dev->dev, NULL);
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kfree(ctrl);
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@ -122,7 +122,7 @@ static DEFINE_SPINLOCK(nand_irq_lock);
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static u32 check_nand_stat(struct fsl_ifc_ctrl *ctrl)
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{
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struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
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struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
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unsigned long flags;
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u32 stat;
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@ -157,7 +157,7 @@ static irqreturn_t fsl_ifc_nand_irq(int irqno, void *data)
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static irqreturn_t fsl_ifc_ctrl_irq(int irqno, void *data)
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{
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struct fsl_ifc_ctrl *ctrl = data;
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struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
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struct fsl_ifc_global __iomem *ifc = ctrl->gregs;
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u32 err_axiid, err_srcid, status, cs_err, err_addr;
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irqreturn_t ret = IRQ_NONE;
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@ -215,6 +215,7 @@ static int fsl_ifc_ctrl_probe(struct platform_device *dev)
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{
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int ret = 0;
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int version, banks;
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void __iomem *addr;
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dev_info(&dev->dev, "Freescale Integrated Flash Controller\n");
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@ -225,22 +226,13 @@ static int fsl_ifc_ctrl_probe(struct platform_device *dev)
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dev_set_drvdata(&dev->dev, fsl_ifc_ctrl_dev);
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/* IOMAP the entire IFC region */
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fsl_ifc_ctrl_dev->regs = of_iomap(dev->dev.of_node, 0);
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if (!fsl_ifc_ctrl_dev->regs) {
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fsl_ifc_ctrl_dev->gregs = of_iomap(dev->dev.of_node, 0);
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if (!fsl_ifc_ctrl_dev->gregs) {
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dev_err(&dev->dev, "failed to get memory region\n");
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ret = -ENODEV;
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goto err;
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}
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version = ifc_in32(&fsl_ifc_ctrl_dev->regs->ifc_rev) &
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FSL_IFC_VERSION_MASK;
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banks = (version == FSL_IFC_VERSION_1_0_0) ? 4 : 8;
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dev_info(&dev->dev, "IFC version %d.%d, %d banks\n",
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version >> 24, (version >> 16) & 0xf, banks);
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fsl_ifc_ctrl_dev->version = version;
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fsl_ifc_ctrl_dev->banks = banks;
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if (of_property_read_bool(dev->dev.of_node, "little-endian")) {
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fsl_ifc_ctrl_dev->little_endian = true;
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dev_dbg(&dev->dev, "IFC REGISTERS are LITTLE endian\n");
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@ -249,8 +241,9 @@ static int fsl_ifc_ctrl_probe(struct platform_device *dev)
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dev_dbg(&dev->dev, "IFC REGISTERS are BIG endian\n");
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}
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version = ioread32be(&fsl_ifc_ctrl_dev->regs->ifc_rev) &
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version = ifc_in32(&fsl_ifc_ctrl_dev->gregs->ifc_rev) &
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FSL_IFC_VERSION_MASK;
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banks = (version == FSL_IFC_VERSION_1_0_0) ? 4 : 8;
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dev_info(&dev->dev, "IFC version %d.%d, %d banks\n",
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version >> 24, (version >> 16) & 0xf, banks);
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@ -258,6 +251,13 @@ static int fsl_ifc_ctrl_probe(struct platform_device *dev)
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fsl_ifc_ctrl_dev->version = version;
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fsl_ifc_ctrl_dev->banks = banks;
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addr = fsl_ifc_ctrl_dev->gregs;
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if (version >= FSL_IFC_VERSION_2_0_0)
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addr += PGOFFSET_64K;
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else
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addr += PGOFFSET_4K;
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fsl_ifc_ctrl_dev->rregs = addr;
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/* get the Controller level irq */
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fsl_ifc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
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if (fsl_ifc_ctrl_dev->irq == 0) {
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@ -232,7 +232,7 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
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struct fsl_ifc_ctrl *ctrl = priv->ctrl;
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struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
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struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
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int buf_num;
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ifc_nand_ctrl->page = page_addr;
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@ -295,7 +295,7 @@ static void fsl_ifc_run_command(struct mtd_info *mtd)
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struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
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struct fsl_ifc_ctrl *ctrl = priv->ctrl;
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struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
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struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
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struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
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u32 eccstat[4];
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int i;
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@ -371,7 +371,7 @@ static void fsl_ifc_do_read(struct nand_chip *chip,
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{
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struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
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struct fsl_ifc_ctrl *ctrl = priv->ctrl;
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struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
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struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
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/* Program FIR/IFC_NAND_FCR0 for Small/Large page */
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if (mtd->writesize > 512) {
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@ -411,7 +411,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
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struct fsl_ifc_ctrl *ctrl = priv->ctrl;
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struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
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struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
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/* clear the read buffer */
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ifc_nand_ctrl->read_bytes = 0;
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@ -723,7 +723,7 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
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{
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struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
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struct fsl_ifc_ctrl *ctrl = priv->ctrl;
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struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
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struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
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u32 nand_fsr;
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/* Use READ_STATUS command, but wait for the device to be ready */
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@ -825,39 +825,42 @@ static int fsl_ifc_chip_init_tail(struct mtd_info *mtd)
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static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
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{
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struct fsl_ifc_ctrl *ctrl = priv->ctrl;
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struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
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struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs;
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struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
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uint32_t csor = 0, csor_8k = 0, csor_ext = 0;
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uint32_t cs = priv->bank;
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/* Save CSOR and CSOR_ext */
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csor = ifc_in32(&ifc->csor_cs[cs].csor);
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csor_ext = ifc_in32(&ifc->csor_cs[cs].csor_ext);
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csor = ifc_in32(&ifc_global->csor_cs[cs].csor);
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csor_ext = ifc_in32(&ifc_global->csor_cs[cs].csor_ext);
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/* chage PageSize 8K and SpareSize 1K*/
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csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
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ifc_out32(csor_8k, &ifc->csor_cs[cs].csor);
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ifc_out32(0x0000400, &ifc->csor_cs[cs].csor_ext);
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ifc_out32(csor_8k, &ifc_global->csor_cs[cs].csor);
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ifc_out32(0x0000400, &ifc_global->csor_cs[cs].csor_ext);
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/* READID */
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ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
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(IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
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(IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT),
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&ifc->ifc_nand.nand_fir0);
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(IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
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(IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT),
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&ifc_runtime->ifc_nand.nand_fir0);
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ifc_out32(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT,
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&ifc->ifc_nand.nand_fcr0);
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ifc_out32(0x0, &ifc->ifc_nand.row3);
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&ifc_runtime->ifc_nand.nand_fcr0);
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ifc_out32(0x0, &ifc_runtime->ifc_nand.row3);
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ifc_out32(0x0, &ifc->ifc_nand.nand_fbcr);
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ifc_out32(0x0, &ifc_runtime->ifc_nand.nand_fbcr);
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/* Program ROW0/COL0 */
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ifc_out32(0x0, &ifc->ifc_nand.row0);
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ifc_out32(0x0, &ifc->ifc_nand.col0);
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ifc_out32(0x0, &ifc_runtime->ifc_nand.row0);
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ifc_out32(0x0, &ifc_runtime->ifc_nand.col0);
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/* set the chip select for NAND Transaction */
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ifc_out32(cs << IFC_NAND_CSEL_SHIFT, &ifc->ifc_nand.nand_csel);
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ifc_out32(cs << IFC_NAND_CSEL_SHIFT,
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&ifc_runtime->ifc_nand.nand_csel);
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/* start read seq */
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ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
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ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT,
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&ifc_runtime->ifc_nand.nandseq_strt);
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/* wait for command complete flag or timeout */
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wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
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@ -867,14 +870,15 @@ static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
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printk(KERN_ERR "fsl-ifc: Failed to Initialise SRAM\n");
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/* Restore CSOR and CSOR_ext */
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ifc_out32(csor, &ifc->csor_cs[cs].csor);
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ifc_out32(csor_ext, &ifc->csor_cs[cs].csor_ext);
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ifc_out32(csor, &ifc_global->csor_cs[cs].csor);
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ifc_out32(csor_ext, &ifc_global->csor_cs[cs].csor_ext);
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}
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static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
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{
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struct fsl_ifc_ctrl *ctrl = priv->ctrl;
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struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
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struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
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struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs;
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struct nand_chip *chip = &priv->chip;
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struct mtd_info *mtd = nand_to_mtd(&priv->chip);
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struct nand_ecclayout *layout;
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@ -886,7 +890,8 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
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/* fill in nand_chip structure */
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/* set up function call table */
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if ((ifc_in32(&ifc->cspr_cs[priv->bank].cspr)) & CSPR_PORT_SIZE_16)
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if ((ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr))
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& CSPR_PORT_SIZE_16)
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chip->read_byte = fsl_ifc_read_byte16;
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else
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chip->read_byte = fsl_ifc_read_byte;
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@ -900,13 +905,14 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
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chip->bbt_td = &bbt_main_descr;
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chip->bbt_md = &bbt_mirror_descr;
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ifc_out32(0x0, &ifc->ifc_nand.ncfgr);
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ifc_out32(0x0, &ifc_runtime->ifc_nand.ncfgr);
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/* set up nand options */
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chip->bbt_options = NAND_BBT_USE_FLASH;
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chip->options = NAND_NO_SUBPAGE_WRITE;
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if (ifc_in32(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) {
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if (ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr)
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& CSPR_PORT_SIZE_16) {
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chip->read_byte = fsl_ifc_read_byte16;
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chip->options |= NAND_BUSWIDTH_16;
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} else {
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@ -919,7 +925,7 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
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chip->ecc.read_page = fsl_ifc_read_page;
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chip->ecc.write_page = fsl_ifc_write_page;
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csor = ifc_in32(&ifc->csor_cs[priv->bank].csor);
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csor = ifc_in32(&ifc_global->csor_cs[priv->bank].csor);
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/* Hardware generates ECC per 512 Bytes */
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chip->ecc.size = 512;
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@ -1007,10 +1013,10 @@ static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv)
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return 0;
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}
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static int match_bank(struct fsl_ifc_regs __iomem *ifc, int bank,
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static int match_bank(struct fsl_ifc_global __iomem *ifc_global, int bank,
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phys_addr_t addr)
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{
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u32 cspr = ifc_in32(&ifc->cspr_cs[bank].cspr);
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u32 cspr = ifc_in32(&ifc_global->cspr_cs[bank].cspr);
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if (!(cspr & CSPR_V))
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return 0;
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@ -1024,7 +1030,7 @@ static DEFINE_MUTEX(fsl_ifc_nand_mutex);
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static int fsl_ifc_nand_probe(struct platform_device *dev)
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{
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struct fsl_ifc_regs __iomem *ifc;
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struct fsl_ifc_runtime __iomem *ifc;
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struct fsl_ifc_mtd *priv;
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struct resource res;
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static const char *part_probe_types[]
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@ -1034,9 +1040,9 @@ static int fsl_ifc_nand_probe(struct platform_device *dev)
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struct device_node *node = dev->dev.of_node;
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struct mtd_info *mtd;
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if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->regs)
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if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->rregs)
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return -ENODEV;
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ifc = fsl_ifc_ctrl_dev->regs;
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ifc = fsl_ifc_ctrl_dev->rregs;
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/* get, allocate and map the memory resource */
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ret = of_address_to_resource(node, 0, &res);
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@ -1047,7 +1053,7 @@ static int fsl_ifc_nand_probe(struct platform_device *dev)
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/* find which chip select it is connected to */
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for (bank = 0; bank < fsl_ifc_ctrl_dev->banks; bank++) {
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if (match_bank(ifc, bank, res.start))
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if (match_bank(fsl_ifc_ctrl_dev->gregs, bank, res.start))
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break;
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}
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@ -39,6 +39,10 @@
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#define FSL_IFC_VERSION_MASK 0x0F0F0000
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#define FSL_IFC_VERSION_1_0_0 0x01000000
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#define FSL_IFC_VERSION_1_1_0 0x01010000
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#define FSL_IFC_VERSION_2_0_0 0x02000000
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#define PGOFFSET_64K (64*1024)
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#define PGOFFSET_4K (4*1024)
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/*
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* CSPR - Chip Select Property Register
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@ -723,20 +727,26 @@ struct fsl_ifc_nand {
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__be32 nand_evter_en;
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u32 res17[0x2];
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__be32 nand_evter_intr_en;
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u32 res18[0x2];
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__be32 nand_vol_addr_stat;
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u32 res18;
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__be32 nand_erattr0;
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__be32 nand_erattr1;
|
||||
u32 res19[0x10];
|
||||
__be32 nand_fsr;
|
||||
u32 res20;
|
||||
__be32 nand_eccstat[4];
|
||||
u32 res21[0x20];
|
||||
u32 res20[0x3];
|
||||
__be32 nand_eccstat[6];
|
||||
u32 res21[0x1c];
|
||||
__be32 nanndcr;
|
||||
u32 res22[0x2];
|
||||
__be32 nand_autoboot_trgr;
|
||||
u32 res23;
|
||||
__be32 nand_mdr;
|
||||
u32 res24[0x5C];
|
||||
u32 res24[0x1C];
|
||||
__be32 nand_dll_lowcfg0;
|
||||
__be32 nand_dll_lowcfg1;
|
||||
u32 res25;
|
||||
__be32 nand_dll_lowstat;
|
||||
u32 res26[0x3c];
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -771,13 +781,12 @@ struct fsl_ifc_gpcm {
|
|||
__be32 gpcm_erattr1;
|
||||
__be32 gpcm_erattr2;
|
||||
__be32 gpcm_stat;
|
||||
u32 res4[0x1F3];
|
||||
};
|
||||
|
||||
/*
|
||||
* IFC Controller Registers
|
||||
*/
|
||||
struct fsl_ifc_regs {
|
||||
struct fsl_ifc_global {
|
||||
__be32 ifc_rev;
|
||||
u32 res1[0x2];
|
||||
struct {
|
||||
|
|
@ -803,21 +812,26 @@ struct fsl_ifc_regs {
|
|||
} ftim_cs[FSL_IFC_BANK_COUNT];
|
||||
u32 res9[0x30];
|
||||
__be32 rb_stat;
|
||||
u32 res10[0x2];
|
||||
__be32 rb_map;
|
||||
__be32 wb_map;
|
||||
__be32 ifc_gcr;
|
||||
u32 res11[0x2];
|
||||
u32 res10[0x2];
|
||||
__be32 cm_evter_stat;
|
||||
u32 res12[0x2];
|
||||
u32 res11[0x2];
|
||||
__be32 cm_evter_en;
|
||||
u32 res13[0x2];
|
||||
u32 res12[0x2];
|
||||
__be32 cm_evter_intr_en;
|
||||
u32 res14[0x2];
|
||||
u32 res13[0x2];
|
||||
__be32 cm_erattr0;
|
||||
__be32 cm_erattr1;
|
||||
u32 res15[0x2];
|
||||
u32 res14[0x2];
|
||||
__be32 ifc_ccr;
|
||||
__be32 ifc_csr;
|
||||
u32 res16[0x2EB];
|
||||
__be32 ddr_ccr_low;
|
||||
};
|
||||
|
||||
|
||||
struct fsl_ifc_runtime {
|
||||
struct fsl_ifc_nand ifc_nand;
|
||||
struct fsl_ifc_nor ifc_nor;
|
||||
struct fsl_ifc_gpcm ifc_gpcm;
|
||||
|
|
@ -831,7 +845,8 @@ extern int fsl_ifc_find(phys_addr_t addr_base);
|
|||
struct fsl_ifc_ctrl {
|
||||
/* device info */
|
||||
struct device *dev;
|
||||
struct fsl_ifc_regs __iomem *regs;
|
||||
struct fsl_ifc_global __iomem *gregs;
|
||||
struct fsl_ifc_runtime __iomem *rregs;
|
||||
int irq;
|
||||
int nand_irq;
|
||||
spinlock_t lock;
|
||||
|
|
|
|||
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