drm/i915: Remove high level intel_edp_vdd_{on, off}() from hpd/detect
want_panel_vdd is a bool so it can't cope with interleaving on/off calls from multiple threads. If we want to make that possible we'd need to convert want_panel_vdd into a proper ref count. But an easier fix is to remove the high level vdd on/off calls from detect/hpd code paths and just rely on the delayed vdd off to avoid needless vdd on<->off ping pong. After this change only the encoder enable/disable paths use the high level functions, which is fine since both the on and off low level edp vdd calls from intel_dp_aux_ch() happen without dropping pps_mutex in between and so want_panel_vdd can't change in between. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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c17ed5b5a4
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7a66800e03
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@ -3846,8 +3846,6 @@ intel_dp_probe_oui(struct intel_dp *intel_dp)
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if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
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return;
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intel_edp_panel_vdd_on(intel_dp);
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if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
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DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
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buf[0], buf[1], buf[2]);
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@ -3855,8 +3853,6 @@ intel_dp_probe_oui(struct intel_dp *intel_dp)
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if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
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DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
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buf[0], buf[1], buf[2]);
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intel_edp_panel_vdd_off(intel_dp, false);
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}
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static bool
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@ -3870,7 +3866,6 @@ intel_dp_probe_mst(struct intel_dp *intel_dp)
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if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
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return false;
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intel_edp_panel_vdd_on(intel_dp);
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if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
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if (buf[0] & DP_MST_CAP) {
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DRM_DEBUG_KMS("Sink is MST capable\n");
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@ -3880,7 +3875,6 @@ intel_dp_probe_mst(struct intel_dp *intel_dp)
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intel_dp->is_mst = false;
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}
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}
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intel_edp_panel_vdd_off(intel_dp, false);
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drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
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return intel_dp->is_mst;
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@ -5086,9 +5080,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
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intel_edp_panel_vdd_sanitize(intel_encoder);
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/* Cache DPCD and EDID for edp. */
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intel_edp_panel_vdd_on(intel_dp);
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has_dpcd = intel_dp_get_dpcd(intel_dp);
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intel_edp_panel_vdd_off(intel_dp, false);
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if (has_dpcd) {
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if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
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