Linux 3.5-rc4
-----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.18 (GNU/Linux) iQEcBAABAgAGBQJP53AxAAoJEHm+PkMAQRiGs2QH/RaqkXz96fwjhDcyiKpDqA3c kGuS5mz5cOhnqKSmR88HFm6pwuhLux/qSJzeAmoQy1MC8a0ACx7AnANW0lfN3/qe /HGYz8h60yCL/fhn8/bUYtdt9xsoDqoDcq/ooFl9mcsJGWbC6WeMSZU5dAUYqviE qFrp5zjY07FG53CRGT0hFpezQNwNL+VLH30CF9LD+fJLPVEYum2zBNGXWM42rcw5 fxzGL/6SO8YqA/Upic1ht6HAd6s5LOrlST7qvnyXUMvRXN5z/Y92ueYJZefkS1Om ohuLIKM2bv9/dJS67H8N2baSKGCzBdfSe5/5WaHdLYW9MiVju0wRl6HPJtAMrkk= =H8t8 -----END PGP SIGNATURE----- Merge tag 'v3.5-rc4' into drm-intel-next-queued I want to merge the "no more fake agp on gen6+" patches into drm-intel-next (well, the last pieces). But a patch in 3.5-rc4 also adds a new use of dev->agp. Hence the backmarge to sort this out, for otherwise drm-intel-next merged into Linus' tree would conflict in the relevant code, things would compile but nicely OOPS at driver load :( Conflicts in this merge are just simple cases of "both branches changed/added lines at the same place". The only tricky part is to keep the order correct wrt the unwind code in case of errors in intel_ringbuffer.c (and the MI_DISPLAY_FLIP #defines in i915_reg.h together, obviously). Conflicts: drivers/gpu/drm/i915/i915_reg.h drivers/gpu/drm/i915/intel_ringbuffer.c Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter
Коммит
7b0cfee1a2
3
.mailmap
3
.mailmap
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@ -111,5 +111,8 @@ Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de>
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Uwe Kleine-König <ukl@pengutronix.de>
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Uwe Kleine-König <Uwe.Kleine-Koenig@digi.com>
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Valdis Kletnieks <Valdis.Kletnieks@vt.edu>
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Viresh Kumar <viresh.linux@gmail.com> <viresh.kumar@st.com>
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Takashi YOSHII <takashi.yoshii.zj@renesas.com>
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Yusuke Goda <goda.yusuke@renesas.com>
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Gustavo Padovan <gustavo@las.ic.unicamp.br>
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Gustavo Padovan <padovan@profusion.mobi>
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@ -6,13 +6,21 @@ Description: This is a read-only file. Dumps below driver information and
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hardware registers.
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- S ACTive
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- Command Issue
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- Allocated
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- Completed
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- PORT IRQ STAT
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- HOST IRQ STAT
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- Allocated
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- Commands in Q
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What: /sys/block/rssd*/status
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Date: April 2012
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KernelVersion: 3.4
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Contact: Asai Thambi S P <asamymuthupa@micron.com>
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Description: This is a read-only file. Indicates the status of the device.
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Description: This is a read-only file. Indicates the status of the device.
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What: /sys/block/rssd*/flags
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Date: May 2012
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KernelVersion: 3.5
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Contact: Asai Thambi S P <asamymuthupa@micron.com>
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Description: This is a read-only file. Dumps the flags in port and driver
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data structure
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@ -0,0 +1,77 @@
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What: /sys/bus/fcoe/ctlr_X
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Date: March 2012
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KernelVersion: TBD
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Contact: Robert Love <robert.w.love@intel.com>, devel@open-fcoe.org
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Description: 'FCoE Controller' instances on the fcoe bus
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Attributes:
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fcf_dev_loss_tmo: Device loss timeout peroid (see below). Changing
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this value will change the dev_loss_tmo for all
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FCFs discovered by this controller.
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lesb_link_fail: Link Error Status Block (LESB) link failure count.
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lesb_vlink_fail: Link Error Status Block (LESB) virtual link
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failure count.
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lesb_miss_fka: Link Error Status Block (LESB) missed FCoE
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Initialization Protocol (FIP) Keep-Alives (FKA).
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lesb_symb_err: Link Error Status Block (LESB) symbolic error count.
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lesb_err_block: Link Error Status Block (LESB) block error count.
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lesb_fcs_error: Link Error Status Block (LESB) Fibre Channel
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Serivces error count.
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Notes: ctlr_X (global increment starting at 0)
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What: /sys/bus/fcoe/fcf_X
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Date: March 2012
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KernelVersion: TBD
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Contact: Robert Love <robert.w.love@intel.com>, devel@open-fcoe.org
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Description: 'FCoE FCF' instances on the fcoe bus. A FCF is a Fibre Channel
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Forwarder, which is a FCoE switch that can accept FCoE
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(Ethernet) packets, unpack them, and forward the embedded
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Fibre Channel frames into a FC fabric. It can also take
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outbound FC frames and pack them in Ethernet packets to
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be sent to their destination on the Ethernet segment.
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Attributes:
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fabric_name: Identifies the fabric that the FCF services.
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switch_name: Identifies the FCF.
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priority: The switch's priority amongst other FCFs on the same
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fabric.
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selected: 1 indicates that the switch has been selected for use;
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0 indicates that the swich will not be used.
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fc_map: The Fibre Channel MAP
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vfid: The Virtual Fabric ID
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mac: The FCF's MAC address
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fka_peroid: The FIP Keep-Alive peroid
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fabric_state: The internal kernel state
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"Unknown" - Initialization value
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"Disconnected" - No link to the FCF/fabric
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"Connected" - Host is connected to the FCF
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"Deleted" - FCF is being removed from the system
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dev_loss_tmo: The device loss timeout peroid for this FCF.
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Notes: A device loss infrastructre similar to the FC Transport's
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is present in fcoe_sysfs. It is nice to have so that a
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link flapping adapter doesn't continually advance the count
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used to identify the discovered FCF. FCFs will exist in a
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"Disconnected" state until either the timer expires and the
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FCF becomes "Deleted" or the FCF is rediscovered and becomes
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"Connected."
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Users: The first user of this interface will be the fcoeadm application,
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which is commonly packaged in the fcoe-utils package.
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@ -219,6 +219,7 @@ What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_scale
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What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_supply_scale
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What: /sys/bus/iio/devices/iio:deviceX/in_voltage_scale
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What: /sys/bus/iio/devices/iio:deviceX/out_voltageY_scale
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What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY_scale
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What: /sys/bus/iio/devices/iio:deviceX/in_accel_scale
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What: /sys/bus/iio/devices/iio:deviceX/in_accel_peak_scale
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What: /sys/bus/iio/devices/iio:deviceX/in_anglvel_scale
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@ -273,6 +274,7 @@ What: /sys/bus/iio/devices/iio:deviceX/in_accel_scale_available
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What: /sys/.../iio:deviceX/in_voltageX_scale_available
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What: /sys/.../iio:deviceX/in_voltage-voltage_scale_available
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What: /sys/.../iio:deviceX/out_voltageX_scale_available
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What: /sys/.../iio:deviceX/out_altvoltageX_scale_available
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What: /sys/.../iio:deviceX/in_capacitance_scale_available
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KernelVersion: 2.635
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Contact: linux-iio@vger.kernel.org
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@ -298,14 +300,19 @@ Description:
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gives the 3dB frequency of the filter in Hz.
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What: /sys/bus/iio/devices/iio:deviceX/out_voltageY_raw
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What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY_raw
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KernelVersion: 2.6.37
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Contact: linux-iio@vger.kernel.org
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Description:
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Raw (unscaled, no bias etc.) output voltage for
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channel Y. The number must always be specified and
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unique if the output corresponds to a single channel.
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While DAC like devices typically use out_voltage,
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a continuous frequency generating device, such as
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a DDS or PLL should use out_altvoltage.
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What: /sys/bus/iio/devices/iio:deviceX/out_voltageY&Z_raw
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What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY&Z_raw
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KernelVersion: 2.6.37
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Contact: linux-iio@vger.kernel.org
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Description:
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@ -316,6 +323,8 @@ Description:
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|||
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What: /sys/bus/iio/devices/iio:deviceX/out_voltageY_powerdown_mode
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What: /sys/bus/iio/devices/iio:deviceX/out_voltage_powerdown_mode
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What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY_powerdown_mode
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What: /sys/bus/iio/devices/iio:deviceX/out_altvoltage_powerdown_mode
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KernelVersion: 2.6.38
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Contact: linux-iio@vger.kernel.org
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Description:
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@ -330,6 +339,8 @@ Description:
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|||
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What: /sys/.../iio:deviceX/out_votlageY_powerdown_mode_available
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What: /sys/.../iio:deviceX/out_voltage_powerdown_mode_available
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What: /sys/.../iio:deviceX/out_altvotlageY_powerdown_mode_available
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What: /sys/.../iio:deviceX/out_altvoltage_powerdown_mode_available
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KernelVersion: 2.6.38
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Contact: linux-iio@vger.kernel.org
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Description:
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@ -338,6 +349,8 @@ Description:
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|||
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What: /sys/bus/iio/devices/iio:deviceX/out_voltageY_powerdown
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What: /sys/bus/iio/devices/iio:deviceX/out_voltage_powerdown
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What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY_powerdown
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What: /sys/bus/iio/devices/iio:deviceX/out_altvoltage_powerdown
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KernelVersion: 2.6.38
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Contact: linux-iio@vger.kernel.org
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Description:
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@ -346,6 +359,24 @@ Description:
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normal operation. Y may be suppressed if all outputs are
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controlled together.
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What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY_frequency
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KernelVersion: 3.4.0
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Contact: linux-iio@vger.kernel.org
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Description:
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Output frequency for channel Y in Hz. The number must always be
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specified and unique if the output corresponds to a single
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channel.
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What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY_phase
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KernelVersion: 3.4.0
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Contact: linux-iio@vger.kernel.org
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Description:
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Phase in radians of one frequency/clock output Y
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(out_altvoltageY) relative to another frequency/clock output
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(out_altvoltageZ) of the device X. The number must always be
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specified and unique if the output corresponds to a single
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channel.
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What: /sys/bus/iio/devices/iio:deviceX/events
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KernelVersion: 2.6.35
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Contact: linux-iio@vger.kernel.org
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|
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@ -123,3 +123,54 @@ Description:
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half page, or a quarter page).
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In the case of ECC NOR, it is the ECC block size.
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What: /sys/class/mtd/mtdX/ecc_strength
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Date: April 2012
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KernelVersion: 3.4
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Contact: linux-mtd@lists.infradead.org
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Description:
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Maximum number of bit errors that the device is capable of
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correcting within each region covering an ecc step. This will
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always be a non-negative integer. Note that some devices will
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have multiple ecc steps within each writesize region.
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In the case of devices lacking any ECC capability, it is 0.
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What: /sys/class/mtd/mtdX/bitflip_threshold
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Date: April 2012
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KernelVersion: 3.4
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Contact: linux-mtd@lists.infradead.org
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Description:
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This allows the user to examine and adjust the criteria by which
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mtd returns -EUCLEAN from mtd_read(). If the maximum number of
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bit errors that were corrected on any single region comprising
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an ecc step (as reported by the driver) equals or exceeds this
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value, -EUCLEAN is returned. Otherwise, absent an error, 0 is
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returned. Higher layers (e.g., UBI) use this return code as an
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indication that an erase block may be degrading and should be
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scrutinized as a candidate for being marked as bad.
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The initial value may be specified by the flash device driver.
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If not, then the default value is ecc_strength.
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The introduction of this feature brings a subtle change to the
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meaning of the -EUCLEAN return code. Previously, it was
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interpreted to mean simply "one or more bit errors were
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corrected". Its new interpretation can be phrased as "a
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dangerously high number of bit errors were corrected on one or
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more regions comprising an ecc step". The precise definition of
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"dangerously high" can be adjusted by the user with
|
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bitflip_threshold. Users are discouraged from doing this,
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however, unless they know what they are doing and have intimate
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knowledge of the properties of their device. Broadly speaking,
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bitflip_threshold should be low enough to detect genuine erase
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block degradation, but high enough to avoid the consequences of
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a persistent return value of -EUCLEAN on devices where sticky
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bitflips occur. Note that if bitflip_threshold exceeds
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ecc_strength, -EUCLEAN is never returned by mtd_read().
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Conversely, if bitflip_threshold is zero, -EUCLEAN is always
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returned, absent a hard error.
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This is generally applicable only to NAND flash devices with ECC
|
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capability. It is ignored on devices lacking ECC capability;
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i.e., devices for which ecc_strength is zero.
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@ -671,8 +671,9 @@ ones already enabled by DEBUG.
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Chapter 14: Allocating memory
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The kernel provides the following general purpose memory allocators:
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kmalloc(), kzalloc(), kcalloc(), vmalloc(), and vzalloc(). Please refer to
|
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the API documentation for further information about them.
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kmalloc(), kzalloc(), kmalloc_array(), kcalloc(), vmalloc(), and
|
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vzalloc(). Please refer to the API documentation for further information
|
||||
about them.
|
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The preferred form for passing a size of a struct is the following:
|
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|
@ -686,6 +687,17 @@ Casting the return value which is a void pointer is redundant. The conversion
|
|||
from void pointer to any other pointer type is guaranteed by the C programming
|
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language.
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|
||||
The preferred form for allocating an array is the following:
|
||||
|
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p = kmalloc_array(n, sizeof(...), ...);
|
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|
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The preferred form for allocating a zeroed array is the following:
|
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p = kcalloc(n, sizeof(...), ...);
|
||||
|
||||
Both forms check for overflow on the allocation size n * sizeof(...),
|
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and return NULL if that occurred.
|
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Chapter 15: The inline disease
|
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|
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|
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|
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@ -1119,8 +1119,6 @@ in this page</entry>
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These constants are defined in nand.h. They are ored together to describe
|
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the chip functionality.
|
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<programlisting>
|
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/* Chip can not auto increment pages */
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#define NAND_NO_AUTOINCR 0x00000001
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/* Buswitdh is 16 bit */
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#define NAND_BUSWIDTH_16 0x00000002
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/* Device supports partial programming without padding */
|
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|
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@ -47,6 +47,51 @@ flexible way to enable non-common multi-display configuration. In addition to
|
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modelling the hardware overlays, omapdss supports virtual overlays and overlay
|
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managers. These can be used when updating a display with CPU or system DMA.
|
||||
|
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omapdss driver support for audio
|
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--------------------------------
|
||||
There exist several display technologies and standards that support audio as
|
||||
well. Hence, it is relevant to update the DSS device driver to provide an audio
|
||||
interface that may be used by an audio driver or any other driver interested in
|
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the functionality.
|
||||
|
||||
The audio_enable function is intended to prepare the relevant
|
||||
IP for playback (e.g., enabling an audio FIFO, taking in/out of reset
|
||||
some IP, enabling companion chips, etc). It is intended to be called before
|
||||
audio_start. The audio_disable function performs the reverse operation and is
|
||||
intended to be called after audio_stop.
|
||||
|
||||
While a given DSS device driver may support audio, it is possible that for
|
||||
certain configurations audio is not supported (e.g., an HDMI display using a
|
||||
VESA video timing). The audio_supported function is intended to query whether
|
||||
the current configuration of the display supports audio.
|
||||
|
||||
The audio_config function is intended to configure all the relevant audio
|
||||
parameters of the display. In order to make the function independent of any
|
||||
specific DSS device driver, a struct omap_dss_audio is defined. Its purpose
|
||||
is to contain all the required parameters for audio configuration. At the
|
||||
moment, such structure contains pointers to IEC-60958 channel status word
|
||||
and CEA-861 audio infoframe structures. This should be enough to support
|
||||
HDMI and DisplayPort, as both are based on CEA-861 and IEC-60958.
|
||||
|
||||
The audio_enable/disable, audio_config and audio_supported functions could be
|
||||
implemented as functions that may sleep. Hence, they should not be called
|
||||
while holding a spinlock or a readlock.
|
||||
|
||||
The audio_start/audio_stop function is intended to effectively start/stop audio
|
||||
playback after the configuration has taken place. These functions are designed
|
||||
to be used in an atomic context. Hence, audio_start should return quickly and be
|
||||
called only after all the needed resources for audio playback (audio FIFOs,
|
||||
DMA channels, companion chips, etc) have been enabled to begin data transfers.
|
||||
audio_stop is designed to only stop the audio transfers. The resources used
|
||||
for playback are released using audio_disable.
|
||||
|
||||
The enum omap_dss_audio_state may be used to help the implementations of
|
||||
the interface to keep track of the audio state. The initial state is _DISABLED;
|
||||
then, the state transitions to _CONFIGURED, and then, when it is ready to
|
||||
play audio, to _ENABLED. The state _PLAYING is used when the audio is being
|
||||
rendered.
|
||||
|
||||
|
||||
Panel and controller drivers
|
||||
----------------------------
|
||||
|
||||
|
|
@ -156,6 +201,7 @@ timings Display timings (pixclock,xres/hfp/hbp/hsw,yres/vfp/vbp/vsw)
|
|||
"pal" and "ntsc"
|
||||
panel_name
|
||||
tear_elim Tearing elimination 0=off, 1=on
|
||||
output_type Output type (video encoder only): "composite" or "svideo"
|
||||
|
||||
There are also some debugfs files at <debugfs>/omapdss/ which show information
|
||||
about clocks and registers.
|
||||
|
|
|
|||
|
|
@ -60,4 +60,4 @@ Introduction
|
|||
Document Author
|
||||
---------------
|
||||
|
||||
Viresh Kumar <viresh.kumar@st.com>, (c) 2010-2012 ST Microelectronics
|
||||
Viresh Kumar <viresh.linux@gmail.com>, (c) 2010-2012 ST Microelectronics
|
||||
|
|
|
|||
|
|
@ -287,6 +287,17 @@ iii) Messages
|
|||
the current transaction id is when you change it with this
|
||||
compare-and-swap message.
|
||||
|
||||
reserve_metadata_snap
|
||||
|
||||
Reserve a copy of the data mapping btree for use by userland.
|
||||
This allows userland to inspect the mappings as they were when
|
||||
this message was executed. Use the pool's status command to
|
||||
get the root block associated with the metadata snapshot.
|
||||
|
||||
release_metadata_snap
|
||||
|
||||
Release a previously reserved copy of the data mapping btree.
|
||||
|
||||
'thin' target
|
||||
-------------
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,93 @@
|
|||
Pinctrl-based I2C Bus Mux
|
||||
|
||||
This binding describes an I2C bus multiplexer that uses pin multiplexing to
|
||||
route the I2C signals, and represents the pin multiplexing configuration
|
||||
using the pinctrl device tree bindings.
|
||||
|
||||
+-----+ +-----+
|
||||
| dev | | dev |
|
||||
+------------------------+ +-----+ +-----+
|
||||
| SoC | | |
|
||||
| /----|------+--------+
|
||||
| +---+ +------+ | child bus A, on first set of pins
|
||||
| |I2C|---|Pinmux| |
|
||||
| +---+ +------+ | child bus B, on second set of pins
|
||||
| \----|------+--------+--------+
|
||||
| | | | |
|
||||
+------------------------+ +-----+ +-----+ +-----+
|
||||
| dev | | dev | | dev |
|
||||
+-----+ +-----+ +-----+
|
||||
|
||||
Required properties:
|
||||
- compatible: i2c-mux-pinctrl
|
||||
- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side
|
||||
port is connected to.
|
||||
|
||||
Also required are:
|
||||
|
||||
* Standard pinctrl properties that specify the pin mux state for each child
|
||||
bus. See ../pinctrl/pinctrl-bindings.txt.
|
||||
|
||||
* Standard I2C mux properties. See mux.txt in this directory.
|
||||
|
||||
* I2C child bus nodes. See mux.txt in this directory.
|
||||
|
||||
For each named state defined in the pinctrl-names property, an I2C child bus
|
||||
will be created. I2C child bus numbers are assigned based on the index into
|
||||
the pinctrl-names property.
|
||||
|
||||
The only exception is that no bus will be created for a state named "idle". If
|
||||
such a state is defined, it must be the last entry in pinctrl-names. For
|
||||
example:
|
||||
|
||||
pinctrl-names = "ddc", "pta", "idle" -> ddc = bus 0, pta = bus 1
|
||||
pinctrl-names = "ddc", "idle", "pta" -> Invalid ("idle" not last)
|
||||
pinctrl-names = "idle", "ddc", "pta" -> Invalid ("idle" not last)
|
||||
|
||||
Whenever an access is made to a device on a child bus, the relevant pinctrl
|
||||
state will be programmed into hardware.
|
||||
|
||||
If an idle state is defined, whenever an access is not being made to a device
|
||||
on a child bus, the idle pinctrl state will be programmed into hardware.
|
||||
|
||||
If an idle state is not defined, the most recently used pinctrl state will be
|
||||
left programmed into hardware whenever no access is being made of a device on
|
||||
a child bus.
|
||||
|
||||
Example:
|
||||
|
||||
i2cmux {
|
||||
compatible = "i2c-mux-pinctrl";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
i2c-parent = <&i2c1>;
|
||||
|
||||
pinctrl-names = "ddc", "pta", "idle";
|
||||
pinctrl-0 = <&state_i2cmux_ddc>;
|
||||
pinctrl-1 = <&state_i2cmux_pta>;
|
||||
pinctrl-2 = <&state_i2cmux_idle>;
|
||||
|
||||
i2c@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
eeprom {
|
||||
compatible = "eeprom";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
eeprom {
|
||||
compatible = "eeprom";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
* Freescale General-Purpose Media Interface (GPMI)
|
||||
|
||||
The GPMI nand controller provides an interface to control the
|
||||
NAND flash chips. We support only one NAND chip now.
|
||||
|
||||
Required properties:
|
||||
- compatible : should be "fsl,<chip>-gpmi-nand"
|
||||
- reg : should contain registers location and length for gpmi and bch.
|
||||
- reg-names: Should contain the reg names "gpmi-nand" and "bch"
|
||||
- interrupts : The first is the DMA interrupt number for GPMI.
|
||||
The second is the BCH interrupt number.
|
||||
- interrupt-names : The interrupt names "gpmi-dma", "bch";
|
||||
- fsl,gpmi-dma-channel : Should contain the dma channel it uses.
|
||||
|
||||
The device tree may optionally contain sub-nodes describing partitions of the
|
||||
address space. See partition.txt for more detail.
|
||||
|
||||
Examples:
|
||||
|
||||
gpmi-nand@8000c000 {
|
||||
compatible = "fsl,imx28-gpmi-nand";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x8000c000 2000>, <0x8000a000 2000>;
|
||||
reg-names = "gpmi-nand", "bch";
|
||||
interrupts = <88>, <41>;
|
||||
interrupt-names = "gpmi-dma", "bch";
|
||||
fsl,gpmi-dma-channel = <4>;
|
||||
|
||||
partition@0 {
|
||||
...
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
* Freescale's mxc_nand
|
||||
|
||||
Required properties:
|
||||
- compatible: "fsl,imxXX-nand"
|
||||
- reg: address range of the nfc block
|
||||
- interrupts: irq to be used
|
||||
- nand-bus-width: see nand.txt
|
||||
- nand-ecc-mode: see nand.txt
|
||||
- nand-on-flash-bbt: see nand.txt
|
||||
|
||||
Example:
|
||||
|
||||
nand@d8000000 {
|
||||
compatible = "fsl,imx27-nand";
|
||||
reg = <0xd8000000 0x1000>;
|
||||
interrupts = <29>;
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "hw";
|
||||
};
|
||||
|
|
@ -606,3 +606,9 @@ Why: There are two mci drivers: at91-mci and atmel-mci. The PDC support
|
|||
Who: Ludovic Desroches <ludovic.desroches@atmel.com>
|
||||
|
||||
----------------------------
|
||||
|
||||
What: net/wanrouter/
|
||||
When: June 2013
|
||||
Why: Unsupported/unmaintained/unused since 2.6
|
||||
|
||||
----------------------------
|
||||
|
|
|
|||
|
|
@ -61,6 +61,7 @@ ata *);
|
|||
ssize_t (*listxattr) (struct dentry *, char *, size_t);
|
||||
int (*removexattr) (struct dentry *, const char *);
|
||||
int (*fiemap)(struct inode *, struct fiemap_extent_info *, u64 start, u64 len);
|
||||
void (*update_time)(struct inode *, struct timespec *, int);
|
||||
|
||||
locking rules:
|
||||
all may block
|
||||
|
|
@ -87,6 +88,8 @@ getxattr: no
|
|||
listxattr: no
|
||||
removexattr: yes
|
||||
fiemap: no
|
||||
update_time: no
|
||||
|
||||
Additionally, ->rmdir(), ->unlink() and ->rename() have ->i_mutex on
|
||||
victim.
|
||||
cross-directory ->rename() has (per-superblock) ->s_vfs_rename_sem.
|
||||
|
|
|
|||
|
|
@ -40,6 +40,7 @@ Table of Contents
|
|||
3.4 /proc/<pid>/coredump_filter - Core dump filtering settings
|
||||
3.5 /proc/<pid>/mountinfo - Information about mounts
|
||||
3.6 /proc/<pid>/comm & /proc/<pid>/task/<tid>/comm
|
||||
3.7 /proc/<pid>/task/<tid>/children - Information about task children
|
||||
|
||||
4 Configuring procfs
|
||||
4.1 Mount options
|
||||
|
|
@ -310,6 +311,11 @@ Table 1-4: Contents of the stat files (as of 2.6.30-rc7)
|
|||
start_data address above which program data+bss is placed
|
||||
end_data address below which program data+bss is placed
|
||||
start_brk address above which program heap can be expanded with brk()
|
||||
arg_start address above which program command line is placed
|
||||
arg_end address below which program command line is placed
|
||||
env_start address above which program environment is placed
|
||||
env_end address below which program environment is placed
|
||||
exit_code the thread's exit_code in the form reported by the waitpid system call
|
||||
..............................................................................
|
||||
|
||||
The /proc/PID/maps file containing the currently mapped memory regions and
|
||||
|
|
@ -1578,6 +1584,23 @@ then the kernel's TASK_COMM_LEN (currently 16 chars) will result in a truncated
|
|||
comm value.
|
||||
|
||||
|
||||
3.7 /proc/<pid>/task/<tid>/children - Information about task children
|
||||
-------------------------------------------------------------------------
|
||||
This file provides a fast way to retrieve first level children pids
|
||||
of a task pointed by <pid>/<tid> pair. The format is a space separated
|
||||
stream of pids.
|
||||
|
||||
Note the "first level" here -- if a child has own children they will
|
||||
not be listed here, one needs to read /proc/<children-pid>/task/<tid>/children
|
||||
to obtain the descendants.
|
||||
|
||||
Since this interface is intended to be fast and cheap it doesn't
|
||||
guarantee to provide precise results and some children might be
|
||||
skipped, especially if they've exited right after we printed their
|
||||
pids, so one need to either stop or freeze processes being inspected
|
||||
if precise results are needed.
|
||||
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
Configuring procfs
|
||||
------------------------------------------------------------------------------
|
||||
|
|
|
|||
|
|
@ -363,6 +363,7 @@ struct inode_operations {
|
|||
ssize_t (*getxattr) (struct dentry *, const char *, void *, size_t);
|
||||
ssize_t (*listxattr) (struct dentry *, char *, size_t);
|
||||
int (*removexattr) (struct dentry *, const char *);
|
||||
void (*update_time)(struct inode *, struct timespec *, int);
|
||||
};
|
||||
|
||||
Again, all methods are called without any locks being held, unless
|
||||
|
|
@ -471,6 +472,9 @@ otherwise noted.
|
|||
removexattr: called by the VFS to remove an extended attribute from
|
||||
a file. This method is called by removexattr(2) system call.
|
||||
|
||||
update_time: called by the VFS to update a specific time or the i_version of
|
||||
an inode. If this is not defined the VFS will update the inode itself
|
||||
and call mark_inode_dirty_sync.
|
||||
|
||||
The Address Space Object
|
||||
========================
|
||||
|
|
|
|||
|
|
@ -6,7 +6,9 @@ Supported chips:
|
|||
Prefix: 'coretemp'
|
||||
CPUID: family 0x6, models 0xe (Pentium M DC), 0xf (Core 2 DC 65nm),
|
||||
0x16 (Core 2 SC 65nm), 0x17 (Penryn 45nm),
|
||||
0x1a (Nehalem), 0x1c (Atom), 0x1e (Lynnfield)
|
||||
0x1a (Nehalem), 0x1c (Atom), 0x1e (Lynnfield),
|
||||
0x26 (Tunnel Creek Atom), 0x27 (Medfield Atom),
|
||||
0x36 (Cedar Trail Atom)
|
||||
Datasheet: Intel 64 and IA-32 Architectures Software Developer's Manual
|
||||
Volume 3A: System Programming Guide
|
||||
http://softwarecommunity.intel.com/Wiki/Mobility/720.htm
|
||||
|
|
@ -52,6 +54,17 @@ Some information comes from ark.intel.com
|
|||
|
||||
Process Processor TjMax(C)
|
||||
|
||||
22nm Core i5/i7 Processors
|
||||
i7 3920XM, 3820QM, 3720QM, 3667U, 3520M 105
|
||||
i5 3427U, 3360M/3320M 105
|
||||
i7 3770/3770K 105
|
||||
i5 3570/3570K, 3550, 3470/3450 105
|
||||
i7 3770S 103
|
||||
i5 3570S/3550S, 3475S/3470S/3450S 103
|
||||
i7 3770T 94
|
||||
i5 3570T 94
|
||||
i5 3470T 91
|
||||
|
||||
32nm Core i3/i5/i7 Processors
|
||||
i7 660UM/640/620, 640LM/620, 620M, 610E 105
|
||||
i5 540UM/520/430, 540M/520/450/430 105
|
||||
|
|
@ -65,6 +78,11 @@ Process Processor TjMax(C)
|
|||
U3400 105
|
||||
P4505/P4500 90
|
||||
|
||||
32nm Atom Processors
|
||||
Z2460 90
|
||||
D2700/2550/2500 100
|
||||
N2850/2800/2650/2600 100
|
||||
|
||||
45nm Xeon Processors 5400 Quad-Core
|
||||
X5492, X5482, X5472, X5470, X5460, X5450 85
|
||||
E5472, E5462, E5450/40/30/20/10/05 85
|
||||
|
|
@ -85,6 +103,8 @@ Process Processor TjMax(C)
|
|||
N475/470/455/450 100
|
||||
N280/270 90
|
||||
330/230 125
|
||||
E680/660/640/620 90
|
||||
E680T/660T/640T/620T 110
|
||||
|
||||
45nm Core2 Processors
|
||||
Solo ULV SU3500/3300 100
|
||||
|
|
|
|||
|
|
@ -2543,6 +2543,15 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
|
|||
|
||||
sched_debug [KNL] Enables verbose scheduler debug messages.
|
||||
|
||||
skew_tick= [KNL] Offset the periodic timer tick per cpu to mitigate
|
||||
xtime_lock contention on larger systems, and/or RCU lock
|
||||
contention on all systems with CONFIG_MAXSMP set.
|
||||
Format: { "0" | "1" }
|
||||
0 -- disable. (may be 1 via CONFIG_CMDLINE="skew_tick=1"
|
||||
1 -- enable.
|
||||
Note: increases power consumption, thus should only be
|
||||
enabled if running jitter sensitive (HPC/RT) workloads.
|
||||
|
||||
security= [SECURITY] Choose a security module to enable at boot.
|
||||
If this boot parameter is not specified, only the first
|
||||
security module asking for security registration will be
|
||||
|
|
|
|||
|
|
@ -10,8 +10,8 @@ Currently this network device driver is for all STM embedded MAC/GMAC
|
|||
(i.e. 7xxx/5xxx SoCs), SPEAr (arm), Loongson1B (mips) and XLINX XC2V3000
|
||||
FF1152AMT0221 D1215994A VIRTEX FPGA board.
|
||||
|
||||
DWC Ether MAC 10/100/1000 Universal version 3.60a (and older) and DWC Ether MAC 10/100
|
||||
Universal version 4.0 have been used for developing this driver.
|
||||
DWC Ether MAC 10/100/1000 Universal version 3.60a (and older) and DWC Ether
|
||||
MAC 10/100 Universal version 4.0 have been used for developing this driver.
|
||||
|
||||
This driver supports both the platform bus and PCI.
|
||||
|
||||
|
|
@ -54,27 +54,27 @@ net_device structure enabling the scatter/gather feature.
|
|||
When one or more packets are received, an interrupt happens. The interrupts
|
||||
are not queued so the driver has to scan all the descriptors in the ring during
|
||||
the receive process.
|
||||
This is based on NAPI so the interrupt handler signals only if there is work to be
|
||||
done, and it exits.
|
||||
This is based on NAPI so the interrupt handler signals only if there is work
|
||||
to be done, and it exits.
|
||||
Then the poll method will be scheduled at some future point.
|
||||
The incoming packets are stored, by the DMA, in a list of pre-allocated socket
|
||||
buffers in order to avoid the memcpy (Zero-copy).
|
||||
|
||||
4.3) Timer-Driver Interrupt
|
||||
Instead of having the device that asynchronously notifies the frame receptions, the
|
||||
driver configures a timer to generate an interrupt at regular intervals.
|
||||
Based on the granularity of the timer, the frames that are received by the device
|
||||
will experience different levels of latency. Some NICs have dedicated timer
|
||||
device to perform this task. STMMAC can use either the RTC device or the TMU
|
||||
channel 2 on STLinux platforms.
|
||||
Instead of having the device that asynchronously notifies the frame receptions,
|
||||
the driver configures a timer to generate an interrupt at regular intervals.
|
||||
Based on the granularity of the timer, the frames that are received by the
|
||||
device will experience different levels of latency. Some NICs have dedicated
|
||||
timer device to perform this task. STMMAC can use either the RTC device or the
|
||||
TMU channel 2 on STLinux platforms.
|
||||
The timers frequency can be passed to the driver as parameter; when change it,
|
||||
take care of both hardware capability and network stability/performance impact.
|
||||
Several performance tests on STM platforms showed this optimisation allows to spare
|
||||
the CPU while having the maximum throughput.
|
||||
Several performance tests on STM platforms showed this optimisation allows to
|
||||
spare the CPU while having the maximum throughput.
|
||||
|
||||
4.4) WOL
|
||||
Wake up on Lan feature through Magic and Unicast frames are supported for the GMAC
|
||||
core.
|
||||
Wake up on Lan feature through Magic and Unicast frames are supported for the
|
||||
GMAC core.
|
||||
|
||||
4.5) DMA descriptors
|
||||
Driver handles both normal and enhanced descriptors. The latter has been only
|
||||
|
|
@ -106,7 +106,8 @@ Several driver's information can be passed through the platform
|
|||
These are included in the include/linux/stmmac.h header file
|
||||
and detailed below as well:
|
||||
|
||||
struct plat_stmmacenet_data {
|
||||
struct plat_stmmacenet_data {
|
||||
char *phy_bus_name;
|
||||
int bus_id;
|
||||
int phy_addr;
|
||||
int interface;
|
||||
|
|
@ -124,19 +125,24 @@ and detailed below as well:
|
|||
void (*bus_setup)(void __iomem *ioaddr);
|
||||
int (*init)(struct platform_device *pdev);
|
||||
void (*exit)(struct platform_device *pdev);
|
||||
void *custom_cfg;
|
||||
void *custom_data;
|
||||
void *bsp_priv;
|
||||
};
|
||||
|
||||
Where:
|
||||
o phy_bus_name: phy bus name to attach to the stmmac.
|
||||
o bus_id: bus identifier.
|
||||
o phy_addr: the physical address can be passed from the platform.
|
||||
If it is set to -1 the driver will automatically
|
||||
detect it at run-time by probing all the 32 addresses.
|
||||
o interface: PHY device's interface.
|
||||
o mdio_bus_data: specific platform fields for the MDIO bus.
|
||||
o pbl: the Programmable Burst Length is maximum number of beats to
|
||||
o dma_cfg: internal DMA parameters
|
||||
o pbl: the Programmable Burst Length is maximum number of beats to
|
||||
be transferred in one DMA transaction.
|
||||
GMAC also enables the 4xPBL by default.
|
||||
o fixed_burst/mixed_burst/burst_len
|
||||
o clk_csr: fixed CSR Clock range selection.
|
||||
o has_gmac: uses the GMAC core.
|
||||
o enh_desc: if sets the MAC will use the enhanced descriptor structure.
|
||||
|
|
@ -160,8 +166,9 @@ Where:
|
|||
this is sometime necessary on some platforms (e.g. ST boxes)
|
||||
where the HW needs to have set some PIO lines or system cfg
|
||||
registers.
|
||||
o custom_cfg: this is a custom configuration that can be passed while
|
||||
initialising the resources.
|
||||
o custom_cfg/custom_data: this is a custom configuration that can be passed
|
||||
while initialising the resources.
|
||||
o bsp_priv: another private poiter.
|
||||
|
||||
For MDIO bus The we have:
|
||||
|
||||
|
|
@ -180,7 +187,6 @@ Where:
|
|||
o irqs: list of IRQs, one per PHY.
|
||||
o probed_phy_irq: if irqs is NULL, use this for probed PHY.
|
||||
|
||||
|
||||
For DMA engine we have the following internal fields that should be
|
||||
tuned according to the HW capabilities.
|
||||
|
||||
|
|
|
|||
|
|
@ -44,6 +44,16 @@ Charger Manager supports the following:
|
|||
Normally, the platform will need to resume and suspend some devices
|
||||
that are used by Charger Manager.
|
||||
|
||||
* Support for premature full-battery event handling
|
||||
If the battery voltage drops by "fullbatt_vchkdrop_uV" after
|
||||
"fullbatt_vchkdrop_ms" from the full-battery event, the framework
|
||||
restarts charging. This check is also performed while suspended by
|
||||
setting wakeup time accordingly and using suspend_again.
|
||||
|
||||
* Support for uevent-notify
|
||||
With the charger-related events, the device sends
|
||||
notification to users with UEVENT.
|
||||
|
||||
2. Global Charger-Manager Data related with suspend_again
|
||||
========================================================
|
||||
In order to setup Charger Manager with suspend-again feature
|
||||
|
|
@ -55,7 +65,7 @@ if there are multiple batteries. If there are multiple batteries, the
|
|||
multiple instances of Charger Manager share the same charger_global_desc
|
||||
and it will manage in-suspend monitoring for all instances of Charger Manager.
|
||||
|
||||
The user needs to provide all the two entries properly in order to activate
|
||||
The user needs to provide all the three entries properly in order to activate
|
||||
in-suspend monitoring:
|
||||
|
||||
struct charger_global_desc {
|
||||
|
|
@ -74,6 +84,11 @@ bool (*rtc_only_wakeup)(void);
|
|||
same struct. If there is any other wakeup source triggered the
|
||||
wakeup, it should return false. If the "rtc" is the only wakeup
|
||||
reason, it should return true.
|
||||
|
||||
bool assume_timer_stops_in_suspend;
|
||||
: if true, Charger Manager assumes that
|
||||
the timer (CM uses jiffies as timer) stops during suspend. Then, CM
|
||||
assumes that the suspend-duration is same as the alarm length.
|
||||
};
|
||||
|
||||
3. How to setup suspend_again
|
||||
|
|
@ -111,6 +126,16 @@ enum polling_modes polling_mode;
|
|||
CM_POLL_CHARGING_ONLY: poll this battery if and only if the
|
||||
battery is being charged.
|
||||
|
||||
unsigned int fullbatt_vchkdrop_ms;
|
||||
unsigned int fullbatt_vchkdrop_uV;
|
||||
: If both have non-zero values, Charger Manager will check the
|
||||
battery voltage drop fullbatt_vchkdrop_ms after the battery is fully
|
||||
charged. If the voltage drop is over fullbatt_vchkdrop_uV, Charger
|
||||
Manager will try to recharge the battery by disabling and enabling
|
||||
chargers. Recharge with voltage drop condition only (without delay
|
||||
condition) is needed to be implemented with hardware interrupts from
|
||||
fuel gauges or charger devices/chips.
|
||||
|
||||
unsigned int fullbatt_uV;
|
||||
: If specified with a non-zero value, Charger Manager assumes
|
||||
that the battery is full (capacity = 100) if the battery is not being
|
||||
|
|
@ -122,6 +147,8 @@ unsigned int polling_interval_ms;
|
|||
this battery every polling_interval_ms or more frequently.
|
||||
|
||||
enum data_source battery_present;
|
||||
: CM_BATTERY_PRESENT: assume that the battery exists.
|
||||
CM_NO_BATTERY: assume that the battery does not exists.
|
||||
CM_FUEL_GAUGE: get battery presence information from fuel gauge.
|
||||
CM_CHARGER_STAT: get battery presence from chargers.
|
||||
|
||||
|
|
@ -151,7 +178,17 @@ bool measure_battery_temp;
|
|||
the value of measure_battery_temp.
|
||||
};
|
||||
|
||||
5. Other Considerations
|
||||
5. Notify Charger-Manager of charger events: cm_notify_event()
|
||||
=========================================================
|
||||
If there is an charger event is required to notify
|
||||
Charger Manager, a charger device driver that triggers the event can call
|
||||
cm_notify_event(psy, type, msg) to notify the corresponding Charger Manager.
|
||||
In the function, psy is the charger driver's power_supply pointer, which is
|
||||
associated with Charger-Manager. The parameter "type"
|
||||
is the same as irq's type (enum cm_event_types). The event message "msg" is
|
||||
optional and is effective only if the event type is "UNDESCRIBED" or "OTHERS".
|
||||
|
||||
6. Other Considerations
|
||||
=======================
|
||||
|
||||
At the charger/battery-related events such as battery-pulled-out,
|
||||
|
|
|
|||
|
|
@ -84,6 +84,8 @@ are already charged or discharging, 'n/a' can be displayed (or
|
|||
HEALTH - represents health of the battery, values corresponds to
|
||||
POWER_SUPPLY_HEALTH_*, defined in battery.h.
|
||||
|
||||
VOLTAGE_OCV - open circuit voltage of the battery.
|
||||
|
||||
VOLTAGE_MAX_DESIGN, VOLTAGE_MIN_DESIGN - design values for maximal and
|
||||
minimal power supply voltages. Maximal/minimal means values of voltages
|
||||
when battery considered "full"/"empty" at normal conditions. Yes, there is
|
||||
|
|
|
|||
|
|
@ -225,6 +225,13 @@ a queue must be less or equal then msg_max.
|
|||
maximum message size value (it is every message queue's attribute set during
|
||||
its creation).
|
||||
|
||||
/proc/sys/fs/mqueue/msg_default is a read/write file for setting/getting the
|
||||
default number of messages in a queue value if attr parameter of mq_open(2) is
|
||||
NULL. If it exceed msg_max, the default value is initialized msg_max.
|
||||
|
||||
/proc/sys/fs/mqueue/msgsize_default is a read/write file for setting/getting
|
||||
the default message size value if attr parameter of mq_open(2) is NULL. If it
|
||||
exceed msgsize_max, the default value is initialized msgsize_max.
|
||||
|
||||
4. /proc/sys/fs/epoll - Configuration options for the epoll interface
|
||||
--------------------------------------------------------
|
||||
|
|
|
|||
|
|
@ -0,0 +1,278 @@
|
|||
Frontswap provides a "transcendent memory" interface for swap pages.
|
||||
In some environments, dramatic performance savings may be obtained because
|
||||
swapped pages are saved in RAM (or a RAM-like device) instead of a swap disk.
|
||||
|
||||
(Note, frontswap -- and cleancache (merged at 3.0) -- are the "frontends"
|
||||
and the only necessary changes to the core kernel for transcendent memory;
|
||||
all other supporting code -- the "backends" -- is implemented as drivers.
|
||||
See the LWN.net article "Transcendent memory in a nutshell" for a detailed
|
||||
overview of frontswap and related kernel parts:
|
||||
https://lwn.net/Articles/454795/ )
|
||||
|
||||
Frontswap is so named because it can be thought of as the opposite of
|
||||
a "backing" store for a swap device. The storage is assumed to be
|
||||
a synchronous concurrency-safe page-oriented "pseudo-RAM device" conforming
|
||||
to the requirements of transcendent memory (such as Xen's "tmem", or
|
||||
in-kernel compressed memory, aka "zcache", or future RAM-like devices);
|
||||
this pseudo-RAM device is not directly accessible or addressable by the
|
||||
kernel and is of unknown and possibly time-varying size. The driver
|
||||
links itself to frontswap by calling frontswap_register_ops to set the
|
||||
frontswap_ops funcs appropriately and the functions it provides must
|
||||
conform to certain policies as follows:
|
||||
|
||||
An "init" prepares the device to receive frontswap pages associated
|
||||
with the specified swap device number (aka "type"). A "store" will
|
||||
copy the page to transcendent memory and associate it with the type and
|
||||
offset associated with the page. A "load" will copy the page, if found,
|
||||
from transcendent memory into kernel memory, but will NOT remove the page
|
||||
from from transcendent memory. An "invalidate_page" will remove the page
|
||||
from transcendent memory and an "invalidate_area" will remove ALL pages
|
||||
associated with the swap type (e.g., like swapoff) and notify the "device"
|
||||
to refuse further stores with that swap type.
|
||||
|
||||
Once a page is successfully stored, a matching load on the page will normally
|
||||
succeed. So when the kernel finds itself in a situation where it needs
|
||||
to swap out a page, it first attempts to use frontswap. If the store returns
|
||||
success, the data has been successfully saved to transcendent memory and
|
||||
a disk write and, if the data is later read back, a disk read are avoided.
|
||||
If a store returns failure, transcendent memory has rejected the data, and the
|
||||
page can be written to swap as usual.
|
||||
|
||||
If a backend chooses, frontswap can be configured as a "writethrough
|
||||
cache" by calling frontswap_writethrough(). In this mode, the reduction
|
||||
in swap device writes is lost (and also a non-trivial performance advantage)
|
||||
in order to allow the backend to arbitrarily "reclaim" space used to
|
||||
store frontswap pages to more completely manage its memory usage.
|
||||
|
||||
Note that if a page is stored and the page already exists in transcendent memory
|
||||
(a "duplicate" store), either the store succeeds and the data is overwritten,
|
||||
or the store fails AND the page is invalidated. This ensures stale data may
|
||||
never be obtained from frontswap.
|
||||
|
||||
If properly configured, monitoring of frontswap is done via debugfs in
|
||||
the /sys/kernel/debug/frontswap directory. The effectiveness of
|
||||
frontswap can be measured (across all swap devices) with:
|
||||
|
||||
failed_stores - how many store attempts have failed
|
||||
loads - how many loads were attempted (all should succeed)
|
||||
succ_stores - how many store attempts have succeeded
|
||||
invalidates - how many invalidates were attempted
|
||||
|
||||
A backend implementation may provide additional metrics.
|
||||
|
||||
FAQ
|
||||
|
||||
1) Where's the value?
|
||||
|
||||
When a workload starts swapping, performance falls through the floor.
|
||||
Frontswap significantly increases performance in many such workloads by
|
||||
providing a clean, dynamic interface to read and write swap pages to
|
||||
"transcendent memory" that is otherwise not directly addressable to the kernel.
|
||||
This interface is ideal when data is transformed to a different form
|
||||
and size (such as with compression) or secretly moved (as might be
|
||||
useful for write-balancing for some RAM-like devices). Swap pages (and
|
||||
evicted page-cache pages) are a great use for this kind of slower-than-RAM-
|
||||
but-much-faster-than-disk "pseudo-RAM device" and the frontswap (and
|
||||
cleancache) interface to transcendent memory provides a nice way to read
|
||||
and write -- and indirectly "name" -- the pages.
|
||||
|
||||
Frontswap -- and cleancache -- with a fairly small impact on the kernel,
|
||||
provides a huge amount of flexibility for more dynamic, flexible RAM
|
||||
utilization in various system configurations:
|
||||
|
||||
In the single kernel case, aka "zcache", pages are compressed and
|
||||
stored in local memory, thus increasing the total anonymous pages
|
||||
that can be safely kept in RAM. Zcache essentially trades off CPU
|
||||
cycles used in compression/decompression for better memory utilization.
|
||||
Benchmarks have shown little or no impact when memory pressure is
|
||||
low while providing a significant performance improvement (25%+)
|
||||
on some workloads under high memory pressure.
|
||||
|
||||
"RAMster" builds on zcache by adding "peer-to-peer" transcendent memory
|
||||
support for clustered systems. Frontswap pages are locally compressed
|
||||
as in zcache, but then "remotified" to another system's RAM. This
|
||||
allows RAM to be dynamically load-balanced back-and-forth as needed,
|
||||
i.e. when system A is overcommitted, it can swap to system B, and
|
||||
vice versa. RAMster can also be configured as a memory server so
|
||||
many servers in a cluster can swap, dynamically as needed, to a single
|
||||
server configured with a large amount of RAM... without pre-configuring
|
||||
how much of the RAM is available for each of the clients!
|
||||
|
||||
In the virtual case, the whole point of virtualization is to statistically
|
||||
multiplex physical resources acrosst the varying demands of multiple
|
||||
virtual machines. This is really hard to do with RAM and efforts to do
|
||||
it well with no kernel changes have essentially failed (except in some
|
||||
well-publicized special-case workloads).
|
||||
Specifically, the Xen Transcendent Memory backend allows otherwise
|
||||
"fallow" hypervisor-owned RAM to not only be "time-shared" between multiple
|
||||
virtual machines, but the pages can be compressed and deduplicated to
|
||||
optimize RAM utilization. And when guest OS's are induced to surrender
|
||||
underutilized RAM (e.g. with "selfballooning"), sudden unexpected
|
||||
memory pressure may result in swapping; frontswap allows those pages
|
||||
to be swapped to and from hypervisor RAM (if overall host system memory
|
||||
conditions allow), thus mitigating the potentially awful performance impact
|
||||
of unplanned swapping.
|
||||
|
||||
A KVM implementation is underway and has been RFC'ed to lkml. And,
|
||||
using frontswap, investigation is also underway on the use of NVM as
|
||||
a memory extension technology.
|
||||
|
||||
2) Sure there may be performance advantages in some situations, but
|
||||
what's the space/time overhead of frontswap?
|
||||
|
||||
If CONFIG_FRONTSWAP is disabled, every frontswap hook compiles into
|
||||
nothingness and the only overhead is a few extra bytes per swapon'ed
|
||||
swap device. If CONFIG_FRONTSWAP is enabled but no frontswap "backend"
|
||||
registers, there is one extra global variable compared to zero for
|
||||
every swap page read or written. If CONFIG_FRONTSWAP is enabled
|
||||
AND a frontswap backend registers AND the backend fails every "store"
|
||||
request (i.e. provides no memory despite claiming it might),
|
||||
CPU overhead is still negligible -- and since every frontswap fail
|
||||
precedes a swap page write-to-disk, the system is highly likely
|
||||
to be I/O bound and using a small fraction of a percent of a CPU
|
||||
will be irrelevant anyway.
|
||||
|
||||
As for space, if CONFIG_FRONTSWAP is enabled AND a frontswap backend
|
||||
registers, one bit is allocated for every swap page for every swap
|
||||
device that is swapon'd. This is added to the EIGHT bits (which
|
||||
was sixteen until about 2.6.34) that the kernel already allocates
|
||||
for every swap page for every swap device that is swapon'd. (Hugh
|
||||
Dickins has observed that frontswap could probably steal one of
|
||||
the existing eight bits, but let's worry about that minor optimization
|
||||
later.) For very large swap disks (which are rare) on a standard
|
||||
4K pagesize, this is 1MB per 32GB swap.
|
||||
|
||||
When swap pages are stored in transcendent memory instead of written
|
||||
out to disk, there is a side effect that this may create more memory
|
||||
pressure that can potentially outweigh the other advantages. A
|
||||
backend, such as zcache, must implement policies to carefully (but
|
||||
dynamically) manage memory limits to ensure this doesn't happen.
|
||||
|
||||
3) OK, how about a quick overview of what this frontswap patch does
|
||||
in terms that a kernel hacker can grok?
|
||||
|
||||
Let's assume that a frontswap "backend" has registered during
|
||||
kernel initialization; this registration indicates that this
|
||||
frontswap backend has access to some "memory" that is not directly
|
||||
accessible by the kernel. Exactly how much memory it provides is
|
||||
entirely dynamic and random.
|
||||
|
||||
Whenever a swap-device is swapon'd frontswap_init() is called,
|
||||
passing the swap device number (aka "type") as a parameter.
|
||||
This notifies frontswap to expect attempts to "store" swap pages
|
||||
associated with that number.
|
||||
|
||||
Whenever the swap subsystem is readying a page to write to a swap
|
||||
device (c.f swap_writepage()), frontswap_store is called. Frontswap
|
||||
consults with the frontswap backend and if the backend says it does NOT
|
||||
have room, frontswap_store returns -1 and the kernel swaps the page
|
||||
to the swap device as normal. Note that the response from the frontswap
|
||||
backend is unpredictable to the kernel; it may choose to never accept a
|
||||
page, it could accept every ninth page, or it might accept every
|
||||
page. But if the backend does accept a page, the data from the page
|
||||
has already been copied and associated with the type and offset,
|
||||
and the backend guarantees the persistence of the data. In this case,
|
||||
frontswap sets a bit in the "frontswap_map" for the swap device
|
||||
corresponding to the page offset on the swap device to which it would
|
||||
otherwise have written the data.
|
||||
|
||||
When the swap subsystem needs to swap-in a page (swap_readpage()),
|
||||
it first calls frontswap_load() which checks the frontswap_map to
|
||||
see if the page was earlier accepted by the frontswap backend. If
|
||||
it was, the page of data is filled from the frontswap backend and
|
||||
the swap-in is complete. If not, the normal swap-in code is
|
||||
executed to obtain the page of data from the real swap device.
|
||||
|
||||
So every time the frontswap backend accepts a page, a swap device read
|
||||
and (potentially) a swap device write are replaced by a "frontswap backend
|
||||
store" and (possibly) a "frontswap backend loads", which are presumably much
|
||||
faster.
|
||||
|
||||
4) Can't frontswap be configured as a "special" swap device that is
|
||||
just higher priority than any real swap device (e.g. like zswap,
|
||||
or maybe swap-over-nbd/NFS)?
|
||||
|
||||
No. First, the existing swap subsystem doesn't allow for any kind of
|
||||
swap hierarchy. Perhaps it could be rewritten to accomodate a hierarchy,
|
||||
but this would require fairly drastic changes. Even if it were
|
||||
rewritten, the existing swap subsystem uses the block I/O layer which
|
||||
assumes a swap device is fixed size and any page in it is linearly
|
||||
addressable. Frontswap barely touches the existing swap subsystem,
|
||||
and works around the constraints of the block I/O subsystem to provide
|
||||
a great deal of flexibility and dynamicity.
|
||||
|
||||
For example, the acceptance of any swap page by the frontswap backend is
|
||||
entirely unpredictable. This is critical to the definition of frontswap
|
||||
backends because it grants completely dynamic discretion to the
|
||||
backend. In zcache, one cannot know a priori how compressible a page is.
|
||||
"Poorly" compressible pages can be rejected, and "poorly" can itself be
|
||||
defined dynamically depending on current memory constraints.
|
||||
|
||||
Further, frontswap is entirely synchronous whereas a real swap
|
||||
device is, by definition, asynchronous and uses block I/O. The
|
||||
block I/O layer is not only unnecessary, but may perform "optimizations"
|
||||
that are inappropriate for a RAM-oriented device including delaying
|
||||
the write of some pages for a significant amount of time. Synchrony is
|
||||
required to ensure the dynamicity of the backend and to avoid thorny race
|
||||
conditions that would unnecessarily and greatly complicate frontswap
|
||||
and/or the block I/O subsystem. That said, only the initial "store"
|
||||
and "load" operations need be synchronous. A separate asynchronous thread
|
||||
is free to manipulate the pages stored by frontswap. For example,
|
||||
the "remotification" thread in RAMster uses standard asynchronous
|
||||
kernel sockets to move compressed frontswap pages to a remote machine.
|
||||
Similarly, a KVM guest-side implementation could do in-guest compression
|
||||
and use "batched" hypercalls.
|
||||
|
||||
In a virtualized environment, the dynamicity allows the hypervisor
|
||||
(or host OS) to do "intelligent overcommit". For example, it can
|
||||
choose to accept pages only until host-swapping might be imminent,
|
||||
then force guests to do their own swapping.
|
||||
|
||||
There is a downside to the transcendent memory specifications for
|
||||
frontswap: Since any "store" might fail, there must always be a real
|
||||
slot on a real swap device to swap the page. Thus frontswap must be
|
||||
implemented as a "shadow" to every swapon'd device with the potential
|
||||
capability of holding every page that the swap device might have held
|
||||
and the possibility that it might hold no pages at all. This means
|
||||
that frontswap cannot contain more pages than the total of swapon'd
|
||||
swap devices. For example, if NO swap device is configured on some
|
||||
installation, frontswap is useless. Swapless portable devices
|
||||
can still use frontswap but a backend for such devices must configure
|
||||
some kind of "ghost" swap device and ensure that it is never used.
|
||||
|
||||
5) Why this weird definition about "duplicate stores"? If a page
|
||||
has been previously successfully stored, can't it always be
|
||||
successfully overwritten?
|
||||
|
||||
Nearly always it can, but no, sometimes it cannot. Consider an example
|
||||
where data is compressed and the original 4K page has been compressed
|
||||
to 1K. Now an attempt is made to overwrite the page with data that
|
||||
is non-compressible and so would take the entire 4K. But the backend
|
||||
has no more space. In this case, the store must be rejected. Whenever
|
||||
frontswap rejects a store that would overwrite, it also must invalidate
|
||||
the old data and ensure that it is no longer accessible. Since the
|
||||
swap subsystem then writes the new data to the read swap device,
|
||||
this is the correct course of action to ensure coherency.
|
||||
|
||||
6) What is frontswap_shrink for?
|
||||
|
||||
When the (non-frontswap) swap subsystem swaps out a page to a real
|
||||
swap device, that page is only taking up low-value pre-allocated disk
|
||||
space. But if frontswap has placed a page in transcendent memory, that
|
||||
page may be taking up valuable real estate. The frontswap_shrink
|
||||
routine allows code outside of the swap subsystem to force pages out
|
||||
of the memory managed by frontswap and back into kernel-addressable memory.
|
||||
For example, in RAMster, a "suction driver" thread will attempt
|
||||
to "repatriate" pages sent to a remote machine back to the local machine;
|
||||
this is driven using the frontswap_shrink mechanism when memory pressure
|
||||
subsides.
|
||||
|
||||
7) Why does the frontswap patch create the new include file swapfile.h?
|
||||
|
||||
The frontswap code depends on some swap-subsystem-internal data
|
||||
structures that have, over the years, moved back and forth between
|
||||
static and global. This seemed a reasonable compromise: Define
|
||||
them as global but declare them in a new include file that isn't
|
||||
included by the large number of source files that include swap.h.
|
||||
|
||||
Dan Magenheimer, last updated April 9, 2012
|
||||
|
|
@ -16,7 +16,7 @@ There are three components to pagemap:
|
|||
* Bits 0-4 swap type if swapped
|
||||
* Bits 5-54 swap offset if swapped
|
||||
* Bits 55-60 page shift (page size = 1<<page shift)
|
||||
* Bit 61 reserved for future use
|
||||
* Bit 61 page is file-page or shared-anon
|
||||
* Bit 62 page swapped
|
||||
* Bit 63 page present
|
||||
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ data and perform operation on the slabs. By default slabinfo only lists
|
|||
slabs that have data in them. See "slabinfo -h" for more options when
|
||||
running the command. slabinfo can be compiled with
|
||||
|
||||
gcc -o slabinfo tools/slub/slabinfo.c
|
||||
gcc -o slabinfo tools/vm/slabinfo.c
|
||||
|
||||
Some of the modes of operation of slabinfo require that slub debugging
|
||||
be enabled on the command line. F.e. no tracking information will be
|
||||
|
|
|
|||
|
|
@ -0,0 +1,65 @@
|
|||
The EFI Boot Stub
|
||||
---------------------------
|
||||
|
||||
On the x86 platform, a bzImage can masquerade as a PE/COFF image,
|
||||
thereby convincing EFI firmware loaders to load it as an EFI
|
||||
executable. The code that modifies the bzImage header, along with the
|
||||
EFI-specific entry point that the firmware loader jumps to are
|
||||
collectively known as the "EFI boot stub", and live in
|
||||
arch/x86/boot/header.S and arch/x86/boot/compressed/eboot.c,
|
||||
respectively.
|
||||
|
||||
By using the EFI boot stub it's possible to boot a Linux kernel
|
||||
without the use of a conventional EFI boot loader, such as grub or
|
||||
elilo. Since the EFI boot stub performs the jobs of a boot loader, in
|
||||
a certain sense it *IS* the boot loader.
|
||||
|
||||
The EFI boot stub is enabled with the CONFIG_EFI_STUB kernel option.
|
||||
|
||||
|
||||
**** How to install bzImage.efi
|
||||
|
||||
The bzImage located in arch/x86/boot/bzImage must be copied to the EFI
|
||||
System Partiion (ESP) and renamed with the extension ".efi". Without
|
||||
the extension the EFI firmware loader will refuse to execute it. It's
|
||||
not possible to execute bzImage.efi from the usual Linux file systems
|
||||
because EFI firmware doesn't have support for them.
|
||||
|
||||
|
||||
**** Passing kernel parameters from the EFI shell
|
||||
|
||||
Arguments to the kernel can be passed after bzImage.efi, e.g.
|
||||
|
||||
fs0:> bzImage.efi console=ttyS0 root=/dev/sda4
|
||||
|
||||
|
||||
**** The "initrd=" option
|
||||
|
||||
Like most boot loaders, the EFI stub allows the user to specify
|
||||
multiple initrd files using the "initrd=" option. This is the only EFI
|
||||
stub-specific command line parameter, everything else is passed to the
|
||||
kernel when it boots.
|
||||
|
||||
The path to the initrd file must be an absolute path from the
|
||||
beginning of the ESP, relative path names do not work. Also, the path
|
||||
is an EFI-style path and directory elements must be separated with
|
||||
backslashes (\). For example, given the following directory layout,
|
||||
|
||||
fs0:>
|
||||
Kernels\
|
||||
bzImage.efi
|
||||
initrd-large.img
|
||||
|
||||
Ramdisks\
|
||||
initrd-small.img
|
||||
initrd-medium.img
|
||||
|
||||
to boot with the initrd-large.img file if the current working
|
||||
directory is fs0:\Kernels, the following command must be used,
|
||||
|
||||
fs0:\Kernels> bzImage.efi initrd=\Kernels\initrd-large.img
|
||||
|
||||
Notice how bzImage.efi can be specified with a relative path. That's
|
||||
because the image we're executing is interpreted by the EFI shell,
|
||||
which understands relative paths, whereas the rest of the command line
|
||||
is passed to bzImage.efi.
|
||||
90
MAINTAINERS
90
MAINTAINERS
|
|
@ -579,7 +579,7 @@ F: drivers/net/appletalk/
|
|||
F: net/appletalk/
|
||||
|
||||
ARASAN COMPACT FLASH PATA CONTROLLER
|
||||
M: Viresh Kumar <viresh.kumar@st.com>
|
||||
M: Viresh Kumar <viresh.linux@gmail.com>
|
||||
L: linux-ide@vger.kernel.org
|
||||
S: Maintained
|
||||
F: include/linux/pata_arasan_cf_data.h
|
||||
|
|
@ -1077,7 +1077,7 @@ F: drivers/media/video/s5p-fimc/
|
|||
ARM/SAMSUNG S5P SERIES Multi Format Codec (MFC) SUPPORT
|
||||
M: Kyungmin Park <kyungmin.park@samsung.com>
|
||||
M: Kamil Debski <k.debski@samsung.com>
|
||||
M: Jeongtae Park <jtp.park@samsung.com>
|
||||
M: Jeongtae Park <jtp.park@samsung.com>
|
||||
L: linux-arm-kernel@lists.infradead.org
|
||||
L: linux-media@vger.kernel.org
|
||||
S: Maintained
|
||||
|
|
@ -1646,11 +1646,11 @@ S: Maintained
|
|||
F: drivers/gpio/gpio-bt8xx.c
|
||||
|
||||
BTRFS FILE SYSTEM
|
||||
M: Chris Mason <chris.mason@oracle.com>
|
||||
M: Chris Mason <chris.mason@fusionio.com>
|
||||
L: linux-btrfs@vger.kernel.org
|
||||
W: http://btrfs.wiki.kernel.org/
|
||||
Q: http://patchwork.kernel.org/project/linux-btrfs/list/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/mason/btrfs-unstable.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/mason/linux-btrfs.git
|
||||
S: Maintained
|
||||
F: Documentation/filesystems/btrfs.txt
|
||||
F: fs/btrfs/
|
||||
|
|
@ -1743,10 +1743,10 @@ F: include/linux/can/platform/
|
|||
CAPABILITIES
|
||||
M: Serge Hallyn <serge.hallyn@canonical.com>
|
||||
L: linux-security-module@vger.kernel.org
|
||||
S: Supported
|
||||
S: Supported
|
||||
F: include/linux/capability.h
|
||||
F: security/capability.c
|
||||
F: security/commoncap.c
|
||||
F: security/commoncap.c
|
||||
F: kernel/capability.c
|
||||
|
||||
CELL BROADBAND ENGINE ARCHITECTURE
|
||||
|
|
@ -1800,6 +1800,9 @@ F: include/linux/cfag12864b.h
|
|||
CFG80211 and NL80211
|
||||
M: Johannes Berg <johannes@sipsolutions.net>
|
||||
L: linux-wireless@vger.kernel.org
|
||||
W: http://wireless.kernel.org/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211-next.git
|
||||
S: Maintained
|
||||
F: include/linux/nl80211.h
|
||||
F: include/net/cfg80211.h
|
||||
|
|
@ -2146,11 +2149,11 @@ S: Orphan
|
|||
F: drivers/net/wan/pc300*
|
||||
|
||||
CYTTSP TOUCHSCREEN DRIVER
|
||||
M: Javier Martinez Canillas <javier@dowhile0.org>
|
||||
L: linux-input@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/input/touchscreen/cyttsp*
|
||||
F: include/linux/input/cyttsp.h
|
||||
M: Javier Martinez Canillas <javier@dowhile0.org>
|
||||
L: linux-input@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/input/touchscreen/cyttsp*
|
||||
F: include/linux/input/cyttsp.h
|
||||
|
||||
DAMA SLAVE for AX.25
|
||||
M: Joerg Reuter <jreuter@yaina.de>
|
||||
|
|
@ -2270,7 +2273,7 @@ F: include/linux/device-mapper.h
|
|||
F: include/linux/dm-*.h
|
||||
|
||||
DIOLAN U2C-12 I2C DRIVER
|
||||
M: Guenter Roeck <guenter.roeck@ericsson.com>
|
||||
M: Guenter Roeck <linux@roeck-us.net>
|
||||
L: linux-i2c@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/i2c/busses/i2c-diolan-u2c.c
|
||||
|
|
@ -2930,6 +2933,13 @@ F: Documentation/power/freezing-of-tasks.txt
|
|||
F: include/linux/freezer.h
|
||||
F: kernel/freezer.c
|
||||
|
||||
FRONTSWAP API
|
||||
M: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
|
||||
L: linux-kernel@vger.kernel.org
|
||||
S: Maintained
|
||||
F: mm/frontswap.c
|
||||
F: include/linux/frontswap.h
|
||||
|
||||
FS-CACHE: LOCAL CACHING FOR NETWORK FILESYSTEMS
|
||||
M: David Howells <dhowells@redhat.com>
|
||||
L: linux-cachefs@redhat.com
|
||||
|
|
@ -3138,7 +3148,7 @@ F: drivers/tty/hvc/
|
|||
|
||||
HARDWARE MONITORING
|
||||
M: Jean Delvare <khali@linux-fr.org>
|
||||
M: Guenter Roeck <guenter.roeck@ericsson.com>
|
||||
M: Guenter Roeck <linux@roeck-us.net>
|
||||
L: lm-sensors@lm-sensors.org
|
||||
W: http://www.lm-sensors.org/
|
||||
T: quilt kernel.org/pub/linux/kernel/people/jdelvare/linux-2.6/jdelvare-hwmon/
|
||||
|
|
@ -4096,6 +4106,8 @@ F: drivers/scsi/53c700*
|
|||
LED SUBSYSTEM
|
||||
M: Bryan Wu <bryan.wu@canonical.com>
|
||||
M: Richard Purdie <rpurdie@rpsys.net>
|
||||
L: linux-leds@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/linux-leds.git
|
||||
S: Maintained
|
||||
F: drivers/leds/
|
||||
F: include/linux/leds.h
|
||||
|
|
@ -4340,7 +4352,8 @@ MAC80211
|
|||
M: Johannes Berg <johannes@sipsolutions.net>
|
||||
L: linux-wireless@vger.kernel.org
|
||||
W: http://linuxwireless.org/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211-next.git
|
||||
S: Maintained
|
||||
F: Documentation/networking/mac80211-injection.txt
|
||||
F: include/net/mac80211.h
|
||||
|
|
@ -4351,7 +4364,8 @@ M: Stefano Brivio <stefano.brivio@polimi.it>
|
|||
M: Mattias Nissler <mattias.nissler@gmx.de>
|
||||
L: linux-wireless@vger.kernel.org
|
||||
W: http://linuxwireless.org/en/developers/Documentation/mac80211/RateControl/PID
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211-next.git
|
||||
S: Maintained
|
||||
F: net/mac80211/rc80211_pid*
|
||||
|
||||
|
|
@ -4411,6 +4425,13 @@ S: Orphan
|
|||
F: drivers/video/matrox/matroxfb_*
|
||||
F: include/linux/matroxfb.h
|
||||
|
||||
MAX16065 HARDWARE MONITOR DRIVER
|
||||
M: Guenter Roeck <linux@roeck-us.net>
|
||||
L: lm-sensors@lm-sensors.org
|
||||
S: Maintained
|
||||
F: Documentation/hwmon/max16065
|
||||
F: drivers/hwmon/max16065.c
|
||||
|
||||
MAX6650 HARDWARE MONITOR AND FAN CONTROLLER DRIVER
|
||||
M: "Hans J. Koch" <hjk@hansjkoch.de>
|
||||
L: lm-sensors@lm-sensors.org
|
||||
|
|
@ -5149,7 +5170,7 @@ F: drivers/leds/leds-pca9532.c
|
|||
F: include/linux/leds-pca9532.h
|
||||
|
||||
PCA9541 I2C BUS MASTER SELECTOR DRIVER
|
||||
M: Guenter Roeck <guenter.roeck@ericsson.com>
|
||||
M: Guenter Roeck <linux@roeck-us.net>
|
||||
L: linux-i2c@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/i2c/muxes/i2c-mux-pca9541.c
|
||||
|
|
@ -5169,7 +5190,7 @@ S: Maintained
|
|||
F: drivers/firmware/pcdp.*
|
||||
|
||||
PCI ERROR RECOVERY
|
||||
M: Linas Vepstas <linasvepstas@gmail.com>
|
||||
M: Linas Vepstas <linasvepstas@gmail.com>
|
||||
L: linux-pci@vger.kernel.org
|
||||
S: Supported
|
||||
F: Documentation/PCI/pci-error-recovery.txt
|
||||
|
|
@ -5275,7 +5296,7 @@ S: Maintained
|
|||
F: drivers/pinctrl/
|
||||
|
||||
PIN CONTROLLER - ST SPEAR
|
||||
M: Viresh Kumar <viresh.kumar@st.com>
|
||||
M: Viresh Kumar <viresh.linux@gmail.com>
|
||||
L: spear-devel@list.st.com
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
W: http://www.st.com/spear
|
||||
|
|
@ -5299,7 +5320,7 @@ F: drivers/video/fb-puv3.c
|
|||
F: drivers/rtc/rtc-puv3.c
|
||||
|
||||
PMBUS HARDWARE MONITORING DRIVERS
|
||||
M: Guenter Roeck <guenter.roeck@ericsson.com>
|
||||
M: Guenter Roeck <linux@roeck-us.net>
|
||||
L: lm-sensors@lm-sensors.org
|
||||
W: http://www.lm-sensors.org/
|
||||
W: http://www.roeck-us.net/linux/drivers/
|
||||
|
|
@ -5337,7 +5358,7 @@ M: David Woodhouse <dwmw2@infradead.org>
|
|||
T: git git://git.infradead.org/battery-2.6.git
|
||||
S: Maintained
|
||||
F: include/linux/power_supply.h
|
||||
F: drivers/power/power_supply*
|
||||
F: drivers/power/
|
||||
|
||||
PNP SUPPORT
|
||||
M: Adam Belay <abelay@mit.edu>
|
||||
|
|
@ -5695,6 +5716,9 @@ F: include/linux/remoteproc.h
|
|||
RFKILL
|
||||
M: Johannes Berg <johannes@sipsolutions.net>
|
||||
L: linux-wireless@vger.kernel.org
|
||||
W: http://wireless.kernel.org/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211-next.git
|
||||
S: Maintained
|
||||
F: Documentation/rfkill.txt
|
||||
F: net/rfkill/
|
||||
|
|
@ -5849,7 +5873,7 @@ S: Maintained
|
|||
F: drivers/tty/serial
|
||||
|
||||
SYNOPSYS DESIGNWARE DMAC DRIVER
|
||||
M: Viresh Kumar <viresh.kumar@st.com>
|
||||
M: Viresh Kumar <viresh.linux@gmail.com>
|
||||
S: Maintained
|
||||
F: include/linux/dw_dmac.h
|
||||
F: drivers/dma/dw_dmac_regs.h
|
||||
|
|
@ -5997,7 +6021,7 @@ S: Maintained
|
|||
F: drivers/mmc/host/sdhci-s3c.c
|
||||
|
||||
SECURE DIGITAL HOST CONTROLLER INTERFACE (SDHCI) ST SPEAR DRIVER
|
||||
M: Viresh Kumar <viresh.kumar@st.com>
|
||||
M: Viresh Kumar <viresh.linux@gmail.com>
|
||||
L: spear-devel@list.st.com
|
||||
L: linux-mmc@vger.kernel.org
|
||||
S: Maintained
|
||||
|
|
@ -6353,7 +6377,7 @@ S: Maintained
|
|||
F: include/linux/compiler.h
|
||||
|
||||
SPEAR PLATFORM SUPPORT
|
||||
M: Viresh Kumar <viresh.kumar@st.com>
|
||||
M: Viresh Kumar <viresh.linux@gmail.com>
|
||||
M: Shiraz Hashim <shiraz.hashim@st.com>
|
||||
L: spear-devel@list.st.com
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
|
|
@ -6362,7 +6386,7 @@ S: Maintained
|
|||
F: arch/arm/plat-spear/
|
||||
|
||||
SPEAR13XX MACHINE SUPPORT
|
||||
M: Viresh Kumar <viresh.kumar@st.com>
|
||||
M: Viresh Kumar <viresh.linux@gmail.com>
|
||||
M: Shiraz Hashim <shiraz.hashim@st.com>
|
||||
L: spear-devel@list.st.com
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
|
|
@ -6371,7 +6395,7 @@ S: Maintained
|
|||
F: arch/arm/mach-spear13xx/
|
||||
|
||||
SPEAR3XX MACHINE SUPPORT
|
||||
M: Viresh Kumar <viresh.kumar@st.com>
|
||||
M: Viresh Kumar <viresh.linux@gmail.com>
|
||||
M: Shiraz Hashim <shiraz.hashim@st.com>
|
||||
L: spear-devel@list.st.com
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
|
|
@ -6382,7 +6406,7 @@ F: arch/arm/mach-spear3xx/
|
|||
SPEAR6XX MACHINE SUPPORT
|
||||
M: Rajeev Kumar <rajeev-dlh.kumar@st.com>
|
||||
M: Shiraz Hashim <shiraz.hashim@st.com>
|
||||
M: Viresh Kumar <viresh.kumar@st.com>
|
||||
M: Viresh Kumar <viresh.linux@gmail.com>
|
||||
L: spear-devel@list.st.com
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
W: http://www.st.com/spear
|
||||
|
|
@ -6390,7 +6414,7 @@ S: Maintained
|
|||
F: arch/arm/mach-spear6xx/
|
||||
|
||||
SPEAR CLOCK FRAMEWORK SUPPORT
|
||||
M: Viresh Kumar <viresh.kumar@st.com>
|
||||
M: Viresh Kumar <viresh.linux@gmail.com>
|
||||
L: spear-devel@list.st.com
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
W: http://www.st.com/spear
|
||||
|
|
@ -6657,7 +6681,7 @@ F: include/linux/taskstats*
|
|||
F: kernel/taskstats.c
|
||||
|
||||
TC CLASSIFIER
|
||||
M: Jamal Hadi Salim <hadi@cyberus.ca>
|
||||
M: Jamal Hadi Salim <jhs@mojatatu.com>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Maintained
|
||||
F: include/linux/pkt_cls.h
|
||||
|
|
@ -7291,11 +7315,11 @@ F: Documentation/DocBook/uio-howto.tmpl
|
|||
F: drivers/uio/
|
||||
F: include/linux/uio*.h
|
||||
|
||||
UTIL-LINUX-NG PACKAGE
|
||||
UTIL-LINUX PACKAGE
|
||||
M: Karel Zak <kzak@redhat.com>
|
||||
L: util-linux-ng@vger.kernel.org
|
||||
W: http://kernel.org/~kzak/util-linux-ng/
|
||||
T: git git://git.kernel.org/pub/scm/utils/util-linux-ng/util-linux-ng.git
|
||||
L: util-linux@vger.kernel.org
|
||||
W: http://en.wikipedia.org/wiki/Util-linux
|
||||
T: git git://git.kernel.org/pub/scm/utils/util-linux/util-linux.git
|
||||
S: Maintained
|
||||
|
||||
UVESAFB DRIVER
|
||||
|
|
@ -7397,7 +7421,7 @@ F: include/linux/vlynq.h
|
|||
|
||||
VME SUBSYSTEM
|
||||
M: Martyn Welch <martyn.welch@ge.com>
|
||||
M: Manohar Vanga <manohar.vanga@cern.ch>
|
||||
M: Manohar Vanga <manohar.vanga@gmail.com>
|
||||
M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
||||
L: devel@driverdev.osuosl.org
|
||||
S: Maintained
|
||||
|
|
|
|||
8
Makefile
8
Makefile
|
|
@ -1,7 +1,7 @@
|
|||
VERSION = 3
|
||||
PATCHLEVEL = 4
|
||||
PATCHLEVEL = 5
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION =
|
||||
EXTRAVERSION = -rc4
|
||||
NAME = Saber-toothed Squirrel
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
@ -561,6 +561,8 @@ else
|
|||
KBUILD_CFLAGS += -O2
|
||||
endif
|
||||
|
||||
include $(srctree)/arch/$(SRCARCH)/Makefile
|
||||
|
||||
ifdef CONFIG_READABLE_ASM
|
||||
# Disable optimizations that make assembler listings hard to read.
|
||||
# reorder blocks reorders the control in the function
|
||||
|
|
@ -571,8 +573,6 @@ KBUILD_CFLAGS += $(call cc-option,-fno-reorder-blocks,) \
|
|||
$(call cc-option,-fno-partial-inlining)
|
||||
endif
|
||||
|
||||
include $(srctree)/arch/$(SRCARCH)/Makefile
|
||||
|
||||
ifneq ($(CONFIG_FRAME_WARN),0)
|
||||
KBUILD_CFLAGS += $(call cc-option,-Wframe-larger-than=${CONFIG_FRAME_WARN})
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -10,9 +10,6 @@
|
|||
typedef unsigned int __kernel_ino_t;
|
||||
#define __kernel_ino_t __kernel_ino_t
|
||||
|
||||
typedef unsigned int __kernel_nlink_t;
|
||||
#define __kernel_nlink_t __kernel_nlink_t
|
||||
|
||||
typedef unsigned long __kernel_sigset_t; /* at least 32 bits */
|
||||
|
||||
#include <asm-generic/posix_types.h>
|
||||
|
|
|
|||
|
|
@ -226,7 +226,6 @@ do_sigreturn(struct sigcontext __user *sc, struct pt_regs *regs,
|
|||
if (__get_user(set.sig[0], &sc->sc_mask))
|
||||
goto give_sigsegv;
|
||||
|
||||
sigdelsetmask(&set, ~_BLOCKABLE);
|
||||
set_current_blocked(&set);
|
||||
|
||||
if (restore_sigcontext(sc, regs, sw))
|
||||
|
|
@ -261,7 +260,6 @@ do_rt_sigreturn(struct rt_sigframe __user *frame, struct pt_regs *regs,
|
|||
if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
|
||||
goto give_sigsegv;
|
||||
|
||||
sigdelsetmask(&set, ~_BLOCKABLE);
|
||||
set_current_blocked(&set);
|
||||
|
||||
if (restore_sigcontext(&frame->uc.uc_mcontext, regs, sw))
|
||||
|
|
@ -468,12 +466,9 @@ static inline void
|
|||
handle_signal(int sig, struct k_sigaction *ka, siginfo_t *info,
|
||||
struct pt_regs * regs, struct switch_stack *sw)
|
||||
{
|
||||
sigset_t *oldset = ¤t->blocked;
|
||||
sigset_t *oldset = sigmask_to_save();
|
||||
int ret;
|
||||
|
||||
if (test_thread_flag(TIF_RESTORE_SIGMASK))
|
||||
oldset = ¤t->saved_sigmask;
|
||||
|
||||
if (ka->sa.sa_flags & SA_SIGINFO)
|
||||
ret = setup_rt_frame(sig, ka, info, oldset, regs, sw);
|
||||
else
|
||||
|
|
@ -483,12 +478,7 @@ handle_signal(int sig, struct k_sigaction *ka, siginfo_t *info,
|
|||
force_sigsegv(sig, current);
|
||||
return;
|
||||
}
|
||||
block_sigmask(ka, sig);
|
||||
/* A signal was successfully delivered, and the
|
||||
saved sigmask was stored on the signal frame,
|
||||
and will be restored by sigreturn. So we can
|
||||
simply clear the restore sigmask flag. */
|
||||
clear_thread_flag(TIF_RESTORE_SIGMASK);
|
||||
signal_delivered(sig, info, ka, regs, 0);
|
||||
}
|
||||
|
||||
static inline void
|
||||
|
|
@ -572,9 +562,7 @@ do_signal(struct pt_regs * regs, struct switch_stack * sw,
|
|||
}
|
||||
|
||||
/* If there's no signal to deliver, we just restore the saved mask. */
|
||||
if (test_and_clear_thread_flag(TIF_RESTORE_SIGMASK))
|
||||
set_current_blocked(¤t->saved_sigmask);
|
||||
|
||||
restore_saved_sigmask();
|
||||
if (single_stepping)
|
||||
ptrace_set_bpt(current); /* re-set breakpoint */
|
||||
}
|
||||
|
|
@ -590,7 +578,5 @@ do_notify_resume(struct pt_regs *regs, struct switch_stack *sw,
|
|||
if (thread_info_flags & _TIF_NOTIFY_RESUME) {
|
||||
clear_thread_flag(TIF_NOTIFY_RESUME);
|
||||
tracehook_notify_resume(regs);
|
||||
if (current->replacement_session_keyring)
|
||||
key_replace_session_keyring();
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -7,7 +7,6 @@ config ARM
|
|||
select HAVE_IDE if PCI || ISA || PCMCIA
|
||||
select HAVE_DMA_ATTRS
|
||||
select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
|
||||
select CMA if (CPU_V6 || CPU_V6K || CPU_V7)
|
||||
select HAVE_MEMBLOCK
|
||||
select RTC_LIB
|
||||
select SYS_SUPPORTS_APM_EMULATION
|
||||
|
|
@ -294,6 +293,7 @@ config ARCH_VERSATILE
|
|||
select ICST
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select ARCH_WANT_OPTIONAL_GPIOLIB
|
||||
select NEED_MACH_IO_H if PCI
|
||||
select PLAT_VERSATILE
|
||||
select PLAT_VERSATILE_CLCD
|
||||
select PLAT_VERSATILE_FPGA_IRQ
|
||||
|
|
@ -525,7 +525,7 @@ config ARCH_IXP4XX
|
|||
select ARCH_HAS_DMA_SET_COHERENT_MASK
|
||||
select CLKSRC_MMIO
|
||||
select CPU_XSCALE
|
||||
select GENERIC_GPIO
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select MIGHT_HAVE_PCI
|
||||
select NEED_MACH_IO_H
|
||||
|
|
@ -589,6 +589,7 @@ config ARCH_ORION5X
|
|||
select PCI
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select NEED_MACH_IO_H
|
||||
select PLAT_ORION
|
||||
help
|
||||
Support for the following Marvell Orion 5x series SoCs:
|
||||
|
|
|
|||
|
|
@ -58,6 +58,8 @@
|
|||
"st,nomadik-gpio";
|
||||
reg = <0x8012e000 0x80>;
|
||||
interrupts = <0 119 0x4>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
supports-sleepmode;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
|
@ -69,6 +71,8 @@
|
|||
"st,nomadik-gpio";
|
||||
reg = <0x8012e080 0x80>;
|
||||
interrupts = <0 120 0x4>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
supports-sleepmode;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
|
@ -80,6 +84,8 @@
|
|||
"st,nomadik-gpio";
|
||||
reg = <0x8000e000 0x80>;
|
||||
interrupts = <0 121 0x4>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
supports-sleepmode;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
|
@ -91,6 +97,8 @@
|
|||
"st,nomadik-gpio";
|
||||
reg = <0x8000e080 0x80>;
|
||||
interrupts = <0 122 0x4>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
supports-sleepmode;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
|
@ -102,6 +110,8 @@
|
|||
"st,nomadik-gpio";
|
||||
reg = <0x8000e100 0x80>;
|
||||
interrupts = <0 123 0x4>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
supports-sleepmode;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
|
@ -113,6 +123,8 @@
|
|||
"st,nomadik-gpio";
|
||||
reg = <0x8000e180 0x80>;
|
||||
interrupts = <0 124 0x4>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
supports-sleepmode;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
|
@ -124,6 +136,8 @@
|
|||
"st,nomadik-gpio";
|
||||
reg = <0x8011e000 0x80>;
|
||||
interrupts = <0 125 0x4>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
supports-sleepmode;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
|
@ -135,6 +149,8 @@
|
|||
"st,nomadik-gpio";
|
||||
reg = <0x8011e080 0x80>;
|
||||
interrupts = <0 126 0x4>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
supports-sleepmode;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
|
@ -146,12 +162,18 @@
|
|||
"st,nomadik-gpio";
|
||||
reg = <0xa03fe000 0x80>;
|
||||
interrupts = <0 127 0x4>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
supports-sleepmode;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-bank = <8>;
|
||||
};
|
||||
|
||||
pinctrl {
|
||||
compatible = "stericsson,nmk_pinctrl";
|
||||
};
|
||||
|
||||
usb@a03e0000 {
|
||||
compatible = "stericsson,db8500-musb",
|
||||
"mentor,musb";
|
||||
|
|
@ -169,20 +191,195 @@
|
|||
prcmu@80157000 {
|
||||
compatible = "stericsson,db8500-prcmu";
|
||||
reg = <0x80157000 0x1000>;
|
||||
interrupts = <46 47>;
|
||||
interrupts = <0 47 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
prcmu-timer-4@80157450 {
|
||||
prcmu-timer-4@80157450 {
|
||||
compatible = "stericsson,db8500-prcmu-timer-4";
|
||||
reg = <0x80157450 0xC>;
|
||||
};
|
||||
|
||||
db8500-prcmu-regulators {
|
||||
compatible = "stericsson,db8500-prcmu-regulator";
|
||||
|
||||
// DB8500_REGULATOR_VAPE
|
||||
db8500_vape_reg: db8500_vape {
|
||||
regulator-name = "db8500-vape";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
// DB8500_REGULATOR_VARM
|
||||
db8500_varm_reg: db8500_varm {
|
||||
regulator-name = "db8500-varm";
|
||||
};
|
||||
|
||||
// DB8500_REGULATOR_VMODEM
|
||||
db8500_vmodem_reg: db8500_vmodem {
|
||||
regulator-name = "db8500-vmodem";
|
||||
};
|
||||
|
||||
// DB8500_REGULATOR_VPLL
|
||||
db8500_vpll_reg: db8500_vpll {
|
||||
regulator-name = "db8500-vpll";
|
||||
};
|
||||
|
||||
// DB8500_REGULATOR_VSMPS1
|
||||
db8500_vsmps1_reg: db8500_vsmps1 {
|
||||
regulator-name = "db8500-vsmps1";
|
||||
};
|
||||
|
||||
// DB8500_REGULATOR_VSMPS2
|
||||
db8500_vsmps2_reg: db8500_vsmps2 {
|
||||
regulator-name = "db8500-vsmps2";
|
||||
};
|
||||
|
||||
// DB8500_REGULATOR_VSMPS3
|
||||
db8500_vsmps3_reg: db8500_vsmps3 {
|
||||
regulator-name = "db8500-vsmps3";
|
||||
};
|
||||
|
||||
// DB8500_REGULATOR_VRF1
|
||||
db8500_vrf1_reg: db8500_vrf1 {
|
||||
regulator-name = "db8500-vrf1";
|
||||
};
|
||||
|
||||
// DB8500_REGULATOR_SWITCH_SVAMMDSP
|
||||
db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
|
||||
regulator-name = "db8500-sva-mmdsp";
|
||||
};
|
||||
|
||||
// DB8500_REGULATOR_SWITCH_SVAMMDSPRET
|
||||
db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
|
||||
regulator-name = "db8500-sva-mmdsp-ret";
|
||||
};
|
||||
|
||||
// DB8500_REGULATOR_SWITCH_SVAPIPE
|
||||
db8500_sva_pipe_reg: db8500_sva_pipe {
|
||||
regulator-name = "db8500_sva_pipe";
|
||||
};
|
||||
|
||||
// DB8500_REGULATOR_SWITCH_SIAMMDSP
|
||||
db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
|
||||
regulator-name = "db8500_sia_mmdsp";
|
||||
};
|
||||
|
||||
// DB8500_REGULATOR_SWITCH_SIAMMDSPRET
|
||||
db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
|
||||
regulator-name = "db8500-sia-mmdsp-ret";
|
||||
};
|
||||
|
||||
// DB8500_REGULATOR_SWITCH_SIAPIPE
|
||||
db8500_sia_pipe_reg: db8500_sia_pipe {
|
||||
regulator-name = "db8500-sia-pipe";
|
||||
};
|
||||
|
||||
// DB8500_REGULATOR_SWITCH_SGA
|
||||
db8500_sga_reg: db8500_sga {
|
||||
regulator-name = "db8500-sga";
|
||||
vin-supply = <&db8500_vape_reg>;
|
||||
};
|
||||
|
||||
// DB8500_REGULATOR_SWITCH_B2R2_MCDE
|
||||
db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
|
||||
regulator-name = "db8500-b2r2-mcde";
|
||||
vin-supply = <&db8500_vape_reg>;
|
||||
};
|
||||
|
||||
// DB8500_REGULATOR_SWITCH_ESRAM12
|
||||
db8500_esram12_reg: db8500_esram12 {
|
||||
regulator-name = "db8500-esram12";
|
||||
};
|
||||
|
||||
// DB8500_REGULATOR_SWITCH_ESRAM12RET
|
||||
db8500_esram12_ret_reg: db8500_esram12_ret {
|
||||
regulator-name = "db8500-esram12-ret";
|
||||
};
|
||||
|
||||
// DB8500_REGULATOR_SWITCH_ESRAM34
|
||||
db8500_esram34_reg: db8500_esram34 {
|
||||
regulator-name = "db8500-esram34";
|
||||
};
|
||||
|
||||
// DB8500_REGULATOR_SWITCH_ESRAM34RET
|
||||
db8500_esram34_ret_reg: db8500_esram34_ret {
|
||||
regulator-name = "db8500-esram34-ret";
|
||||
};
|
||||
};
|
||||
|
||||
ab8500@5 {
|
||||
compatible = "stericsson,ab8500";
|
||||
reg = <5>; /* mailbox 5 is i2c */
|
||||
interrupts = <0 40 0x4>;
|
||||
|
||||
ab8500-regulators {
|
||||
compatible = "stericsson,ab8500-regulator";
|
||||
|
||||
// supplies to the display/camera
|
||||
ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
|
||||
regulator-name = "V-DISPLAY";
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
regulator-boot-on;
|
||||
/* BUG: If turned off MMC will be affected. */
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
// supplies to the on-board eMMC
|
||||
ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
|
||||
regulator-name = "V-eMMC1";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
// supply for VAUX3; SDcard slots
|
||||
ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
|
||||
regulator-name = "V-MMC-SD";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
// supply for v-intcore12; VINTCORE12 LDO
|
||||
ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
|
||||
regulator-name = "V-INTCORE";
|
||||
};
|
||||
|
||||
// supply for tvout; gpadc; TVOUT LDO
|
||||
ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
|
||||
regulator-name = "V-TVOUT";
|
||||
};
|
||||
|
||||
// supply for ab8500-usb; USB LDO
|
||||
ab8500_ldo_usb_reg: ab8500_ldo_usb {
|
||||
regulator-name = "dummy";
|
||||
};
|
||||
|
||||
// supply for ab8500-vaudio; VAUDIO LDO
|
||||
ab8500_ldo_audio_reg: ab8500_ldo_audio {
|
||||
regulator-name = "V-AUD";
|
||||
};
|
||||
|
||||
// supply for v-anamic1 VAMic1-LDO
|
||||
ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
|
||||
regulator-name = "V-AMIC1";
|
||||
};
|
||||
|
||||
// supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
|
||||
ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
|
||||
regulator-name = "V-AMIC2";
|
||||
};
|
||||
|
||||
// supply for v-dmic; VDMIC LDO
|
||||
ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
|
||||
regulator-name = "V-DMIC";
|
||||
};
|
||||
|
||||
// supply for U8500 CSI/DSI; VANA LDO
|
||||
ab8500_ldo_ana_reg: ab8500_ldo_ana {
|
||||
regulator-name = "V-CSI/DSI";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -235,7 +432,8 @@
|
|||
status = "disabled";
|
||||
|
||||
// Add one of these for each child device
|
||||
cs-gpios = <&gpio0 31 &gpio4 14 &gpio4 16 &gpio6 22 &gpio7 0>;
|
||||
cs-gpios = <&gpio0 31 0x4 &gpio4 14 0x4 &gpio4 16 0x4
|
||||
&gpio6 22 0x4 &gpio7 0 0x4>;
|
||||
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -30,6 +30,22 @@
|
|||
reg = <0x10481000 0x1000>, <0x10482000 0x2000>;
|
||||
};
|
||||
|
||||
combiner:interrupt-controller@10440000 {
|
||||
compatible = "samsung,exynos4210-combiner";
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
samsung,combiner-nr = <32>;
|
||||
reg = <0x10440000 0x1000>;
|
||||
interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
|
||||
<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
|
||||
<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
|
||||
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
|
||||
<0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
|
||||
<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
|
||||
<0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
|
||||
<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
|
||||
};
|
||||
|
||||
watchdog {
|
||||
compatible = "samsung,s3c2410-wdt";
|
||||
reg = <0x101D0000 0x100>;
|
||||
|
|
|
|||
|
|
@ -213,5 +213,14 @@
|
|||
status = "disabled";
|
||||
};
|
||||
};
|
||||
nand@d8000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
compatible = "fsl,imx27-nand";
|
||||
reg = <0xd8000000 0x1000>;
|
||||
interrupts = <29>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -215,45 +215,8 @@
|
|||
gpio: gpio@40028000 {
|
||||
compatible = "nxp,lpc3220-gpio";
|
||||
reg = <0x40028000 0x1000>;
|
||||
/* create a private address space for enumeration */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
gpio_p0: gpio-bank@0 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
gpio_p1: gpio-bank@1 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
gpio_p2: gpio-bank@2 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
gpio_p3: gpio-bank@3 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <3>;
|
||||
};
|
||||
|
||||
gpi_p3: gpio-bank@4 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <4>;
|
||||
};
|
||||
|
||||
gpo_p3: gpio-bank@5 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <5>;
|
||||
};
|
||||
gpio-controller;
|
||||
#gpio-cells = <3>; /* bank, pin, flags */
|
||||
};
|
||||
|
||||
watchdog@4003C000 {
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
/include/ "mmp2.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell MMP2 Aspenite Development Board";
|
||||
model = "Marvell MMP2 Brownstone Development Board";
|
||||
compatible = "mrvl,mmp2-brownstone", "mrvl,mmp2";
|
||||
|
||||
chosen {
|
||||
|
|
@ -19,7 +19,7 @@
|
|||
};
|
||||
|
||||
memory {
|
||||
reg = <0x00000000 0x04000000>;
|
||||
reg = <0x00000000 0x08000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
|
|
|
|||
|
|
@ -44,6 +44,8 @@
|
|||
compatible = "ti,omap2-intc";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
ti,intc-size = <96>;
|
||||
reg = <0x480FE000 0x1000>;
|
||||
};
|
||||
|
||||
uart1: serial@4806a000 {
|
||||
|
|
|
|||
|
|
@ -131,13 +131,13 @@
|
|||
compatible = "gpio-leds";
|
||||
|
||||
led0 {
|
||||
gpios = <&gpo_p3 1 1>; /* GPO_P3 1, GPIO 80, active low */
|
||||
gpios = <&gpio 5 1 1>; /* GPO_P3 1, GPIO 80, active low */
|
||||
linux,default-trigger = "heartbeat";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led1 {
|
||||
gpios = <&gpo_p3 14 1>; /* GPO_P3 14, GPIO 93, active low */
|
||||
gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */
|
||||
linux,default-trigger = "timer";
|
||||
default-state = "off";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -20,6 +20,16 @@
|
|||
reg = <0x00000000 0x20000000>;
|
||||
};
|
||||
|
||||
en_3v3_reg: en_3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "en-3v3-fixed-supply";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpios = <&gpio0 26 0x4>; // 26
|
||||
startup-delay-us = <5000>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
|
|
@ -30,35 +40,35 @@
|
|||
wakeup = <1>;
|
||||
linux,code = <2>;
|
||||
label = "userpb";
|
||||
gpios = <&gpio1 0 0>;
|
||||
gpios = <&gpio1 0 0x4>;
|
||||
};
|
||||
button@2 {
|
||||
debounce_interval = <50>;
|
||||
wakeup = <1>;
|
||||
linux,code = <3>;
|
||||
label = "extkb1";
|
||||
gpios = <&gpio4 23 0>;
|
||||
gpios = <&gpio4 23 0x4>;
|
||||
};
|
||||
button@3 {
|
||||
debounce_interval = <50>;
|
||||
wakeup = <1>;
|
||||
linux,code = <4>;
|
||||
label = "extkb2";
|
||||
gpios = <&gpio4 24 0>;
|
||||
gpios = <&gpio4 24 0x4>;
|
||||
};
|
||||
button@4 {
|
||||
debounce_interval = <50>;
|
||||
wakeup = <1>;
|
||||
linux,code = <5>;
|
||||
label = "extkb3";
|
||||
gpios = <&gpio5 1 0>;
|
||||
gpios = <&gpio5 1 0x4>;
|
||||
};
|
||||
button@5 {
|
||||
debounce_interval = <50>;
|
||||
wakeup = <1>;
|
||||
linux,code = <6>;
|
||||
label = "extkb4";
|
||||
gpios = <&gpio5 2 0>;
|
||||
gpios = <&gpio5 2 0x4>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -66,12 +76,11 @@
|
|||
compatible = "gpio-leds";
|
||||
used-led {
|
||||
label = "user_led";
|
||||
gpios = <&gpio4 14>;
|
||||
gpios = <&gpio4 14 0x4>;
|
||||
};
|
||||
};
|
||||
|
||||
soc-u9500 {
|
||||
|
||||
external-bus@50000000 {
|
||||
status = "okay";
|
||||
|
||||
|
|
@ -80,6 +89,9 @@
|
|||
reg = <0 0x10000>;
|
||||
interrupts = <12 0x1>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
vdd33a-supply = <&en_3v3_reg>;
|
||||
vddvario-supply = <&db8500_vape_reg>;
|
||||
|
||||
|
||||
reg-shift = <1>;
|
||||
reg-io-width = <2>;
|
||||
|
|
@ -91,11 +103,13 @@
|
|||
|
||||
sdi@80126000 {
|
||||
status = "enabled";
|
||||
cd-gpios = <&gpio6 26>;
|
||||
vmmc-supply = <&ab8500_ldo_aux3_reg>;
|
||||
cd-gpios = <&gpio6 26 0x4>; // 218
|
||||
};
|
||||
|
||||
sdi@80114000 {
|
||||
status = "enabled";
|
||||
vmmc-supply = <&ab8500_ldo_aux2_reg>;
|
||||
};
|
||||
|
||||
uart@80120000 {
|
||||
|
|
@ -114,7 +128,7 @@
|
|||
tc3589x@42 {
|
||||
//compatible = "tc3589x";
|
||||
reg = <0x42>;
|
||||
interrupts = <25>;
|
||||
gpios = <&gpio6 25 0x4>;
|
||||
interrupt-parent = <&gpio6>;
|
||||
};
|
||||
tps61052@33 {
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* DTS file for SPEAr1310 Evaluation Baord
|
||||
*
|
||||
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
|
||||
* Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* DTS file for all SPEAr1310 SoCs
|
||||
*
|
||||
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
|
||||
* Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* DTS file for SPEAr1340 Evaluation Baord
|
||||
*
|
||||
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
|
||||
* Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* DTS file for all SPEAr1340 SoCs
|
||||
*
|
||||
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
|
||||
* Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* DTS file for all SPEAr13xx SoCs
|
||||
*
|
||||
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
|
||||
* Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* DTS file for SPEAr300 Evaluation Baord
|
||||
*
|
||||
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
|
||||
* Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* DTS file for SPEAr300 SoC
|
||||
*
|
||||
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
|
||||
* Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* DTS file for SPEAr310 Evaluation Baord
|
||||
*
|
||||
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
|
||||
* Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* DTS file for SPEAr310 SoC
|
||||
*
|
||||
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
|
||||
* Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* DTS file for SPEAr320 Evaluation Baord
|
||||
*
|
||||
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
|
||||
* Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* DTS file for SPEAr320 SoC
|
||||
*
|
||||
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
|
||||
* Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* DTS file for all SPEAr3xx SoCs
|
||||
*
|
||||
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
|
||||
* Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
|
|
|
|||
|
|
@ -73,7 +73,10 @@
|
|||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x2c001000 0x1000>,
|
||||
<0x2c002000 0x100>;
|
||||
<0x2c002000 0x1000>,
|
||||
<0x2c004000 0x2000>,
|
||||
<0x2c006000 0x2000>;
|
||||
interrupts = <1 9 0xf04>;
|
||||
};
|
||||
|
||||
memory-controller@7ffd0000 {
|
||||
|
|
@ -93,6 +96,14 @@
|
|||
<0 91 4>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts = <1 13 0xf08>,
|
||||
<1 14 0xf08>,
|
||||
<1 11 0xf08>,
|
||||
<1 10 0xf08>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
|
||||
interrupts = <0 68 4>,
|
||||
|
|
|
|||
|
|
@ -77,13 +77,18 @@
|
|||
|
||||
timer@2c000600 {
|
||||
compatible = "arm,cortex-a5-twd-timer";
|
||||
reg = <0x2c000600 0x38>;
|
||||
interrupts = <1 2 0x304>,
|
||||
<1 3 0x304>;
|
||||
reg = <0x2c000600 0x20>;
|
||||
interrupts = <1 13 0x304>;
|
||||
};
|
||||
|
||||
watchdog@2c000620 {
|
||||
compatible = "arm,cortex-a5-twd-wdt";
|
||||
reg = <0x2c000620 0x20>;
|
||||
interrupts = <1 14 0x304>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@2c001000 {
|
||||
compatible = "arm,corex-a5-gic", "arm,cortex-a9-gic";
|
||||
compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
|
|
|
|||
|
|
@ -105,8 +105,13 @@
|
|||
timer@1e000600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0x1e000600 0x20>;
|
||||
interrupts = <1 2 0xf04>,
|
||||
<1 3 0xf04>;
|
||||
interrupts = <1 13 0xf04>;
|
||||
};
|
||||
|
||||
watchdog@1e000620 {
|
||||
compatible = "arm,cortex-a9-twd-wdt";
|
||||
reg = <0x1e000620 0x20>;
|
||||
interrupts = <1 14 0xf04>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@1e001000 {
|
||||
|
|
|
|||
|
|
@ -366,8 +366,8 @@ static int __dmabounce_sync_for_cpu(struct device *dev, dma_addr_t addr,
|
|||
struct safe_buffer *buf;
|
||||
unsigned long off;
|
||||
|
||||
dev_dbg(dev, "%s(dma=%#x,off=%#lx,sz=%zx,dir=%x)\n",
|
||||
__func__, addr, off, sz, dir);
|
||||
dev_dbg(dev, "%s(dma=%#x,sz=%zx,dir=%x)\n",
|
||||
__func__, addr, sz, dir);
|
||||
|
||||
buf = find_safe_buffer_dev(dev, addr, __func__);
|
||||
if (!buf)
|
||||
|
|
@ -377,8 +377,8 @@ static int __dmabounce_sync_for_cpu(struct device *dev, dma_addr_t addr,
|
|||
|
||||
BUG_ON(buf->direction != dir);
|
||||
|
||||
dev_dbg(dev, "%s: unsafe buffer %p (dma=%#x) mapped to %p (dma=%#x)\n",
|
||||
__func__, buf->ptr, virt_to_dma(dev, buf->ptr),
|
||||
dev_dbg(dev, "%s: unsafe buffer %p (dma=%#x off=%#lx) mapped to %p (dma=%#x)\n",
|
||||
__func__, buf->ptr, virt_to_dma(dev, buf->ptr), off,
|
||||
buf->safe, buf->safe_dma_addr);
|
||||
|
||||
DO_STATS(dev->archdata.dmabounce->bounce_count++);
|
||||
|
|
@ -406,8 +406,8 @@ static int __dmabounce_sync_for_device(struct device *dev, dma_addr_t addr,
|
|||
struct safe_buffer *buf;
|
||||
unsigned long off;
|
||||
|
||||
dev_dbg(dev, "%s(dma=%#x,off=%#lx,sz=%zx,dir=%x)\n",
|
||||
__func__, addr, off, sz, dir);
|
||||
dev_dbg(dev, "%s(dma=%#x,sz=%zx,dir=%x)\n",
|
||||
__func__, addr, sz, dir);
|
||||
|
||||
buf = find_safe_buffer_dev(dev, addr, __func__);
|
||||
if (!buf)
|
||||
|
|
@ -417,8 +417,8 @@ static int __dmabounce_sync_for_device(struct device *dev, dma_addr_t addr,
|
|||
|
||||
BUG_ON(buf->direction != dir);
|
||||
|
||||
dev_dbg(dev, "%s: unsafe buffer %p (dma=%#x) mapped to %p (dma=%#x)\n",
|
||||
__func__, buf->ptr, virt_to_dma(dev, buf->ptr),
|
||||
dev_dbg(dev, "%s: unsafe buffer %p (dma=%#x off=%#lx) mapped to %p (dma=%#x)\n",
|
||||
__func__, buf->ptr, virt_to_dma(dev, buf->ptr), off,
|
||||
buf->safe, buf->safe_dma_addr);
|
||||
|
||||
DO_STATS(dev->archdata.dmabounce->bounce_count++);
|
||||
|
|
|
|||
|
|
@ -75,6 +75,7 @@ CONFIG_AB5500_CORE=y
|
|||
CONFIG_AB8500_CORE=y
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_REGULATOR_AB8500=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
# CONFIG_HID_SUPPORT is not set
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_AB8500_USB=y
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
" .long 1b, 4f, 2b, 4f\n" \
|
||||
" .popsection\n" \
|
||||
" .pushsection .fixup,\"ax\"\n" \
|
||||
" .align 2\n" \
|
||||
"4: mov %0, " err_reg "\n" \
|
||||
" b 3b\n" \
|
||||
" .popsection"
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
* ARM PrimeXsys System Controller SP810 header file
|
||||
*
|
||||
* Copyright (C) 2009 ST Microelectronics
|
||||
* Viresh Kumar<viresh.kumar@st.com>
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
|
|
|
|||
|
|
@ -22,9 +22,6 @@
|
|||
typedef unsigned short __kernel_mode_t;
|
||||
#define __kernel_mode_t __kernel_mode_t
|
||||
|
||||
typedef unsigned short __kernel_nlink_t;
|
||||
#define __kernel_nlink_t __kernel_nlink_t
|
||||
|
||||
typedef unsigned short __kernel_ipc_pid_t;
|
||||
#define __kernel_ipc_pid_t __kernel_ipc_pid_t
|
||||
|
||||
|
|
|
|||
|
|
@ -495,6 +495,7 @@ ENDPROC(__und_usr)
|
|||
* The out of line fixup for the ldrt above.
|
||||
*/
|
||||
.pushsection .fixup, "ax"
|
||||
.align 2
|
||||
4: mov pc, r9
|
||||
.popsection
|
||||
.pushsection __ex_table,"a"
|
||||
|
|
|
|||
|
|
@ -660,7 +660,7 @@ static const union decode_item t32_table_1111_100x[] = {
|
|||
/* LDRSB (literal) 1111 1001 x001 1111 xxxx xxxx xxxx xxxx */
|
||||
/* LDRH (literal) 1111 1000 x011 1111 xxxx xxxx xxxx xxxx */
|
||||
/* LDRSH (literal) 1111 1001 x011 1111 xxxx xxxx xxxx xxxx */
|
||||
DECODE_EMULATEX (0xfe5f0000, 0xf81f0000, t32_simulate_ldr_literal,
|
||||
DECODE_SIMULATEX(0xfe5f0000, 0xf81f0000, t32_simulate_ldr_literal,
|
||||
REGS(PC, NOSPPCX, 0, 0, 0)),
|
||||
|
||||
/* STRB (immediate) 1111 1000 0000 xxxx xxxx 1xxx xxxx xxxx */
|
||||
|
|
|
|||
|
|
@ -22,8 +22,6 @@
|
|||
|
||||
#include "signal.h"
|
||||
|
||||
#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
|
||||
|
||||
/*
|
||||
* For ARM syscalls, we encode the syscall number into the instruction.
|
||||
*/
|
||||
|
|
@ -210,10 +208,8 @@ static int restore_sigframe(struct pt_regs *regs, struct sigframe __user *sf)
|
|||
int err;
|
||||
|
||||
err = __copy_from_user(&set, &sf->uc.uc_sigmask, sizeof(set));
|
||||
if (err == 0) {
|
||||
sigdelsetmask(&set, ~_BLOCKABLE);
|
||||
if (err == 0)
|
||||
set_current_blocked(&set);
|
||||
}
|
||||
|
||||
__get_user_error(regs->ARM_r0, &sf->uc.uc_mcontext.arm_r0, err);
|
||||
__get_user_error(regs->ARM_r1, &sf->uc.uc_mcontext.arm_r1, err);
|
||||
|
|
@ -528,13 +524,13 @@ setup_rt_frame(int usig, struct k_sigaction *ka, siginfo_t *info,
|
|||
/*
|
||||
* OK, we're invoking a handler
|
||||
*/
|
||||
static int
|
||||
static void
|
||||
handle_signal(unsigned long sig, struct k_sigaction *ka,
|
||||
siginfo_t *info, sigset_t *oldset,
|
||||
struct pt_regs * regs)
|
||||
siginfo_t *info, struct pt_regs *regs)
|
||||
{
|
||||
struct thread_info *thread = current_thread_info();
|
||||
struct task_struct *tsk = current;
|
||||
sigset_t *oldset = sigmask_to_save();
|
||||
int usig = sig;
|
||||
int ret;
|
||||
|
||||
|
|
@ -559,17 +555,9 @@ handle_signal(unsigned long sig, struct k_sigaction *ka,
|
|||
|
||||
if (ret != 0) {
|
||||
force_sigsegv(sig, tsk);
|
||||
return ret;
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Block the signal if we were successful.
|
||||
*/
|
||||
block_sigmask(ka, sig);
|
||||
|
||||
tracehook_signal_handler(sig, info, ka, regs, 0);
|
||||
|
||||
return 0;
|
||||
signal_delivered(sig, info, ka, regs, 0);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -617,8 +605,6 @@ static void do_signal(struct pt_regs *regs, int syscall)
|
|||
*/
|
||||
signr = get_signal_to_deliver(&info, &ka, regs, NULL);
|
||||
if (signr > 0) {
|
||||
sigset_t *oldset;
|
||||
|
||||
/*
|
||||
* Depending on the signal settings we may need to revert the
|
||||
* decision to restart the system call. But skip this if a
|
||||
|
|
@ -635,20 +621,7 @@ static void do_signal(struct pt_regs *regs, int syscall)
|
|||
clear_thread_flag(TIF_SYSCALL_RESTARTSYS);
|
||||
}
|
||||
|
||||
if (test_thread_flag(TIF_RESTORE_SIGMASK))
|
||||
oldset = ¤t->saved_sigmask;
|
||||
else
|
||||
oldset = ¤t->blocked;
|
||||
if (handle_signal(signr, &ka, &info, oldset, regs) == 0) {
|
||||
/*
|
||||
* A signal was successfully delivered; the saved
|
||||
* sigmask will have been stored in the signal frame,
|
||||
* and will be restored by sigreturn, so we can simply
|
||||
* clear the TIF_RESTORE_SIGMASK flag.
|
||||
*/
|
||||
if (test_thread_flag(TIF_RESTORE_SIGMASK))
|
||||
clear_thread_flag(TIF_RESTORE_SIGMASK);
|
||||
}
|
||||
handle_signal(signr, &ka, &info, regs);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -663,11 +636,7 @@ static void do_signal(struct pt_regs *regs, int syscall)
|
|||
set_thread_flag(TIF_SYSCALL_RESTARTSYS);
|
||||
}
|
||||
|
||||
/* If there's no signal to deliver, we just put the saved sigmask
|
||||
* back.
|
||||
*/
|
||||
if (test_and_clear_thread_flag(TIF_RESTORE_SIGMASK))
|
||||
set_current_blocked(¤t->saved_sigmask);
|
||||
restore_saved_sigmask();
|
||||
}
|
||||
|
||||
asmlinkage void
|
||||
|
|
@ -679,7 +648,5 @@ do_notify_resume(struct pt_regs *regs, unsigned int thread_flags, int syscall)
|
|||
if (thread_flags & _TIF_NOTIFY_RESUME) {
|
||||
clear_thread_flag(TIF_NOTIFY_RESUME);
|
||||
tracehook_notify_resume(regs);
|
||||
if (current->replacement_session_keyring)
|
||||
key_replace_session_keyring();
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -109,7 +109,6 @@ static void percpu_timer_stop(void);
|
|||
int __cpu_disable(void)
|
||||
{
|
||||
unsigned int cpu = smp_processor_id();
|
||||
struct task_struct *p;
|
||||
int ret;
|
||||
|
||||
ret = platform_cpu_disable(cpu);
|
||||
|
|
@ -139,12 +138,7 @@ int __cpu_disable(void)
|
|||
flush_cache_all();
|
||||
local_flush_tlb_all();
|
||||
|
||||
read_lock(&tasklist_lock);
|
||||
for_each_process(p) {
|
||||
if (p->mm)
|
||||
cpumask_clear_cpu(cpu, mm_cpumask(p->mm));
|
||||
}
|
||||
read_unlock(&tasklist_lock);
|
||||
clear_tasks_mm_cpumask(cpu);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -82,8 +82,6 @@ static int snappercl15_nand_dev_ready(struct mtd_info *mtd)
|
|||
return !!(__raw_readw(NAND_CTRL_ADDR(chip)) & SNAPPERCL15_NAND_RDY);
|
||||
}
|
||||
|
||||
static const char *snappercl15_nand_part_probes[] = {"cmdlinepart", NULL};
|
||||
|
||||
static struct mtd_partition snappercl15_nand_parts[] = {
|
||||
{
|
||||
.name = "Kernel",
|
||||
|
|
@ -100,10 +98,8 @@ static struct mtd_partition snappercl15_nand_parts[] = {
|
|||
static struct platform_nand_data snappercl15_nand_data = {
|
||||
.chip = {
|
||||
.nr_chips = 1,
|
||||
.part_probe_types = snappercl15_nand_part_probes,
|
||||
.partitions = snappercl15_nand_parts,
|
||||
.nr_partitions = ARRAY_SIZE(snappercl15_nand_parts),
|
||||
.options = NAND_NO_AUTOINCR,
|
||||
.chip_delay = 25,
|
||||
},
|
||||
.ctrl = {
|
||||
|
|
|
|||
|
|
@ -105,8 +105,6 @@ static int ts72xx_nand_device_ready(struct mtd_info *mtd)
|
|||
return !!(__raw_readb(addr) & 0x20);
|
||||
}
|
||||
|
||||
static const char *ts72xx_nand_part_probes[] = { "cmdlinepart", NULL };
|
||||
|
||||
#define TS72XX_BOOTROM_PART_SIZE (SZ_16K)
|
||||
#define TS72XX_REDBOOT_PART_SIZE (SZ_2M + SZ_1M)
|
||||
|
||||
|
|
@ -134,7 +132,6 @@ static struct platform_nand_data ts72xx_nand_data = {
|
|||
.nr_chips = 1,
|
||||
.chip_offset = 0,
|
||||
.chip_delay = 15,
|
||||
.part_probe_types = ts72xx_nand_part_probes,
|
||||
.partitions = ts72xx_nand_parts,
|
||||
.nr_partitions = ARRAY_SIZE(ts72xx_nand_parts),
|
||||
},
|
||||
|
|
|
|||
|
|
@ -62,6 +62,8 @@ config SOC_EXYNOS5250
|
|||
default y
|
||||
depends on ARCH_EXYNOS5
|
||||
select SAMSUNG_DMADEV
|
||||
select S5P_PM if PM
|
||||
select S5P_SLEEP if PM
|
||||
help
|
||||
Enable EXYNOS5250 SoC support
|
||||
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@ obj-$(CONFIG_PM) += pm.o
|
|||
obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
|
||||
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
|
||||
|
||||
obj-$(CONFIG_ARCH_EXYNOS4) += pmu.o
|
||||
obj-$(CONFIG_ARCH_EXYNOS) += pmu.o
|
||||
|
||||
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
|
||||
|
||||
|
|
|
|||
|
|
@ -30,7 +30,56 @@
|
|||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static struct sleep_save exynos5_clock_save[] = {
|
||||
/* will be implemented */
|
||||
SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP),
|
||||
SAVE_ITEM(EXYNOS5_CLKSRC_MASK_GSCL),
|
||||
SAVE_ITEM(EXYNOS5_CLKSRC_MASK_DISP1_0),
|
||||
SAVE_ITEM(EXYNOS5_CLKSRC_MASK_FSYS),
|
||||
SAVE_ITEM(EXYNOS5_CLKSRC_MASK_MAUDIO),
|
||||
SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC0),
|
||||
SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC1),
|
||||
SAVE_ITEM(EXYNOS5_CLKGATE_IP_GSCL),
|
||||
SAVE_ITEM(EXYNOS5_CLKGATE_IP_DISP1),
|
||||
SAVE_ITEM(EXYNOS5_CLKGATE_IP_MFC),
|
||||
SAVE_ITEM(EXYNOS5_CLKGATE_IP_G3D),
|
||||
SAVE_ITEM(EXYNOS5_CLKGATE_IP_GEN),
|
||||
SAVE_ITEM(EXYNOS5_CLKGATE_IP_FSYS),
|
||||
SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIC),
|
||||
SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIS),
|
||||
SAVE_ITEM(EXYNOS5_CLKGATE_BLOCK),
|
||||
SAVE_ITEM(EXYNOS5_CLKDIV_TOP0),
|
||||
SAVE_ITEM(EXYNOS5_CLKDIV_TOP1),
|
||||
SAVE_ITEM(EXYNOS5_CLKDIV_GSCL),
|
||||
SAVE_ITEM(EXYNOS5_CLKDIV_DISP1_0),
|
||||
SAVE_ITEM(EXYNOS5_CLKDIV_GEN),
|
||||
SAVE_ITEM(EXYNOS5_CLKDIV_MAUDIO),
|
||||
SAVE_ITEM(EXYNOS5_CLKDIV_FSYS0),
|
||||
SAVE_ITEM(EXYNOS5_CLKDIV_FSYS1),
|
||||
SAVE_ITEM(EXYNOS5_CLKDIV_FSYS2),
|
||||
SAVE_ITEM(EXYNOS5_CLKDIV_FSYS3),
|
||||
SAVE_ITEM(EXYNOS5_CLKDIV_PERIC0),
|
||||
SAVE_ITEM(EXYNOS5_CLKDIV_PERIC1),
|
||||
SAVE_ITEM(EXYNOS5_CLKDIV_PERIC2),
|
||||
SAVE_ITEM(EXYNOS5_CLKDIV_PERIC3),
|
||||
SAVE_ITEM(EXYNOS5_CLKDIV_PERIC4),
|
||||
SAVE_ITEM(EXYNOS5_CLKDIV_PERIC5),
|
||||
SAVE_ITEM(EXYNOS5_SCLK_DIV_ISP),
|
||||
SAVE_ITEM(EXYNOS5_CLKSRC_TOP0),
|
||||
SAVE_ITEM(EXYNOS5_CLKSRC_TOP1),
|
||||
SAVE_ITEM(EXYNOS5_CLKSRC_TOP2),
|
||||
SAVE_ITEM(EXYNOS5_CLKSRC_TOP3),
|
||||
SAVE_ITEM(EXYNOS5_CLKSRC_GSCL),
|
||||
SAVE_ITEM(EXYNOS5_CLKSRC_DISP1_0),
|
||||
SAVE_ITEM(EXYNOS5_CLKSRC_MAUDIO),
|
||||
SAVE_ITEM(EXYNOS5_CLKSRC_FSYS),
|
||||
SAVE_ITEM(EXYNOS5_CLKSRC_PERIC0),
|
||||
SAVE_ITEM(EXYNOS5_CLKSRC_PERIC1),
|
||||
SAVE_ITEM(EXYNOS5_SCLK_SRC_ISP),
|
||||
SAVE_ITEM(EXYNOS5_EPLL_CON0),
|
||||
SAVE_ITEM(EXYNOS5_EPLL_CON1),
|
||||
SAVE_ITEM(EXYNOS5_EPLL_CON2),
|
||||
SAVE_ITEM(EXYNOS5_VPLL_CON0),
|
||||
SAVE_ITEM(EXYNOS5_VPLL_CON1),
|
||||
SAVE_ITEM(EXYNOS5_VPLL_CON2),
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -100,7 +100,7 @@ static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
|
|||
exynos4_set_wakeupmask();
|
||||
|
||||
/* Set value of power down register for aftr mode */
|
||||
exynos4_sys_powerdown_conf(SYS_AFTR);
|
||||
exynos_sys_powerdown_conf(SYS_AFTR);
|
||||
|
||||
__raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
|
||||
__raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
|
||||
|
|
|
|||
|
|
@ -33,7 +33,7 @@ static inline void s3c_pm_arch_prepare_irqs(void)
|
|||
__raw_writel(tmp, S5P_WAKEUP_MASK);
|
||||
|
||||
__raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK);
|
||||
__raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
|
||||
__raw_writel(s3c_irqwake_eintmask & 0xFFFFFFFE, S5P_EINT_WAKEUP_MASK);
|
||||
}
|
||||
|
||||
static inline void s3c_pm_arch_stop_clocks(void)
|
||||
|
|
|
|||
|
|
@ -23,12 +23,12 @@ enum sys_powerdown {
|
|||
};
|
||||
|
||||
extern unsigned long l2x0_regs_phys;
|
||||
struct exynos4_pmu_conf {
|
||||
struct exynos_pmu_conf {
|
||||
void __iomem *reg;
|
||||
unsigned int val[NUM_SYS_POWERDOWN];
|
||||
};
|
||||
|
||||
extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
|
||||
extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
|
||||
extern void s3c_cpu_resume(void);
|
||||
|
||||
#endif /* __ASM_ARCH_PMU_H */
|
||||
|
|
|
|||
|
|
@ -274,36 +274,51 @@
|
|||
|
||||
#define EXYNOS5_CLKDIV_ACP EXYNOS_CLKREG(0x08500)
|
||||
|
||||
#define EXYNOS5_CLKSRC_TOP2 EXYNOS_CLKREG(0x10218)
|
||||
#define EXYNOS5_EPLL_CON0 EXYNOS_CLKREG(0x10130)
|
||||
#define EXYNOS5_EPLL_CON1 EXYNOS_CLKREG(0x10134)
|
||||
#define EXYNOS5_EPLL_CON2 EXYNOS_CLKREG(0x10138)
|
||||
#define EXYNOS5_VPLL_CON0 EXYNOS_CLKREG(0x10140)
|
||||
#define EXYNOS5_VPLL_CON1 EXYNOS_CLKREG(0x10144)
|
||||
#define EXYNOS5_VPLL_CON2 EXYNOS_CLKREG(0x10148)
|
||||
#define EXYNOS5_CPLL_CON0 EXYNOS_CLKREG(0x10120)
|
||||
|
||||
#define EXYNOS5_CLKSRC_TOP0 EXYNOS_CLKREG(0x10210)
|
||||
#define EXYNOS5_CLKSRC_TOP1 EXYNOS_CLKREG(0x10214)
|
||||
#define EXYNOS5_CLKSRC_TOP2 EXYNOS_CLKREG(0x10218)
|
||||
#define EXYNOS5_CLKSRC_TOP3 EXYNOS_CLKREG(0x1021C)
|
||||
#define EXYNOS5_CLKSRC_GSCL EXYNOS_CLKREG(0x10220)
|
||||
#define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C)
|
||||
#define EXYNOS5_CLKSRC_MAUDIO EXYNOS_CLKREG(0x10240)
|
||||
#define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244)
|
||||
#define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250)
|
||||
#define EXYNOS5_CLKSRC_PERIC1 EXYNOS_CLKREG(0x10254)
|
||||
#define EXYNOS5_SCLK_SRC_ISP EXYNOS_CLKREG(0x10270)
|
||||
|
||||
#define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310)
|
||||
#define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320)
|
||||
#define EXYNOS5_CLKSRC_MASK_DISP1_0 EXYNOS_CLKREG(0x1032C)
|
||||
#define EXYNOS5_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x10334)
|
||||
#define EXYNOS5_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x10340)
|
||||
#define EXYNOS5_CLKSRC_MASK_PERIC0 EXYNOS_CLKREG(0x10350)
|
||||
#define EXYNOS5_CLKSRC_MASK_PERIC1 EXYNOS_CLKREG(0x10354)
|
||||
|
||||
#define EXYNOS5_CLKDIV_TOP0 EXYNOS_CLKREG(0x10510)
|
||||
#define EXYNOS5_CLKDIV_TOP1 EXYNOS_CLKREG(0x10514)
|
||||
#define EXYNOS5_CLKDIV_GSCL EXYNOS_CLKREG(0x10520)
|
||||
#define EXYNOS5_CLKDIV_DISP1_0 EXYNOS_CLKREG(0x1052C)
|
||||
#define EXYNOS5_CLKDIV_GEN EXYNOS_CLKREG(0x1053C)
|
||||
#define EXYNOS5_CLKDIV_MAUDIO EXYNOS_CLKREG(0x10544)
|
||||
#define EXYNOS5_CLKDIV_FSYS0 EXYNOS_CLKREG(0x10548)
|
||||
#define EXYNOS5_CLKDIV_FSYS1 EXYNOS_CLKREG(0x1054C)
|
||||
#define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550)
|
||||
#define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554)
|
||||
#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558)
|
||||
#define EXYNOS5_CLKDIV_PERIC1 EXYNOS_CLKREG(0x1055C)
|
||||
#define EXYNOS5_CLKDIV_PERIC2 EXYNOS_CLKREG(0x10560)
|
||||
#define EXYNOS5_CLKDIV_PERIC3 EXYNOS_CLKREG(0x10564)
|
||||
#define EXYNOS5_CLKDIV_PERIC4 EXYNOS_CLKREG(0x10568)
|
||||
#define EXYNOS5_CLKDIV_PERIC5 EXYNOS_CLKREG(0x1056C)
|
||||
#define EXYNOS5_SCLK_DIV_ISP EXYNOS_CLKREG(0x10580)
|
||||
|
||||
#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800)
|
||||
#define EXYNOS5_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x0C800)
|
||||
|
|
@ -311,6 +326,7 @@
|
|||
#define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920)
|
||||
#define EXYNOS5_CLKGATE_IP_DISP1 EXYNOS_CLKREG(0x10928)
|
||||
#define EXYNOS5_CLKGATE_IP_MFC EXYNOS_CLKREG(0x1092C)
|
||||
#define EXYNOS5_CLKGATE_IP_G3D EXYNOS_CLKREG(0x10930)
|
||||
#define EXYNOS5_CLKGATE_IP_GEN EXYNOS_CLKREG(0x10934)
|
||||
#define EXYNOS5_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x10944)
|
||||
#define EXYNOS5_CLKGATE_IP_GPS EXYNOS_CLKREG(0x1094C)
|
||||
|
|
|
|||
|
|
@ -1,9 +1,8 @@
|
|||
/* linux/arch/arm/mach-exynos4/include/mach/regs-pmu.h
|
||||
*
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
/*
|
||||
* Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4 - Power management unit definition
|
||||
* EXYNOS - Power management unit definition
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
|
@ -229,4 +228,138 @@
|
|||
#define S5P_DIS_IRQ_CORE3 S5P_PMUREG(0x1034)
|
||||
#define S5P_DIS_IRQ_CENTRAL3 S5P_PMUREG(0x1038)
|
||||
|
||||
/* For EXYNOS5 */
|
||||
|
||||
#define EXYNOS5_USB_CFG S5P_PMUREG(0x0230)
|
||||
|
||||
#define EXYNOS5_ARM_CORE0_SYS_PWR_REG S5P_PMUREG(0x1000)
|
||||
#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1004)
|
||||
#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008)
|
||||
#define EXYNOS5_ARM_CORE1_SYS_PWR_REG S5P_PMUREG(0x1010)
|
||||
#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1014)
|
||||
#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1018)
|
||||
#define EXYNOS5_FSYS_ARM_SYS_PWR_REG S5P_PMUREG(0x1040)
|
||||
#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1048)
|
||||
#define EXYNOS5_ISP_ARM_SYS_PWR_REG S5P_PMUREG(0x1050)
|
||||
#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1054)
|
||||
#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1058)
|
||||
#define EXYNOS5_ARM_COMMON_SYS_PWR_REG S5P_PMUREG(0x1080)
|
||||
#define EXYNOS5_ARM_L2_SYS_PWR_REG S5P_PMUREG(0x10C0)
|
||||
#define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1100)
|
||||
#define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1104)
|
||||
#define EXYNOS5_CMU_RESET_SYS_PWR_REG S5P_PMUREG(0x110C)
|
||||
#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1120)
|
||||
#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1124)
|
||||
#define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x112C)
|
||||
#define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG S5P_PMUREG(0x1130)
|
||||
#define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG S5P_PMUREG(0x1134)
|
||||
#define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG S5P_PMUREG(0x1138)
|
||||
#define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1140)
|
||||
#define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1144)
|
||||
#define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1148)
|
||||
#define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x114C)
|
||||
#define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1150)
|
||||
#define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1154)
|
||||
#define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1164)
|
||||
#define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1170)
|
||||
#define EXYNOS5_TOP_BUS_SYS_PWR_REG S5P_PMUREG(0x1180)
|
||||
#define EXYNOS5_TOP_RETENTION_SYS_PWR_REG S5P_PMUREG(0x1184)
|
||||
#define EXYNOS5_TOP_PWR_SYS_PWR_REG S5P_PMUREG(0x1188)
|
||||
#define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1190)
|
||||
#define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1194)
|
||||
#define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1198)
|
||||
#define EXYNOS5_LOGIC_RESET_SYS_PWR_REG S5P_PMUREG(0x11A0)
|
||||
#define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG S5P_PMUREG(0x11A4)
|
||||
#define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B0)
|
||||
#define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B4)
|
||||
#define EXYNOS5_USBOTG_MEM_SYS_PWR_REG S5P_PMUREG(0x11C0)
|
||||
#define EXYNOS5_G2D_MEM_SYS_PWR_REG S5P_PMUREG(0x11C8)
|
||||
#define EXYNOS5_USBDRD_MEM_SYS_PWR_REG S5P_PMUREG(0x11CC)
|
||||
#define EXYNOS5_SDMMC_MEM_SYS_PWR_REG S5P_PMUREG(0x11D0)
|
||||
#define EXYNOS5_CSSYS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D4)
|
||||
#define EXYNOS5_SECSS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D8)
|
||||
#define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG S5P_PMUREG(0x11DC)
|
||||
#define EXYNOS5_INTRAM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E0)
|
||||
#define EXYNOS5_INTROM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E4)
|
||||
#define EXYNOS5_JPEG_MEM_SYS_PWR_REG S5P_PMUREG(0x11E8)
|
||||
#define EXYNOS5_HSI_MEM_SYS_PWR_REG S5P_PMUREG(0x11EC)
|
||||
#define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG S5P_PMUREG(0x11F4)
|
||||
#define EXYNOS5_SATA_MEM_SYS_PWR_REG S5P_PMUREG(0x11FC)
|
||||
#define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG S5P_PMUREG(0x1200)
|
||||
#define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG S5P_PMUREG(0x1204)
|
||||
#define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG S5P_PMUREG(0x1208)
|
||||
#define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG S5P_PMUREG(0x1220)
|
||||
#define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG S5P_PMUREG(0x1224)
|
||||
#define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG S5P_PMUREG(0x1228)
|
||||
#define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG S5P_PMUREG(0x122C)
|
||||
#define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG S5P_PMUREG(0x1230)
|
||||
#define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG S5P_PMUREG(0x1234)
|
||||
#define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG S5P_PMUREG(0x1238)
|
||||
#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x123C)
|
||||
#define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1240)
|
||||
#define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1250)
|
||||
#define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG S5P_PMUREG(0x1260)
|
||||
#define EXYNOS5_XUSBXTI_SYS_PWR_REG S5P_PMUREG(0x1280)
|
||||
#define EXYNOS5_XXTI_SYS_PWR_REG S5P_PMUREG(0x1284)
|
||||
#define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG S5P_PMUREG(0x12C0)
|
||||
#define EXYNOS5_GPIO_MODE_SYS_PWR_REG S5P_PMUREG(0x1300)
|
||||
#define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1320)
|
||||
#define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG S5P_PMUREG(0x1340)
|
||||
#define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG S5P_PMUREG(0x1344)
|
||||
#define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1348)
|
||||
#define EXYNOS5_GSCL_SYS_PWR_REG S5P_PMUREG(0x1400)
|
||||
#define EXYNOS5_ISP_SYS_PWR_REG S5P_PMUREG(0x1404)
|
||||
#define EXYNOS5_MFC_SYS_PWR_REG S5P_PMUREG(0x1408)
|
||||
#define EXYNOS5_G3D_SYS_PWR_REG S5P_PMUREG(0x140C)
|
||||
#define EXYNOS5_DISP1_SYS_PWR_REG S5P_PMUREG(0x1414)
|
||||
#define EXYNOS5_MAU_SYS_PWR_REG S5P_PMUREG(0x1418)
|
||||
#define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG S5P_PMUREG(0x1480)
|
||||
#define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG S5P_PMUREG(0x1484)
|
||||
#define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG S5P_PMUREG(0x1488)
|
||||
#define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG S5P_PMUREG(0x148C)
|
||||
#define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG S5P_PMUREG(0x1494)
|
||||
#define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG S5P_PMUREG(0x1498)
|
||||
#define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG S5P_PMUREG(0x14C0)
|
||||
#define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG S5P_PMUREG(0x14C4)
|
||||
#define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG S5P_PMUREG(0x14C8)
|
||||
#define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG S5P_PMUREG(0x14CC)
|
||||
#define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG S5P_PMUREG(0x14D4)
|
||||
#define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG S5P_PMUREG(0x14D8)
|
||||
#define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG S5P_PMUREG(0x1580)
|
||||
#define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG S5P_PMUREG(0x1584)
|
||||
#define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG S5P_PMUREG(0x1588)
|
||||
#define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG S5P_PMUREG(0x158C)
|
||||
#define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG S5P_PMUREG(0x1594)
|
||||
#define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG S5P_PMUREG(0x1598)
|
||||
|
||||
#define EXYNOS5_ARM_CORE0_OPTION S5P_PMUREG(0x2008)
|
||||
#define EXYNOS5_ARM_CORE1_OPTION S5P_PMUREG(0x2088)
|
||||
#define EXYNOS5_FSYS_ARM_OPTION S5P_PMUREG(0x2208)
|
||||
#define EXYNOS5_ISP_ARM_OPTION S5P_PMUREG(0x2288)
|
||||
#define EXYNOS5_ARM_COMMON_OPTION S5P_PMUREG(0x2408)
|
||||
#define EXYNOS5_TOP_PWR_OPTION S5P_PMUREG(0x2C48)
|
||||
#define EXYNOS5_TOP_PWR_SYSMEM_OPTION S5P_PMUREG(0x2CC8)
|
||||
#define EXYNOS5_JPEG_MEM_OPTION S5P_PMUREG(0x2F48)
|
||||
#define EXYNOS5_GSCL_STATUS S5P_PMUREG(0x4004)
|
||||
#define EXYNOS5_ISP_STATUS S5P_PMUREG(0x4024)
|
||||
#define EXYNOS5_GSCL_OPTION S5P_PMUREG(0x4008)
|
||||
#define EXYNOS5_ISP_OPTION S5P_PMUREG(0x4028)
|
||||
#define EXYNOS5_MFC_OPTION S5P_PMUREG(0x4048)
|
||||
#define EXYNOS5_G3D_CONFIGURATION S5P_PMUREG(0x4060)
|
||||
#define EXYNOS5_G3D_STATUS S5P_PMUREG(0x4064)
|
||||
#define EXYNOS5_G3D_OPTION S5P_PMUREG(0x4068)
|
||||
#define EXYNOS5_DISP1_OPTION S5P_PMUREG(0x40A8)
|
||||
#define EXYNOS5_MAU_OPTION S5P_PMUREG(0x40C8)
|
||||
|
||||
#define EXYNOS5_USE_SC_FEEDBACK (1 << 1)
|
||||
#define EXYNOS5_USE_SC_COUNTER (1 << 0)
|
||||
|
||||
#define EXYNOS5_MANUAL_L2RSTDISABLE_CONTROL (1 << 2)
|
||||
#define EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN (1 << 7)
|
||||
|
||||
#define EXYNOS5_OPTION_USE_STANDBYWFE (1 << 24)
|
||||
#define EXYNOS5_OPTION_USE_STANDBYWFI (1 << 16)
|
||||
|
||||
#define EXYNOS5_OPTION_USE_RETENTION (1 << 4)
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_PMU_H */
|
||||
|
|
|
|||
|
|
@ -237,25 +237,29 @@ static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
|
|||
#else
|
||||
/* Frame Buffer */
|
||||
static struct s3c_fb_pd_win nuri_fb_win0 = {
|
||||
.win_mode = {
|
||||
.left_margin = 64,
|
||||
.right_margin = 16,
|
||||
.upper_margin = 64,
|
||||
.lower_margin = 1,
|
||||
.hsync_len = 48,
|
||||
.vsync_len = 3,
|
||||
.xres = 1024,
|
||||
.yres = 600,
|
||||
.refresh = 60,
|
||||
},
|
||||
.max_bpp = 24,
|
||||
.default_bpp = 16,
|
||||
.xres = 1024,
|
||||
.yres = 600,
|
||||
.virtual_x = 1024,
|
||||
.virtual_y = 2 * 600,
|
||||
};
|
||||
|
||||
static struct fb_videomode nuri_lcd_timing = {
|
||||
.left_margin = 64,
|
||||
.right_margin = 16,
|
||||
.upper_margin = 64,
|
||||
.lower_margin = 1,
|
||||
.hsync_len = 48,
|
||||
.vsync_len = 3,
|
||||
.xres = 1024,
|
||||
.yres = 600,
|
||||
.refresh = 60,
|
||||
};
|
||||
|
||||
static struct s3c_fb_platdata nuri_fb_pdata __initdata = {
|
||||
.win[0] = &nuri_fb_win0,
|
||||
.vtiming = &nuri_lcd_timing,
|
||||
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
|
||||
VIDCON0_CLKSEL_LCD,
|
||||
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
|
||||
|
|
|
|||
|
|
@ -604,24 +604,28 @@ static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
|
|||
};
|
||||
#else
|
||||
static struct s3c_fb_pd_win origen_fb_win0 = {
|
||||
.win_mode = {
|
||||
.left_margin = 64,
|
||||
.right_margin = 16,
|
||||
.upper_margin = 64,
|
||||
.lower_margin = 16,
|
||||
.hsync_len = 48,
|
||||
.vsync_len = 3,
|
||||
.xres = 1024,
|
||||
.yres = 600,
|
||||
},
|
||||
.xres = 1024,
|
||||
.yres = 600,
|
||||
.max_bpp = 32,
|
||||
.default_bpp = 24,
|
||||
.virtual_x = 1024,
|
||||
.virtual_y = 2 * 600,
|
||||
};
|
||||
|
||||
static struct fb_videomode origen_lcd_timing = {
|
||||
.left_margin = 64,
|
||||
.right_margin = 16,
|
||||
.upper_margin = 64,
|
||||
.lower_margin = 16,
|
||||
.hsync_len = 48,
|
||||
.vsync_len = 3,
|
||||
.xres = 1024,
|
||||
.yres = 600,
|
||||
};
|
||||
|
||||
static struct s3c_fb_platdata origen_lcd_pdata __initdata = {
|
||||
.win[0] = &origen_fb_win0,
|
||||
.vtiming = &origen_lcd_timing,
|
||||
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
|
||||
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
|
||||
VIDCON1_INV_VCLK,
|
||||
|
|
|
|||
|
|
@ -178,22 +178,26 @@ static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
|
|||
};
|
||||
#else
|
||||
static struct s3c_fb_pd_win smdkv310_fb_win0 = {
|
||||
.win_mode = {
|
||||
.left_margin = 13,
|
||||
.right_margin = 8,
|
||||
.upper_margin = 7,
|
||||
.lower_margin = 5,
|
||||
.hsync_len = 3,
|
||||
.vsync_len = 1,
|
||||
.xres = 800,
|
||||
.yres = 480,
|
||||
},
|
||||
.max_bpp = 32,
|
||||
.default_bpp = 24,
|
||||
.max_bpp = 32,
|
||||
.default_bpp = 24,
|
||||
.xres = 800,
|
||||
.yres = 480,
|
||||
};
|
||||
|
||||
static struct fb_videomode smdkv310_lcd_timing = {
|
||||
.left_margin = 13,
|
||||
.right_margin = 8,
|
||||
.upper_margin = 7,
|
||||
.lower_margin = 5,
|
||||
.hsync_len = 3,
|
||||
.vsync_len = 1,
|
||||
.xres = 800,
|
||||
.yres = 480,
|
||||
};
|
||||
|
||||
static struct s3c_fb_platdata smdkv310_lcd0_pdata __initdata = {
|
||||
.win[0] = &smdkv310_fb_win0,
|
||||
.vtiming = &smdkv310_lcd_timing,
|
||||
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
|
||||
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
|
||||
.setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
|
||||
|
|
|
|||
|
|
@ -843,25 +843,29 @@ static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
|
|||
#else
|
||||
/* Frame Buffer */
|
||||
static struct s3c_fb_pd_win universal_fb_win0 = {
|
||||
.win_mode = {
|
||||
.left_margin = 16,
|
||||
.right_margin = 16,
|
||||
.upper_margin = 2,
|
||||
.lower_margin = 28,
|
||||
.hsync_len = 2,
|
||||
.vsync_len = 1,
|
||||
.xres = 480,
|
||||
.yres = 800,
|
||||
.refresh = 55,
|
||||
},
|
||||
.max_bpp = 32,
|
||||
.default_bpp = 16,
|
||||
.xres = 480,
|
||||
.yres = 800,
|
||||
.virtual_x = 480,
|
||||
.virtual_y = 2 * 800,
|
||||
};
|
||||
|
||||
static struct fb_videomode universal_lcd_timing = {
|
||||
.left_margin = 16,
|
||||
.right_margin = 16,
|
||||
.upper_margin = 2,
|
||||
.lower_margin = 28,
|
||||
.hsync_len = 2,
|
||||
.vsync_len = 1,
|
||||
.xres = 480,
|
||||
.yres = 800,
|
||||
.refresh = 55,
|
||||
};
|
||||
|
||||
static struct s3c_fb_platdata universal_lcd_pdata __initdata = {
|
||||
.win[0] = &universal_fb_win0,
|
||||
.vtiming = &universal_lcd_timing,
|
||||
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
|
||||
VIDCON0_CLKSEL_LCD,
|
||||
.vidcon1 = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
|
||||
|
|
|
|||
|
|
@ -1,9 +1,8 @@
|
|||
/* linux/arch/arm/mach-exynos4/pm.c
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
/*
|
||||
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4210 - Power Management support
|
||||
* EXYNOS - Power Management support
|
||||
*
|
||||
* Based on arch/arm/mach-s3c2410/pm.c
|
||||
* Copyright (c) 2006 Simtec Electronics
|
||||
|
|
@ -63,90 +62,7 @@ static struct sleep_save exynos4_vpll_save[] = {
|
|||
SAVE_ITEM(EXYNOS4_VPLL_CON1),
|
||||
};
|
||||
|
||||
static struct sleep_save exynos4_core_save[] = {
|
||||
/* GIC side */
|
||||
SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
|
||||
SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
|
||||
SAVE_ITEM(S5P_VA_GIC_CPU + 0x008),
|
||||
SAVE_ITEM(S5P_VA_GIC_CPU + 0x00C),
|
||||
SAVE_ITEM(S5P_VA_GIC_CPU + 0x014),
|
||||
SAVE_ITEM(S5P_VA_GIC_CPU + 0x018),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x000),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x004),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x100),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x104),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x108),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x300),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x304),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x308),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x400),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x404),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x408),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x40C),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x410),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x414),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x418),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x41C),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x420),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x424),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x428),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x42C),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x430),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x434),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x438),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x43C),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x440),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x444),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x448),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x44C),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x450),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x454),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x458),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x45C),
|
||||
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x800),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x804),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x808),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x80C),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x810),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x814),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x818),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x81C),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x820),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x824),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x828),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x82C),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x830),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x834),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x838),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x83C),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x840),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x844),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x848),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x84C),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x850),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x854),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x858),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x85C),
|
||||
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0xC00),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0xC04),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0xC08),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0xC0C),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0xC10),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0xC14),
|
||||
|
||||
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x000),
|
||||
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x010),
|
||||
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x020),
|
||||
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x030),
|
||||
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x040),
|
||||
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x050),
|
||||
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x060),
|
||||
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070),
|
||||
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080),
|
||||
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090),
|
||||
|
||||
static struct sleep_save exynos_core_save[] = {
|
||||
/* SROM side */
|
||||
SAVE_ITEM(S5P_SROM_BW),
|
||||
SAVE_ITEM(S5P_SROM_BC0),
|
||||
|
|
@ -159,9 +75,11 @@ static struct sleep_save exynos4_core_save[] = {
|
|||
/* For Cortex-A9 Diagnostic and Power control register */
|
||||
static unsigned int save_arm_register[2];
|
||||
|
||||
static int exynos4_cpu_suspend(unsigned long arg)
|
||||
static int exynos_cpu_suspend(unsigned long arg)
|
||||
{
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
outer_flush_all();
|
||||
#endif
|
||||
|
||||
/* issue the standby signal into the pm unit. */
|
||||
cpu_do_idle();
|
||||
|
|
@ -170,19 +88,25 @@ static int exynos4_cpu_suspend(unsigned long arg)
|
|||
panic("sleep resumed to originator?");
|
||||
}
|
||||
|
||||
static void exynos4_pm_prepare(void)
|
||||
static void exynos_pm_prepare(void)
|
||||
{
|
||||
u32 tmp;
|
||||
unsigned int tmp;
|
||||
|
||||
s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
|
||||
s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
|
||||
s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
|
||||
s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
|
||||
|
||||
tmp = __raw_readl(S5P_INFORM1);
|
||||
if (!soc_is_exynos5250()) {
|
||||
s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
|
||||
s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
|
||||
} else {
|
||||
/* Disable USE_RETENTION of JPEG_MEM_OPTION */
|
||||
tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
|
||||
tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
|
||||
__raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
|
||||
}
|
||||
|
||||
/* Set value of power down register for sleep mode */
|
||||
|
||||
exynos4_sys_powerdown_conf(SYS_SLEEP);
|
||||
exynos_sys_powerdown_conf(SYS_SLEEP);
|
||||
__raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
|
||||
|
||||
/* ensure at least INFORM0 has the resume address */
|
||||
|
|
@ -191,17 +115,18 @@ static void exynos4_pm_prepare(void)
|
|||
|
||||
/* Before enter central sequence mode, clock src register have to set */
|
||||
|
||||
s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
|
||||
if (!soc_is_exynos5250())
|
||||
s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
|
||||
|
||||
if (soc_is_exynos4210())
|
||||
s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
|
||||
|
||||
}
|
||||
|
||||
static int exynos4_pm_add(struct device *dev, struct subsys_interface *sif)
|
||||
static int exynos_pm_add(struct device *dev, struct subsys_interface *sif)
|
||||
{
|
||||
pm_cpu_prep = exynos4_pm_prepare;
|
||||
pm_cpu_sleep = exynos4_cpu_suspend;
|
||||
pm_cpu_prep = exynos_pm_prepare;
|
||||
pm_cpu_sleep = exynos_cpu_suspend;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -273,13 +198,13 @@ static void exynos4_restore_pll(void)
|
|||
} while (epll_wait || vpll_wait);
|
||||
}
|
||||
|
||||
static struct subsys_interface exynos4_pm_interface = {
|
||||
.name = "exynos4_pm",
|
||||
static struct subsys_interface exynos_pm_interface = {
|
||||
.name = "exynos_pm",
|
||||
.subsys = &exynos_subsys,
|
||||
.add_dev = exynos4_pm_add,
|
||||
.add_dev = exynos_pm_add,
|
||||
};
|
||||
|
||||
static __init int exynos4_pm_drvinit(void)
|
||||
static __init int exynos_pm_drvinit(void)
|
||||
{
|
||||
struct clk *pll_base;
|
||||
unsigned int tmp;
|
||||
|
|
@ -292,18 +217,20 @@ static __init int exynos4_pm_drvinit(void)
|
|||
tmp |= ((0xFF << 8) | (0x1F << 1));
|
||||
__raw_writel(tmp, S5P_WAKEUP_MASK);
|
||||
|
||||
pll_base = clk_get(NULL, "xtal");
|
||||
if (!soc_is_exynos5250()) {
|
||||
pll_base = clk_get(NULL, "xtal");
|
||||
|
||||
if (!IS_ERR(pll_base)) {
|
||||
pll_base_rate = clk_get_rate(pll_base);
|
||||
clk_put(pll_base);
|
||||
if (!IS_ERR(pll_base)) {
|
||||
pll_base_rate = clk_get_rate(pll_base);
|
||||
clk_put(pll_base);
|
||||
}
|
||||
}
|
||||
|
||||
return subsys_interface_register(&exynos4_pm_interface);
|
||||
return subsys_interface_register(&exynos_pm_interface);
|
||||
}
|
||||
arch_initcall(exynos4_pm_drvinit);
|
||||
arch_initcall(exynos_pm_drvinit);
|
||||
|
||||
static int exynos4_pm_suspend(void)
|
||||
static int exynos_pm_suspend(void)
|
||||
{
|
||||
unsigned long tmp;
|
||||
|
||||
|
|
@ -313,27 +240,27 @@ static int exynos4_pm_suspend(void)
|
|||
tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
|
||||
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
|
||||
|
||||
if (soc_is_exynos4212() || soc_is_exynos4412()) {
|
||||
tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
|
||||
tmp &= ~(S5P_USE_STANDBYWFI_ISP_ARM |
|
||||
S5P_USE_STANDBYWFE_ISP_ARM);
|
||||
__raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
|
||||
/* Setting SEQ_OPTION register */
|
||||
|
||||
tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
|
||||
__raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
|
||||
|
||||
if (!soc_is_exynos5250()) {
|
||||
/* Save Power control register */
|
||||
asm ("mrc p15, 0, %0, c15, c0, 0"
|
||||
: "=r" (tmp) : : "cc");
|
||||
save_arm_register[0] = tmp;
|
||||
|
||||
/* Save Diagnostic register */
|
||||
asm ("mrc p15, 0, %0, c15, c0, 1"
|
||||
: "=r" (tmp) : : "cc");
|
||||
save_arm_register[1] = tmp;
|
||||
}
|
||||
|
||||
/* Save Power control register */
|
||||
asm ("mrc p15, 0, %0, c15, c0, 0"
|
||||
: "=r" (tmp) : : "cc");
|
||||
save_arm_register[0] = tmp;
|
||||
|
||||
/* Save Diagnostic register */
|
||||
asm ("mrc p15, 0, %0, c15, c0, 1"
|
||||
: "=r" (tmp) : : "cc");
|
||||
save_arm_register[1] = tmp;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void exynos4_pm_resume(void)
|
||||
static void exynos_pm_resume(void)
|
||||
{
|
||||
unsigned long tmp;
|
||||
|
||||
|
|
@ -350,17 +277,19 @@ static void exynos4_pm_resume(void)
|
|||
/* No need to perform below restore code */
|
||||
goto early_wakeup;
|
||||
}
|
||||
/* Restore Power control register */
|
||||
tmp = save_arm_register[0];
|
||||
asm volatile ("mcr p15, 0, %0, c15, c0, 0"
|
||||
: : "r" (tmp)
|
||||
: "cc");
|
||||
if (!soc_is_exynos5250()) {
|
||||
/* Restore Power control register */
|
||||
tmp = save_arm_register[0];
|
||||
asm volatile ("mcr p15, 0, %0, c15, c0, 0"
|
||||
: : "r" (tmp)
|
||||
: "cc");
|
||||
|
||||
/* Restore Diagnostic register */
|
||||
tmp = save_arm_register[1];
|
||||
asm volatile ("mcr p15, 0, %0, c15, c0, 1"
|
||||
: : "r" (tmp)
|
||||
: "cc");
|
||||
/* Restore Diagnostic register */
|
||||
tmp = save_arm_register[1];
|
||||
asm volatile ("mcr p15, 0, %0, c15, c0, 1"
|
||||
: : "r" (tmp)
|
||||
: "cc");
|
||||
}
|
||||
|
||||
/* For release retention */
|
||||
|
||||
|
|
@ -372,26 +301,28 @@ static void exynos4_pm_resume(void)
|
|||
__raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
|
||||
__raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
|
||||
|
||||
s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
|
||||
s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
|
||||
|
||||
exynos4_restore_pll();
|
||||
if (!soc_is_exynos5250()) {
|
||||
exynos4_restore_pll();
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
scu_enable(S5P_VA_SCU);
|
||||
scu_enable(S5P_VA_SCU);
|
||||
#endif
|
||||
}
|
||||
|
||||
early_wakeup:
|
||||
return;
|
||||
}
|
||||
|
||||
static struct syscore_ops exynos4_pm_syscore_ops = {
|
||||
.suspend = exynos4_pm_suspend,
|
||||
.resume = exynos4_pm_resume,
|
||||
static struct syscore_ops exynos_pm_syscore_ops = {
|
||||
.suspend = exynos_pm_suspend,
|
||||
.resume = exynos_pm_resume,
|
||||
};
|
||||
|
||||
static __init int exynos4_pm_syscore_init(void)
|
||||
static __init int exynos_pm_syscore_init(void)
|
||||
{
|
||||
register_syscore_ops(&exynos4_pm_syscore_ops);
|
||||
register_syscore_ops(&exynos_pm_syscore_ops);
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(exynos4_pm_syscore_init);
|
||||
arch_initcall(exynos_pm_syscore_init);
|
||||
|
|
|
|||
|
|
@ -1,9 +1,8 @@
|
|||
/* linux/arch/arm/mach-exynos4/pmu.c
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
/*
|
||||
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* EXYNOS4210 - CPU PMU(Power Management Unit) support
|
||||
* EXYNOS - CPU PMU(Power Management Unit) support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
|
@ -12,13 +11,14 @@
|
|||
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/bug.h>
|
||||
|
||||
#include <mach/regs-clock.h>
|
||||
#include <mach/pmu.h>
|
||||
|
||||
static struct exynos4_pmu_conf *exynos4_pmu_config;
|
||||
static struct exynos_pmu_conf *exynos_pmu_config;
|
||||
|
||||
static struct exynos4_pmu_conf exynos4210_pmu_config[] = {
|
||||
static struct exynos_pmu_conf exynos4210_pmu_config[] = {
|
||||
/* { .reg = address, .val = { AFTR, LPA, SLEEP } */
|
||||
{ S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
|
||||
{ S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
|
||||
|
|
@ -94,7 +94,7 @@ static struct exynos4_pmu_conf exynos4210_pmu_config[] = {
|
|||
{ PMU_TABLE_END,},
|
||||
};
|
||||
|
||||
static struct exynos4_pmu_conf exynos4x12_pmu_config[] = {
|
||||
static struct exynos_pmu_conf exynos4x12_pmu_config[] = {
|
||||
{ S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
|
||||
{ S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
|
||||
{ S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
|
||||
|
|
@ -202,7 +202,7 @@ static struct exynos4_pmu_conf exynos4x12_pmu_config[] = {
|
|||
{ PMU_TABLE_END,},
|
||||
};
|
||||
|
||||
static struct exynos4_pmu_conf exynos4412_pmu_config[] = {
|
||||
static struct exynos_pmu_conf exynos4412_pmu_config[] = {
|
||||
{ S5P_ARM_CORE2_LOWPWR, { 0x0, 0x0, 0x2 } },
|
||||
{ S5P_DIS_IRQ_CORE2, { 0x0, 0x0, 0x0 } },
|
||||
{ S5P_DIS_IRQ_CENTRAL2, { 0x0, 0x0, 0x0 } },
|
||||
|
|
@ -212,13 +212,174 @@ static struct exynos4_pmu_conf exynos4412_pmu_config[] = {
|
|||
{ PMU_TABLE_END,},
|
||||
};
|
||||
|
||||
void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
|
||||
static struct exynos_pmu_conf exynos5250_pmu_config[] = {
|
||||
/* { .reg = address, .val = { AFTR, LPA, SLEEP } */
|
||||
{ EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
|
||||
{ EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
||||
{ EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
||||
{ EXYNOS5_ARM_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
|
||||
{ EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
||||
{ EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
||||
{ EXYNOS5_FSYS_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
||||
{ EXYNOS5_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
||||
{ EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
||||
{ EXYNOS5_ARM_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
|
||||
{ EXYNOS5_ARM_L2_SYS_PWR_REG, { 0x3, 0x3, 0x3} },
|
||||
{ EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
||||
{ EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
||||
{ EXYNOS5_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
||||
{ EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
||||
{ EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
||||
{ EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
||||
{ EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
||||
{ EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
||||
{ EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
||||
{ EXYNOS5_APLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
||||
{ EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_TOP_BUS_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
||||
{ EXYNOS5_TOP_RETENTION_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
||||
{ EXYNOS5_TOP_PWR_SYS_PWR_REG, { 0x3, 0x0, 0x3} },
|
||||
{ EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
||||
{ EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
||||
{ EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x3} },
|
||||
{ EXYNOS5_LOGIC_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
||||
{ EXYNOS5_OSCCLK_GATE_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
||||
{ EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
||||
{ EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
||||
{ EXYNOS5_USBOTG_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
||||
{ EXYNOS5_G2D_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
||||
{ EXYNOS5_USBDRD_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
||||
{ EXYNOS5_SDMMC_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
||||
{ EXYNOS5_CSSYS_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
||||
{ EXYNOS5_SECSS_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
||||
{ EXYNOS5_ROTATOR_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
||||
{ EXYNOS5_INTRAM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
||||
{ EXYNOS5_INTROM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
||||
{ EXYNOS5_JPEG_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
||||
{ EXYNOS5_HSI_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
||||
{ EXYNOS5_MCUIOP_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
||||
{ EXYNOS5_SATA_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
||||
{ EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
||||
{ EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_PAD_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_XUSBXTI_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
||||
{ EXYNOS5_XXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
||||
{ EXYNOS5_EXT_REGULATOR_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
||||
{ EXYNOS5_GPIO_MODE_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
||||
{ EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
||||
{ EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
||||
{ EXYNOS5_GSCL_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
||||
{ EXYNOS5_ISP_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
||||
{ EXYNOS5_MFC_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
||||
{ EXYNOS5_G3D_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
||||
{ EXYNOS5_DISP1_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
||||
{ EXYNOS5_MAU_SYS_PWR_REG, { 0x7, 0x7, 0x0} },
|
||||
{ EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
||||
{ EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
||||
{ EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||
{ EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
||||
{ PMU_TABLE_END,},
|
||||
};
|
||||
|
||||
void __iomem *exynos5_list_both_cnt_feed[] = {
|
||||
EXYNOS5_ARM_CORE0_OPTION,
|
||||
EXYNOS5_ARM_CORE1_OPTION,
|
||||
EXYNOS5_ARM_COMMON_OPTION,
|
||||
EXYNOS5_GSCL_OPTION,
|
||||
EXYNOS5_ISP_OPTION,
|
||||
EXYNOS5_MFC_OPTION,
|
||||
EXYNOS5_G3D_OPTION,
|
||||
EXYNOS5_DISP1_OPTION,
|
||||
EXYNOS5_MAU_OPTION,
|
||||
EXYNOS5_TOP_PWR_OPTION,
|
||||
EXYNOS5_TOP_PWR_SYSMEM_OPTION,
|
||||
};
|
||||
|
||||
void __iomem *exynos5_list_diable_wfi_wfe[] = {
|
||||
EXYNOS5_ARM_CORE1_OPTION,
|
||||
EXYNOS5_FSYS_ARM_OPTION,
|
||||
EXYNOS5_ISP_ARM_OPTION,
|
||||
};
|
||||
|
||||
static void exynos5_init_pmu(void)
|
||||
{
|
||||
unsigned int i;
|
||||
unsigned int tmp;
|
||||
|
||||
/*
|
||||
* Enable both SC_FEEDBACK and SC_COUNTER
|
||||
*/
|
||||
for (i = 0 ; i < ARRAY_SIZE(exynos5_list_both_cnt_feed) ; i++) {
|
||||
tmp = __raw_readl(exynos5_list_both_cnt_feed[i]);
|
||||
tmp |= (EXYNOS5_USE_SC_FEEDBACK |
|
||||
EXYNOS5_USE_SC_COUNTER);
|
||||
__raw_writel(tmp, exynos5_list_both_cnt_feed[i]);
|
||||
}
|
||||
|
||||
/*
|
||||
* SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable
|
||||
* MANUAL_L2RSTDISABLE_CONTROL_BITFIELD Enable
|
||||
*/
|
||||
tmp = __raw_readl(EXYNOS5_ARM_COMMON_OPTION);
|
||||
tmp |= (EXYNOS5_MANUAL_L2RSTDISABLE_CONTROL |
|
||||
EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN);
|
||||
__raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION);
|
||||
|
||||
/*
|
||||
* Disable WFI/WFE on XXX_OPTION
|
||||
*/
|
||||
for (i = 0 ; i < ARRAY_SIZE(exynos5_list_diable_wfi_wfe) ; i++) {
|
||||
tmp = __raw_readl(exynos5_list_diable_wfi_wfe[i]);
|
||||
tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE |
|
||||
EXYNOS5_OPTION_USE_STANDBYWFI);
|
||||
__raw_writel(tmp, exynos5_list_diable_wfi_wfe[i]);
|
||||
}
|
||||
}
|
||||
|
||||
void exynos_sys_powerdown_conf(enum sys_powerdown mode)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; (exynos4_pmu_config[i].reg != PMU_TABLE_END) ; i++)
|
||||
__raw_writel(exynos4_pmu_config[i].val[mode],
|
||||
exynos4_pmu_config[i].reg);
|
||||
if (soc_is_exynos5250())
|
||||
exynos5_init_pmu();
|
||||
|
||||
for (i = 0; (exynos_pmu_config[i].reg != PMU_TABLE_END) ; i++)
|
||||
__raw_writel(exynos_pmu_config[i].val[mode],
|
||||
exynos_pmu_config[i].reg);
|
||||
|
||||
if (soc_is_exynos4412()) {
|
||||
for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++)
|
||||
|
|
@ -227,20 +388,23 @@ void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
|
|||
}
|
||||
}
|
||||
|
||||
static int __init exynos4_pmu_init(void)
|
||||
static int __init exynos_pmu_init(void)
|
||||
{
|
||||
exynos4_pmu_config = exynos4210_pmu_config;
|
||||
exynos_pmu_config = exynos4210_pmu_config;
|
||||
|
||||
if (soc_is_exynos4210()) {
|
||||
exynos4_pmu_config = exynos4210_pmu_config;
|
||||
exynos_pmu_config = exynos4210_pmu_config;
|
||||
pr_info("EXYNOS4210 PMU Initialize\n");
|
||||
} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
|
||||
exynos4_pmu_config = exynos4x12_pmu_config;
|
||||
exynos_pmu_config = exynos4x12_pmu_config;
|
||||
pr_info("EXYNOS4x12 PMU Initialize\n");
|
||||
} else if (soc_is_exynos5250()) {
|
||||
exynos_pmu_config = exynos5250_pmu_config;
|
||||
pr_info("EXYNOS5250 PMU Initialize\n");
|
||||
} else {
|
||||
pr_info("EXYNOS4: PMU not supported\n");
|
||||
pr_info("EXYNOS: PMU not supported\n");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(exynos4_pmu_init);
|
||||
arch_initcall(exynos_pmu_init);
|
||||
|
|
|
|||
|
|
@ -1,4 +1,8 @@
|
|||
obj-y := clock.o highbank.o system.o
|
||||
obj-y := clock.o highbank.o system.o smc.o
|
||||
|
||||
plus_sec := $(call as-instr,.arch_extension sec,+sec)
|
||||
AFLAGS_smc.o :=-Wa,-march=armv7-a$(plus_sec)
|
||||
|
||||
obj-$(CONFIG_DEBUG_HIGHBANK_UART) += lluart.o
|
||||
obj-$(CONFIG_SMP) += platsmp.o
|
||||
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
||||
|
|
|
|||
|
|
@ -8,3 +8,4 @@ extern void highbank_lluart_map_io(void);
|
|||
static inline void highbank_lluart_map_io(void) {}
|
||||
#endif
|
||||
|
||||
extern void highbank_smc1(int fn, int arg);
|
||||
|
|
|
|||
|
|
@ -85,10 +85,24 @@ const static struct of_device_id irq_match[] = {
|
|||
{}
|
||||
};
|
||||
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
static void highbank_l2x0_disable(void)
|
||||
{
|
||||
/* Disable PL310 L2 Cache controller */
|
||||
highbank_smc1(0x102, 0x0);
|
||||
}
|
||||
#endif
|
||||
|
||||
static void __init highbank_init_irq(void)
|
||||
{
|
||||
of_irq_init(irq_match);
|
||||
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
/* Enable PL310 L2 Cache controller */
|
||||
highbank_smc1(0x102, 0x1);
|
||||
l2x0_of_init(0, ~0UL);
|
||||
outer_cache.disable = highbank_l2x0_disable;
|
||||
#endif
|
||||
}
|
||||
|
||||
static void __init highbank_timer_init(void)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,27 @@
|
|||
/*
|
||||
* Copied from omap44xx-smc.S Copyright (C) 2010 Texas Instruments, Inc.
|
||||
* Copyright 2012 Calxeda, Inc.
|
||||
*
|
||||
* This program is free software,you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/linkage.h>
|
||||
|
||||
/*
|
||||
* This is common routine to manage secure monitor API
|
||||
* used to modify the PL310 secure registers.
|
||||
* 'r0' contains the value to be modified and 'r12' contains
|
||||
* the monitor API number.
|
||||
* Function signature : void highbank_smc1(u32 fn, u32 arg)
|
||||
*/
|
||||
|
||||
ENTRY(highbank_smc1)
|
||||
stmfd sp!, {r4-r11, lr}
|
||||
mov r12, r0
|
||||
mov r0, r1
|
||||
dsb
|
||||
smc #0
|
||||
ldmfd sp!, {r4-r11, pc}
|
||||
ENDPROC(highbank_smc1)
|
||||
|
|
@ -477,6 +477,7 @@ config MACH_MX31_3DS
|
|||
select IMX_HAVE_PLATFORM_IMX2_WDT
|
||||
select IMX_HAVE_PLATFORM_IMX_I2C
|
||||
select IMX_HAVE_PLATFORM_IMX_KEYPAD
|
||||
select IMX_HAVE_PLATFORM_IMX_SSI
|
||||
select IMX_HAVE_PLATFORM_IMX_UART
|
||||
select IMX_HAVE_PLATFORM_IPU_CORE
|
||||
select IMX_HAVE_PLATFORM_MXC_EHCI
|
||||
|
|
|
|||
|
|
@ -108,8 +108,7 @@ int __init mx1_clocks_init(unsigned long fref)
|
|||
clk_register_clkdev(clk[clk32], NULL, "mxc_rtc.0");
|
||||
clk_register_clkdev(clk[clko], "clko", NULL);
|
||||
|
||||
mxc_timer_init(NULL, MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR),
|
||||
MX1_TIM1_INT);
|
||||
mxc_timer_init(MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR), MX1_TIM1_INT);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -180,7 +180,7 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href)
|
|||
clk_register_clkdev(clk[sdhc1_ipg_gate], "sdhc1", NULL);
|
||||
clk_register_clkdev(clk[sdhc2_ipg_gate], "sdhc2", NULL);
|
||||
|
||||
mxc_timer_init(NULL, MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR),
|
||||
MX21_INT_GPT1);
|
||||
mxc_timer_init(MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR), MX21_INT_GPT1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -243,6 +243,6 @@ int __init mx25_clocks_init(void)
|
|||
clk_register_clkdev(clk[sdma_ahb], "ahb", "imx35-sdma");
|
||||
clk_register_clkdev(clk[iim_ipg], "iim", NULL);
|
||||
|
||||
mxc_timer_init(NULL, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
|
||||
mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -263,8 +263,7 @@ int __init mx27_clocks_init(unsigned long fref)
|
|||
clk_register_clkdev(clk[ssi1_baud_gate], "bitrate" , "imx-ssi.0");
|
||||
clk_register_clkdev(clk[ssi2_baud_gate], "bitrate" , "imx-ssi.1");
|
||||
|
||||
mxc_timer_init(NULL, MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR),
|
||||
MX27_INT_GPT1);
|
||||
mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
|
||||
|
||||
clk_prepare_enable(clk[emi_ahb_gate]);
|
||||
|
||||
|
|
|
|||
|
|
@ -175,8 +175,7 @@ int __init mx31_clocks_init(unsigned long fref)
|
|||
mx31_revision();
|
||||
clk_disable_unprepare(clk[iim_gate]);
|
||||
|
||||
mxc_timer_init(NULL, MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR),
|
||||
MX31_INT_GPT);
|
||||
mxc_timer_init(MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR), MX31_INT_GPT);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -267,11 +267,9 @@ int __init mx35_clocks_init()
|
|||
imx_print_silicon_rev("i.MX35", mx35_revision());
|
||||
|
||||
#ifdef CONFIG_MXC_USE_EPIT
|
||||
epit_timer_init(&epit1_clk,
|
||||
MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1);
|
||||
epit_timer_init(MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1);
|
||||
#else
|
||||
mxc_timer_init(NULL, MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR),
|
||||
MX35_INT_GPT);
|
||||
mxc_timer_init(MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -104,12 +104,12 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
|
|||
periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
|
||||
clk[main_bus] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
|
||||
main_bus_sel, ARRAY_SIZE(main_bus_sel));
|
||||
clk[per_lp_apm] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCDR, 1, 1,
|
||||
clk[per_lp_apm] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1,
|
||||
per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
|
||||
clk[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
|
||||
clk[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3);
|
||||
clk[per_podf] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3);
|
||||
clk[per_root] = imx_clk_mux("per_root", MXC_CCM_CBCDR, 1, 0,
|
||||
clk[per_root] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1,
|
||||
per_root_sel, ARRAY_SIZE(per_root_sel));
|
||||
clk[ahb] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3);
|
||||
clk[ahb_max] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28);
|
||||
|
|
@ -172,7 +172,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
|
|||
clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "ipg", MXC_CCM_CCGR2, 12);
|
||||
clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
|
||||
clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "ipg", MXC_CCM_CCGR2, 16);
|
||||
clk[gpt_gate] = imx_clk_gate2("gpt_gate", "ipg", MXC_CCM_CCGR2, 18);
|
||||
clk[gpt_gate] = imx_clk_gate2("gpt_gate", "per_root", MXC_CCM_CCGR2, 18);
|
||||
clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
|
||||
clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
|
||||
clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
|
||||
|
|
@ -366,8 +366,7 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
|
|||
clk_set_rate(clk[esdhc_b_podf], 166250000);
|
||||
|
||||
/* System timer */
|
||||
mxc_timer_init(NULL, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
|
||||
MX51_INT_GPT);
|
||||
mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT);
|
||||
|
||||
clk_prepare_enable(clk[iim_gate]);
|
||||
imx_print_silicon_rev("i.MX51", mx51_revision());
|
||||
|
|
@ -452,8 +451,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
|
|||
clk_set_rate(clk[esdhc_b_podf], 200000000);
|
||||
|
||||
/* System timer */
|
||||
mxc_timer_init(NULL, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
|
||||
MX53_INT_GPT);
|
||||
mxc_timer_init(MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), MX53_INT_GPT);
|
||||
|
||||
clk_prepare_enable(clk[iim_gate]);
|
||||
imx_print_silicon_rev("i.MX53", mx53_revision());
|
||||
|
|
|
|||
|
|
@ -122,10 +122,6 @@ static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5
|
|||
"dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0",
|
||||
"ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio", };
|
||||
|
||||
static const char * const clks_init_on[] __initconst = {
|
||||
"mmdc_ch0_axi", "mmdc_ch1_axi", "usboh3",
|
||||
};
|
||||
|
||||
enum mx6q_clks {
|
||||
dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
|
||||
pll3_pfd0_720m, pll3_pfd1_540m, pll3_pfd2_508m, pll3_pfd3_454m,
|
||||
|
|
@ -161,11 +157,14 @@ enum mx6q_clks {
|
|||
|
||||
static struct clk *clk[clk_max];
|
||||
|
||||
static enum mx6q_clks const clks_init_on[] __initconst = {
|
||||
mmdc_ch0_axi, mmdc_ch1_axi,
|
||||
};
|
||||
|
||||
int __init mx6q_clocks_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
void __iomem *base;
|
||||
struct clk *c;
|
||||
int i, irq;
|
||||
|
||||
clk[dummy] = imx_clk_fixed("dummy", 0);
|
||||
|
|
@ -424,21 +423,14 @@ int __init mx6q_clocks_init(void)
|
|||
clk_register_clkdev(clk[ahb], "ahb", NULL);
|
||||
clk_register_clkdev(clk[cko1], "cko1", NULL);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) {
|
||||
c = clk_get_sys(clks_init_on[i], NULL);
|
||||
if (IS_ERR(c)) {
|
||||
pr_err("%s: failed to get clk %s", __func__,
|
||||
clks_init_on[i]);
|
||||
return PTR_ERR(c);
|
||||
}
|
||||
clk_prepare_enable(c);
|
||||
}
|
||||
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
|
||||
clk_prepare_enable(clk[clks_init_on[i]]);
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
|
||||
base = of_iomap(np, 0);
|
||||
WARN_ON(!base);
|
||||
irq = irq_of_parse_and_map(np, 0);
|
||||
mxc_timer_init(NULL, base, irq);
|
||||
mxc_timer_init(base, irq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -74,30 +74,15 @@ struct clk_pllv2 {
|
|||
void __iomem *base;
|
||||
};
|
||||
|
||||
static unsigned long clk_pllv2_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
static unsigned long __clk_pllv2_recalc_rate(unsigned long parent_rate,
|
||||
u32 dp_ctl, u32 dp_op, u32 dp_mfd, u32 dp_mfn)
|
||||
{
|
||||
long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
|
||||
unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
|
||||
void __iomem *pllbase;
|
||||
unsigned long dbl;
|
||||
s64 temp;
|
||||
struct clk_pllv2 *pll = to_clk_pllv2(hw);
|
||||
|
||||
pllbase = pll->base;
|
||||
|
||||
dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
|
||||
pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
|
||||
dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
|
||||
|
||||
if (pll_hfsm == 0) {
|
||||
dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
|
||||
dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
|
||||
dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
|
||||
} else {
|
||||
dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
|
||||
dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
|
||||
dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
|
||||
}
|
||||
pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
|
||||
mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
|
||||
mfi = (mfi <= 5) ? 5 : mfi;
|
||||
|
|
@ -123,18 +108,30 @@ static unsigned long clk_pllv2_recalc_rate(struct clk_hw *hw,
|
|||
return temp;
|
||||
}
|
||||
|
||||
static int clk_pllv2_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
static unsigned long clk_pllv2_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_pllv2 *pll = to_clk_pllv2(hw);
|
||||
u32 reg;
|
||||
u32 dp_op, dp_mfd, dp_mfn, dp_ctl;
|
||||
void __iomem *pllbase;
|
||||
struct clk_pllv2 *pll = to_clk_pllv2(hw);
|
||||
|
||||
pllbase = pll->base;
|
||||
|
||||
dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
|
||||
dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
|
||||
dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
|
||||
dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
|
||||
|
||||
return __clk_pllv2_recalc_rate(parent_rate, dp_ctl, dp_op, dp_mfd, dp_mfn);
|
||||
}
|
||||
|
||||
static int __clk_pllv2_set_rate(unsigned long rate, unsigned long parent_rate,
|
||||
u32 *dp_op, u32 *dp_mfd, u32 *dp_mfn)
|
||||
{
|
||||
u32 reg;
|
||||
long mfi, pdf, mfn, mfd = 999999;
|
||||
s64 temp64;
|
||||
unsigned long quad_parent_rate;
|
||||
unsigned long pll_hfsm, dp_ctl;
|
||||
|
||||
pllbase = pll->base;
|
||||
|
||||
quad_parent_rate = 4 * parent_rate;
|
||||
pdf = mfi = -1;
|
||||
|
|
@ -144,25 +141,41 @@ static int clk_pllv2_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
return -EINVAL;
|
||||
pdf--;
|
||||
|
||||
temp64 = rate * (pdf+1) - quad_parent_rate * mfi;
|
||||
do_div(temp64, quad_parent_rate/1000000);
|
||||
temp64 = rate * (pdf + 1) - quad_parent_rate * mfi;
|
||||
do_div(temp64, quad_parent_rate / 1000000);
|
||||
mfn = (long)temp64;
|
||||
|
||||
reg = mfi << 4 | pdf;
|
||||
|
||||
*dp_op = reg;
|
||||
*dp_mfd = mfd;
|
||||
*dp_mfn = mfn;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int clk_pllv2_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_pllv2 *pll = to_clk_pllv2(hw);
|
||||
void __iomem *pllbase;
|
||||
u32 dp_ctl, dp_op, dp_mfd, dp_mfn;
|
||||
int ret;
|
||||
|
||||
pllbase = pll->base;
|
||||
|
||||
|
||||
ret = __clk_pllv2_set_rate(rate, parent_rate, &dp_op, &dp_mfd, &dp_mfn);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
|
||||
/* use dpdck0_2 */
|
||||
__raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
|
||||
pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
|
||||
if (pll_hfsm == 0) {
|
||||
reg = mfi << 4 | pdf;
|
||||
__raw_writel(reg, pllbase + MXC_PLL_DP_OP);
|
||||
__raw_writel(mfd, pllbase + MXC_PLL_DP_MFD);
|
||||
__raw_writel(mfn, pllbase + MXC_PLL_DP_MFN);
|
||||
} else {
|
||||
reg = mfi << 4 | pdf;
|
||||
__raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP);
|
||||
__raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD);
|
||||
__raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN);
|
||||
}
|
||||
|
||||
__raw_writel(dp_op, pllbase + MXC_PLL_DP_OP);
|
||||
__raw_writel(dp_mfd, pllbase + MXC_PLL_DP_MFD);
|
||||
__raw_writel(dp_mfn, pllbase + MXC_PLL_DP_MFN);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -170,7 +183,11 @@ static int clk_pllv2_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
static long clk_pllv2_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
return rate;
|
||||
u32 dp_op, dp_mfd, dp_mfn;
|
||||
|
||||
__clk_pllv2_set_rate(rate, *prate, &dp_op, &dp_mfd, &dp_mfn);
|
||||
return __clk_pllv2_recalc_rate(*prate, MXC_PLL_DP_CTL_DPDCK0_2_EN,
|
||||
dp_op, dp_mfd, dp_mfn);
|
||||
}
|
||||
|
||||
static int clk_pllv2_prepare(struct clk_hw *hw)
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@
|
|||
#define MX53_DPLL1_BASE MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR)
|
||||
#define MX53_DPLL2_BASE MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR)
|
||||
#define MX53_DPLL3_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
|
||||
#define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
|
||||
#define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL4_BASE_ADDR)
|
||||
|
||||
/* PLL Register Offsets */
|
||||
#define MXC_PLL_DP_CTL 0x00
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
|
||||
#include <linux/errno.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/cp15.h>
|
||||
#include <mach/common.h>
|
||||
|
||||
int platform_cpu_kill(unsigned int cpu)
|
||||
|
|
@ -19,6 +20,44 @@ int platform_cpu_kill(unsigned int cpu)
|
|||
return 1;
|
||||
}
|
||||
|
||||
static inline void cpu_enter_lowpower(void)
|
||||
{
|
||||
unsigned int v;
|
||||
|
||||
flush_cache_all();
|
||||
asm volatile(
|
||||
"mcr p15, 0, %1, c7, c5, 0\n"
|
||||
" mcr p15, 0, %1, c7, c10, 4\n"
|
||||
/*
|
||||
* Turn off coherency
|
||||
*/
|
||||
" mrc p15, 0, %0, c1, c0, 1\n"
|
||||
" bic %0, %0, %3\n"
|
||||
" mcr p15, 0, %0, c1, c0, 1\n"
|
||||
" mrc p15, 0, %0, c1, c0, 0\n"
|
||||
" bic %0, %0, %2\n"
|
||||
" mcr p15, 0, %0, c1, c0, 0\n"
|
||||
: "=&r" (v)
|
||||
: "r" (0), "Ir" (CR_C), "Ir" (0x40)
|
||||
: "cc");
|
||||
}
|
||||
|
||||
static inline void cpu_leave_lowpower(void)
|
||||
{
|
||||
unsigned int v;
|
||||
|
||||
asm volatile(
|
||||
"mrc p15, 0, %0, c1, c0, 0\n"
|
||||
" orr %0, %0, %1\n"
|
||||
" mcr p15, 0, %0, c1, c0, 0\n"
|
||||
" mrc p15, 0, %0, c1, c0, 1\n"
|
||||
" orr %0, %0, %2\n"
|
||||
" mcr p15, 0, %0, c1, c0, 1\n"
|
||||
: "=&r" (v)
|
||||
: "Ir" (CR_C), "Ir" (0x40)
|
||||
: "cc");
|
||||
}
|
||||
|
||||
/*
|
||||
* platform-specific code to shutdown a CPU
|
||||
*
|
||||
|
|
@ -26,9 +65,10 @@ int platform_cpu_kill(unsigned int cpu)
|
|||
*/
|
||||
void platform_cpu_die(unsigned int cpu)
|
||||
{
|
||||
flush_cache_all();
|
||||
cpu_enter_lowpower();
|
||||
imx_enable_cpu(cpu, false);
|
||||
cpu_do_idle();
|
||||
cpu_leave_lowpower();
|
||||
|
||||
/* We should never return from idle */
|
||||
panic("cpu %d unexpectedly exit from shutdown\n", cpu);
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@ static const struct of_dev_auxdata imx27_auxdata_lookup[] __initconst = {
|
|||
OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI2_BASE_ADDR, "imx27-cspi.1", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI3_BASE_ADDR, "imx27-cspi.2", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx27-wdt", MX27_WDOG_BASE_ADDR, "imx2-wdt.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx27-nand", MX27_NFC_BASE_ADDR, "mxc_nand.0", NULL),
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -70,7 +70,6 @@ static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
|
|||
I2C_BOARD_INFO("pcf8563", 0x51),
|
||||
}, {
|
||||
I2C_BOARD_INFO("tsc2007", 0x48),
|
||||
.type = "tsc2007",
|
||||
.platform_data = &tsc2007_info,
|
||||
.irq = IMX_GPIO_TO_IRQ(TSC2007_IRQGPIO),
|
||||
},
|
||||
|
|
|
|||
|
|
@ -142,7 +142,6 @@ static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
|
|||
I2C_BOARD_INFO("pcf8563", 0x51),
|
||||
}, {
|
||||
I2C_BOARD_INFO("tsc2007", 0x49),
|
||||
.type = "tsc2007",
|
||||
.platform_data = &tsc2007_info,
|
||||
},
|
||||
};
|
||||
|
|
|
|||
|
|
@ -116,6 +116,8 @@ static const int visstrim_m10_pins[] __initconst = {
|
|||
PB23_PF_USB_PWR,
|
||||
PB24_PF_USB_OC,
|
||||
/* CSI */
|
||||
TVP5150_RSTN | GPIO_GPIO | GPIO_OUT,
|
||||
TVP5150_PWDN | GPIO_GPIO | GPIO_OUT,
|
||||
PB10_PF_CSI_D0,
|
||||
PB11_PF_CSI_D1,
|
||||
PB12_PF_CSI_D2,
|
||||
|
|
@ -147,6 +149,24 @@ static struct gpio visstrim_m10_version_gpios[] = {
|
|||
{ MOTHERBOARD_BIT2, GPIOF_IN, "mother-version-2" },
|
||||
};
|
||||
|
||||
static const struct gpio visstrim_m10_gpios[] __initconst = {
|
||||
{
|
||||
.gpio = TVP5150_RSTN,
|
||||
.flags = GPIOF_DIR_OUT | GPIOF_INIT_HIGH,
|
||||
.label = "tvp5150_rstn",
|
||||
},
|
||||
{
|
||||
.gpio = TVP5150_PWDN,
|
||||
.flags = GPIOF_DIR_OUT | GPIOF_INIT_LOW,
|
||||
.label = "tvp5150_pwdn",
|
||||
},
|
||||
{
|
||||
.gpio = OTG_PHY_CS_GPIO,
|
||||
.flags = GPIOF_DIR_OUT | GPIOF_INIT_LOW,
|
||||
.label = "usbotg_cs",
|
||||
},
|
||||
};
|
||||
|
||||
/* Camera */
|
||||
static int visstrim_camera_power(struct device *dev, int on)
|
||||
{
|
||||
|
|
@ -190,13 +210,6 @@ static void __init visstrim_camera_init(void)
|
|||
struct platform_device *pdev;
|
||||
int dma;
|
||||
|
||||
/* Initialize tvp5150 gpios */
|
||||
mxc_gpio_mode(TVP5150_RSTN | GPIO_GPIO | GPIO_OUT);
|
||||
mxc_gpio_mode(TVP5150_PWDN | GPIO_GPIO | GPIO_OUT);
|
||||
gpio_set_value(TVP5150_RSTN, 1);
|
||||
gpio_set_value(TVP5150_PWDN, 0);
|
||||
ndelay(1);
|
||||
|
||||
gpio_set_value(TVP5150_PWDN, 1);
|
||||
ndelay(1);
|
||||
gpio_set_value(TVP5150_RSTN, 0);
|
||||
|
|
@ -377,10 +390,6 @@ static struct i2c_board_info visstrim_m10_i2c_devices[] = {
|
|||
/* USB OTG */
|
||||
static int otg_phy_init(struct platform_device *pdev)
|
||||
{
|
||||
gpio_set_value(OTG_PHY_CS_GPIO, 0);
|
||||
|
||||
mdelay(10);
|
||||
|
||||
return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
|
||||
}
|
||||
|
||||
|
|
@ -435,6 +444,11 @@ static void __init visstrim_m10_board_init(void)
|
|||
if (ret)
|
||||
pr_err("Failed to setup pins (%d)\n", ret);
|
||||
|
||||
ret = gpio_request_array(visstrim_m10_gpios,
|
||||
ARRAY_SIZE(visstrim_m10_gpios));
|
||||
if (ret)
|
||||
pr_err("Failed to request gpios (%d)\n", ret);
|
||||
|
||||
imx27_add_imx_ssi(0, &visstrim_m10_ssi_pdata);
|
||||
imx27_add_imx_uart0(&uart_pdata);
|
||||
|
||||
|
|
|
|||
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