(2.6.20) pata_mpiix: fix PIO setup issues
Fix clearing/setting the wrong TIME/IE/PPE bits for a slave drive caused by a wrong shift count. Fix the PIO mode 1 being overclocked by wrongly selecting the fast timing bank. Also, fix/rephrase some comments while at it. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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7b4f1a13f7
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@ -35,7 +35,7 @@
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#include <linux/libata.h>
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#include <linux/libata.h>
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#define DRV_NAME "pata_mpiix"
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#define DRV_NAME "pata_mpiix"
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#define DRV_VERSION "0.7.3"
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#define DRV_VERSION "0.7.4"
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enum {
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enum {
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IDETIM = 0x6C, /* IDE control register */
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IDETIM = 0x6C, /* IDE control register */
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@ -80,8 +80,8 @@ static void mpiix_error_handler(struct ata_port *ap)
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* @adev: ATA device
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* @adev: ATA device
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*
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*
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* Called to do the PIO mode setup. The MPIIX allows us to program the
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* Called to do the PIO mode setup. The MPIIX allows us to program the
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* IORDY sample point (2-5 clocks), recovery 1-4 clocks and whether
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* IORDY sample point (2-5 clocks), recovery (1-4 clocks) and whether
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* prefetching or iordy are used.
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* prefetching or IORDY are used.
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*
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*
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* This would get very ugly because we can only program timing for one
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* This would get very ugly because we can only program timing for one
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* device at a time, the other gets PIO0. Fortunately libata calls
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* device at a time, the other gets PIO0. Fortunately libata calls
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@ -103,18 +103,19 @@ static void mpiix_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{ 2, 3 }, };
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{ 2, 3 }, };
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pci_read_config_word(pdev, IDETIM, &idetim);
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pci_read_config_word(pdev, IDETIM, &idetim);
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/* Mask the IORDY/TIME/PPE0 bank for this device */
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/* Mask the IORDY/TIME/PPE for this device */
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if (adev->class == ATA_DEV_ATA)
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if (adev->class == ATA_DEV_ATA)
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control |= PPE; /* PPE enable for disk */
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control |= PPE; /* Enable prefetch/posting for disk */
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if (ata_pio_need_iordy(adev))
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if (ata_pio_need_iordy(adev))
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control |= IORDY; /* IORDY */
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control |= IORDY;
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if (pio > 0)
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if (pio > 1)
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control |= FTIM; /* This drive is on the fast timing bank */
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control |= FTIM; /* This drive is on the fast timing bank */
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/* Mask out timing and clear both TIME bank selects */
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/* Mask out timing and clear both TIME bank selects */
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idetim &= 0xCCEE;
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idetim &= 0xCCEE;
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idetim &= ~(0x07 << (2 * adev->devno));
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idetim &= ~(0x07 << (4 * adev->devno));
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idetim |= (control << (2 * adev->devno));
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idetim |= control << (4 * adev->devno);
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idetim |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
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idetim |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
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pci_write_config_word(pdev, IDETIM, idetim);
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pci_write_config_word(pdev, IDETIM, idetim);
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